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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -7 X-Spam_score: -0.8 X-Spam_bar: / X-Spam_report: (-0.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1, RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1775057463366158500 Add system event and cause code definitions needed for exception handling in sysemu mode. Add privilege checks that raise exceptions for guest/supervisor-only instructions executed without appropriate privilege. Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 10 +++++ target/hexagon/cpu_bits.h | 75 +++++++++++++++++++++++++++++---- linux-user/hexagon/cpu_loop.c | 16 +++++++ target/hexagon/cpu.c | 1 + target/hexagon/translate.c | 8 ++++ target/hexagon/gen_tcg_funcs.py | 35 +++++++++------ 6 files changed, 123 insertions(+), 22 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 85afd592778..937194e460e 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -44,6 +44,15 @@ =20 #define MMU_USER_IDX 0 =20 +#define HEXAGON_CPU_IRQ_0 0 +#define HEXAGON_CPU_IRQ_1 1 +#define HEXAGON_CPU_IRQ_2 2 +#define HEXAGON_CPU_IRQ_3 3 +#define HEXAGON_CPU_IRQ_4 4 +#define HEXAGON_CPU_IRQ_5 5 +#define HEXAGON_CPU_IRQ_6 6 +#define HEXAGON_CPU_IRQ_7 7 + typedef struct { target_ulong va; uint32_t width; @@ -76,6 +85,7 @@ typedef struct { typedef struct CPUArchState { target_ulong gpr[TOTAL_PER_THREAD_REGS]; target_ulong pred[NUM_PREGS]; + uint32_t cause_code; =20 /* For comparing with LLDB on target - see adjust_stack_ptrs function = */ target_ulong last_pc_dumped; diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h index 19beca81c0c..91e9da09e03 100644 --- a/target/hexagon/cpu_bits.h +++ b/target/hexagon/cpu_bits.h @@ -24,20 +24,77 @@ #define PCALIGN_MASK (PCALIGN - 1) =20 enum hex_event { - HEX_EVENT_NONE =3D -1, - HEX_EVENT_TRAP0 =3D 0x008, + HEX_EVENT_NONE =3D -1, + HEX_EVENT_RESET =3D 0x0, + HEX_EVENT_IMPRECISE =3D 0x1, + HEX_EVENT_PRECISE =3D 0x2, + HEX_EVENT_TLB_MISS_X =3D 0x4, + HEX_EVENT_TLB_MISS_RW =3D 0x6, + HEX_EVENT_TRAP0 =3D 0x8, + HEX_EVENT_TRAP1 =3D 0x9, + HEX_EVENT_FPTRAP =3D 0xb, + HEX_EVENT_DEBUG =3D 0xc, + HEX_EVENT_INT0 =3D 0x10, + HEX_EVENT_INT1 =3D 0x11, + HEX_EVENT_INT2 =3D 0x12, + HEX_EVENT_INT3 =3D 0x13, + HEX_EVENT_INT4 =3D 0x14, + HEX_EVENT_INT5 =3D 0x15, + HEX_EVENT_INT6 =3D 0x16, + HEX_EVENT_INT7 =3D 0x17, + HEX_EVENT_INT8 =3D 0x18, + HEX_EVENT_INT9 =3D 0x19, + HEX_EVENT_INTA =3D 0x1a, + HEX_EVENT_INTB =3D 0x1b, + HEX_EVENT_INTC =3D 0x1c, + HEX_EVENT_INTD =3D 0x1d, + HEX_EVENT_INTE =3D 0x1e, + HEX_EVENT_INTF =3D 0x1f, }; =20 enum hex_cause { HEX_CAUSE_NONE =3D -1, - HEX_CAUSE_TRAP0 =3D 0x172, - HEX_CAUSE_FETCH_NO_UPAGE =3D 0x012, - HEX_CAUSE_INVALID_PACKET =3D 0x015, - HEX_CAUSE_INVALID_OPCODE =3D 0x015, + HEX_CAUSE_RESET =3D 0x000, + HEX_CAUSE_BIU_PRECISE =3D 0x001, + HEX_CAUSE_UNSUPPORTED_HVX_64B =3D 0x002, /* QEMU-specific */ + HEX_CAUSE_DOUBLE_EXCEPT =3D 0x003, + HEX_CAUSE_TRAP0 =3D 0x008, + HEX_CAUSE_TRAP1 =3D 0x009, + HEX_CAUSE_FETCH_NO_XPAGE =3D 0x011, + HEX_CAUSE_FETCH_NO_UPAGE =3D 0x012, + HEX_CAUSE_INVALID_PACKET =3D 0x015, + HEX_CAUSE_INVALID_OPCODE =3D 0x015, /* alias: same cause as INVALID_PA= CKET */ + HEX_CAUSE_NO_COPROC_ENABLE =3D 0x016, + HEX_CAUSE_NO_COPROC2_ENABLE =3D 0x018, + HEX_CAUSE_PRIV_USER_NO_GINSN =3D 0x01a, + HEX_CAUSE_PRIV_USER_NO_SINSN =3D 0x01b, HEX_CAUSE_REG_WRITE_CONFLICT =3D 0x01d, - HEX_CAUSE_PC_NOT_ALIGNED =3D 0x01e, - HEX_CAUSE_PRIV_NO_UREAD =3D 0x024, - HEX_CAUSE_PRIV_NO_UWRITE =3D 0x025, + HEX_CAUSE_PC_NOT_ALIGNED =3D 0x01e, + HEX_CAUSE_MISALIGNED_LOAD =3D 0x020, + HEX_CAUSE_MISALIGNED_STORE =3D 0x021, + HEX_CAUSE_PRIV_NO_READ =3D 0x022, + HEX_CAUSE_PRIV_NO_WRITE =3D 0x023, + HEX_CAUSE_PRIV_NO_UREAD =3D 0x024, + HEX_CAUSE_PRIV_NO_UWRITE =3D 0x025, + HEX_CAUSE_COPROC_LDST =3D 0x026, + HEX_CAUSE_STACK_LIMIT =3D 0x027, + HEX_CAUSE_VWCTRL_WINDOW_MISS =3D 0x029, + HEX_CAUSE_IMPRECISE_NMI =3D 0x043, + HEX_CAUSE_IMPRECISE_MULTI_TLB_MATCH =3D 0x044, + HEX_CAUSE_TLBMISSX_CAUSE_NORMAL =3D 0x060, + HEX_CAUSE_TLBMISSX_CAUSE_NEXTPAGE =3D 0x061, + HEX_CAUSE_TLBMISSRW_CAUSE_READ =3D 0x070, + HEX_CAUSE_TLBMISSRW_CAUSE_WRITE =3D 0x071, + HEX_CAUSE_DEBUG_SINGLESTEP =3D 0x80, + HEX_CAUSE_FPTRAP_CAUSE_BADFLOAT =3D 0x0bf, + HEX_CAUSE_INT0 =3D 0x0c0, + HEX_CAUSE_INT1 =3D 0x0c1, + HEX_CAUSE_INT2 =3D 0x0c2, + HEX_CAUSE_INT3 =3D 0x0c3, + HEX_CAUSE_INT4 =3D 0x0c4, + HEX_CAUSE_INT5 =3D 0x0c5, + HEX_CAUSE_INT6 =3D 0x0c6, + HEX_CAUSE_INT7 =3D 0x0c7, }; =20 #define PACKET_WORDS_MAX 4 diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c index 9464246e9e3..9f54c7b3f96 100644 --- a/linux-user/hexagon/cpu_loop.c +++ b/linux-user/hexagon/cpu_loop.c @@ -22,6 +22,7 @@ #include "qemu.h" #include "user-internals.h" #include "user/cpu_loop.h" +#include "target/hexagon/internal.h" #include "signal-common.h" #include "internal.h" =20 @@ -60,6 +61,21 @@ void cpu_loop(CPUHexagonState *env) env->gpr[0] =3D ret; } break; + case HEX_EVENT_PRECISE: + switch (env->cause_code) { + case HEX_CAUSE_PRIV_USER_NO_GINSN: + case HEX_CAUSE_PRIV_USER_NO_SINSN: + case HEX_CAUSE_INVALID_PACKET: + force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, + env->gpr[HEX_REG_PC]); + break; + default: + EXCP_DUMP(env, "\nqemu: unhandled CPU precise exception " + "cause code 0x%x - aborting\n", + env->cause_code); + exit(EXIT_FAILURE); + } + break; case HEX_CAUSE_PC_NOT_ALIGNED: force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN, env->gpr[HEX_REG_R31]); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 4f72d4759cf..a4dcad5f7a5 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -306,6 +306,7 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetTy= pe type) set_float_detect_tininess(float_tininess_before_rounding, &env->fp_sta= tus); /* Default NaN value: sign bit set, all frac bits set */ set_float_default_nan_pattern(0b11111111, &env->fp_status); + env->cause_code =3D HEX_EVENT_NONE; } =20 static void hexagon_cpu_disas_set_info(const CPUState *cs, diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 1f4ac2c3c84..c947db85ab7 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -65,6 +65,10 @@ TCGv hex_vstore_addr[VSTORES_MAX]; TCGv hex_vstore_size[VSTORES_MAX]; TCGv hex_vstore_pending[VSTORES_MAX]; =20 +#ifndef CONFIG_USER_ONLY +TCGv_i32 hex_cause_code; +#endif + static const char * const hexagon_prednames[] =3D { "p0", "p1", "p2", "p3" }; @@ -1153,4 +1157,8 @@ void hexagon_translate_init(void) offsetof(CPUHexagonState, vstore_pending[i]), vstore_pending_names[i]); } +#ifndef CONFIG_USER_ONLY + hex_cause_code =3D tcg_global_mem_new(tcg_env, + offsetof(CPUHexagonState, cause_code), "cause_code"); +#endif } diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs= .py index 87b7f10d7fd..d91bbcf1dc8 100755 --- a/target/hexagon/gen_tcg_funcs.py +++ b/target/hexagon/gen_tcg_funcs.py @@ -21,7 +21,7 @@ import re import string import hex_common - +from textwrap import dedent =20 ## ## Generate the TCG code to call the helper @@ -49,6 +49,18 @@ def gen_tcg_func(f, tag, regs, imms): =20 f.write(" Insn *insn G_GNUC_UNUSED =3D ctx->insn;\n") =20 + if "A_PRIV" in hex_common.attribdict[tag]: + f.write(dedent("""\ +#ifdef CONFIG_USER_ONLY + hex_gen_exception_end_tb(ctx, HEX_CAUSE_PRIV_USER_NO_SINSN); +#else +""")) + if "A_GUEST" in hex_common.attribdict[tag]: + f.write(dedent("""\ +#ifdef CONFIG_USER_ONLY + hex_gen_exception_end_tb(ctx, HEX_CAUSE_PRIV_USER_NO_GINSN); +#else +""")) if hex_common.need_ea(tag): f.write(" TCGv EA G_GNUC_UNUSED =3D tcg_temp_new();\n") =20 @@ -100,6 +112,11 @@ def gen_tcg_func(f, tag, regs, imms): if reg.is_written(): reg.gen_write(f, tag) =20 + if ( + "A_PRIV" in hex_common.attribdict[tag] + or "A_GUEST" in hex_common.attribdict[tag] + ): + f.write("#endif /* CONFIG_USER_ONLY */\n") f.write("}\n\n") =20 =20 @@ -124,18 +141,10 @@ def main(): f.write('#include "idef-generated-emitter.h.inc"\n\n') =20 for tag in hex_common.tags: - ## Skip the priv instructions - if "A_PRIV" in hex_common.attribdict[tag]: - continue - ## Skip the guest instructions - if "A_GUEST" in hex_common.attribdict[tag]: - continue - ## Skip the diag instructions - if tag =3D=3D "Y6_diag": - continue - if tag =3D=3D "Y6_diag0": - continue - if tag =3D=3D "Y6_diag1": + if hex_common.tag_ignore(tag): + f.write(f"static void generate_{tag}" + f"(DisasContext *ctx)\n") + f.write("{\n}\n\n") continue =20 gen_def_tcg_func(f, tag, tagregs, tagimms) --=20 2.34.1