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Use the latter which is more explicit. Mechanical changes. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/mips/tcg/lcsr_translate.c | 16 +++--- target/mips/tcg/loong_translate.c | 92 +++++++++++++++--------------- target/mips/tcg/octeon_translate.c | 60 +++++++++---------- target/mips/tcg/tx79_translate.c | 14 ++--- 4 files changed, 91 insertions(+), 91 deletions(-) diff --git a/target/mips/tcg/lcsr_translate.c b/target/mips/tcg/lcsr_transl= ate.c index 352b0f43282..128c17a9181 100644 --- a/target/mips/tcg/lcsr_translate.c +++ b/target/mips/tcg/lcsr_translate.c @@ -18,8 +18,8 @@ =20 static bool trans_CPUCFG(DisasContext *ctx, arg_CPUCFG *a) { - TCGv dest =3D tcg_temp_new(); - TCGv src1 =3D tcg_temp_new(); + TCGv_i64 dest =3D tcg_temp_new_i64(); + TCGv_i64 src1 =3D tcg_temp_new_i64(); =20 gen_load_gpr(src1, a->rs); gen_helper_lcsr_cpucfg(dest, tcg_env, src1); @@ -30,10 +30,10 @@ static bool trans_CPUCFG(DisasContext *ctx, arg_CPUCFG = *a) =20 #ifndef CONFIG_USER_ONLY static bool gen_rdcsr(DisasContext *ctx, arg_r *a, - void (*func)(TCGv, TCGv_ptr, TCGv)) + void (*func)(TCGv_i64, TCGv_ptr, TCGv_i64)) { - TCGv dest =3D tcg_temp_new(); - TCGv src1 =3D tcg_temp_new(); + TCGv_i64 dest =3D tcg_temp_new_i64(); + TCGv_i64 src1 =3D tcg_temp_new_i64(); =20 check_cp0_enabled(ctx); gen_load_gpr(src1, a->rs); @@ -44,10 +44,10 @@ static bool gen_rdcsr(DisasContext *ctx, arg_r *a, } =20 static bool gen_wrcsr(DisasContext *ctx, arg_r *a, - void (*func)(TCGv_ptr, TCGv, TCGv)) + void (*func)(TCGv_ptr, TCGv_i64, TCGv_i64)) { - TCGv val =3D tcg_temp_new(); - TCGv addr =3D tcg_temp_new(); + TCGv_i64 val =3D tcg_temp_new_i64(); + TCGv_i64 addr =3D tcg_temp_new_i64(); =20 check_cp0_enabled(ctx); gen_load_gpr(addr, a->rs); diff --git a/target/mips/tcg/loong_translate.c b/target/mips/tcg/loong_tran= slate.c index 7d74cc34f8a..797e3b5f721 100644 --- a/target/mips/tcg/loong_translate.c +++ b/target/mips/tcg/loong_translate.c @@ -28,7 +28,7 @@ static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt, bool is_double) { - TCGv t0, t1; + TCGv_i64 t0, t1; TCGLabel *l1, *l2, *l3; =20 if (rd =3D=3D 0) { @@ -36,8 +36,8 @@ static bool gen_lext_DIV_G(DisasContext *s, int rd, int r= s, int rt, return true; } =20 - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); l1 =3D gen_new_label(); l2 =3D gen_new_label(); l3 =3D gen_new_label(); @@ -46,23 +46,23 @@ static bool gen_lext_DIV_G(DisasContext *s, int rd, int= rs, int rt, gen_load_gpr(t1, rt); =20 if (!is_double) { - tcg_gen_ext32s_tl(t0, t0); - tcg_gen_ext32s_tl(t1, t1); + tcg_gen_ext32s_i64(t0, t0); + tcg_gen_ext32s_i64(t1, t1); } - tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); - tcg_gen_movi_tl(cpu_gpr[rd], 0); + tcg_gen_brcondi_i64(TCG_COND_NE, t1, 0, l1); + tcg_gen_movi_i64(cpu_gpr[rd], 0); tcg_gen_br(l3); gen_set_label(l1); =20 - tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double ? LLONG_MIN : INT_MIN, l= 2); - tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); - tcg_gen_mov_tl(cpu_gpr[rd], t0); + tcg_gen_brcondi_i64(TCG_COND_NE, t0, is_double ? LLONG_MIN : INT_MIN, = l2); + tcg_gen_brcondi_i64(TCG_COND_NE, t1, -1LL, l2); + tcg_gen_mov_i64(cpu_gpr[rd], t0); =20 tcg_gen_br(l3); gen_set_label(l2); - tcg_gen_div_tl(cpu_gpr[rd], t0, t1); + tcg_gen_div_i64(cpu_gpr[rd], t0, t1); if (!is_double) { - tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + tcg_gen_ext32s_i64(cpu_gpr[rd], cpu_gpr[rd]); } gen_set_label(l3); =20 @@ -82,7 +82,7 @@ static bool trans_DDIV_G(DisasContext *s, arg_muldiv *a) static bool gen_lext_DIVU_G(DisasContext *s, int rd, int rs, int rt, bool is_double) { - TCGv t0, t1; + TCGv_i64 t0, t1; TCGLabel *l1, *l2; =20 if (rd =3D=3D 0) { @@ -90,8 +90,8 @@ static bool gen_lext_DIVU_G(DisasContext *s, int rd, int = rs, int rt, return true; } =20 - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); l1 =3D gen_new_label(); l2 =3D gen_new_label(); =20 @@ -99,17 +99,17 @@ static bool gen_lext_DIVU_G(DisasContext *s, int rd, in= t rs, int rt, gen_load_gpr(t1, rt); =20 if (!is_double) { - tcg_gen_ext32u_tl(t0, t0); - tcg_gen_ext32u_tl(t1, t1); + tcg_gen_ext32u_i64(t0, t0); + tcg_gen_ext32u_i64(t1, t1); } - tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); - tcg_gen_movi_tl(cpu_gpr[rd], 0); + tcg_gen_brcondi_i64(TCG_COND_NE, t1, 0, l1); + tcg_gen_movi_i64(cpu_gpr[rd], 0); =20 tcg_gen_br(l2); gen_set_label(l1); - tcg_gen_divu_tl(cpu_gpr[rd], t0, t1); + tcg_gen_divu_i64(cpu_gpr[rd], t0, t1); if (!is_double) { - tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + tcg_gen_ext32s_i64(cpu_gpr[rd], cpu_gpr[rd]); } gen_set_label(l2); =20 @@ -129,7 +129,7 @@ static bool trans_DDIVU_G(DisasContext *s, arg_muldiv *= a) static bool gen_lext_MOD_G(DisasContext *s, int rd, int rs, int rt, bool is_double) { - TCGv t0, t1; + TCGv_i64 t0, t1; TCGLabel *l1, *l2, *l3; =20 if (rd =3D=3D 0) { @@ -137,8 +137,8 @@ static bool gen_lext_MOD_G(DisasContext *s, int rd, int= rs, int rt, return true; } =20 - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); l1 =3D gen_new_label(); l2 =3D gen_new_label(); l3 =3D gen_new_label(); @@ -147,19 +147,19 @@ static bool gen_lext_MOD_G(DisasContext *s, int rd, i= nt rs, int rt, gen_load_gpr(t1, rt); =20 if (!is_double) { - tcg_gen_ext32u_tl(t0, t0); - tcg_gen_ext32u_tl(t1, t1); + tcg_gen_ext32u_i64(t0, t0); + tcg_gen_ext32u_i64(t1, t1); } - tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); - tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double ? LLONG_MIN : INT_MIN, l= 2); - tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); + tcg_gen_brcondi_i64(TCG_COND_EQ, t1, 0, l1); + tcg_gen_brcondi_i64(TCG_COND_NE, t0, is_double ? LLONG_MIN : INT_MIN, = l2); + tcg_gen_brcondi_i64(TCG_COND_NE, t1, -1LL, l2); gen_set_label(l1); - tcg_gen_movi_tl(cpu_gpr[rd], 0); + tcg_gen_movi_i64(cpu_gpr[rd], 0); tcg_gen_br(l3); gen_set_label(l2); - tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); + tcg_gen_rem_i64(cpu_gpr[rd], t0, t1); if (!is_double) { - tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + tcg_gen_ext32s_i64(cpu_gpr[rd], cpu_gpr[rd]); } gen_set_label(l3); =20 @@ -179,7 +179,7 @@ static bool trans_DMOD_G(DisasContext *s, arg_muldiv *a) static bool gen_lext_MODU_G(DisasContext *s, int rd, int rs, int rt, bool is_double) { - TCGv t0, t1; + TCGv_i64 t0, t1; TCGLabel *l1, *l2; =20 if (rd =3D=3D 0) { @@ -187,8 +187,8 @@ static bool gen_lext_MODU_G(DisasContext *s, int rd, in= t rs, int rt, return true; } =20 - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); l1 =3D gen_new_label(); l2 =3D gen_new_label(); =20 @@ -196,16 +196,16 @@ static bool gen_lext_MODU_G(DisasContext *s, int rd, = int rs, int rt, gen_load_gpr(t1, rt); =20 if (!is_double) { - tcg_gen_ext32u_tl(t0, t0); - tcg_gen_ext32u_tl(t1, t1); + tcg_gen_ext32u_i64(t0, t0); + tcg_gen_ext32u_i64(t1, t1); } - tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); - tcg_gen_movi_tl(cpu_gpr[rd], 0); + tcg_gen_brcondi_i64(TCG_COND_NE, t1, 0, l1); + tcg_gen_movi_i64(cpu_gpr[rd], 0); tcg_gen_br(l2); gen_set_label(l1); - tcg_gen_remu_tl(cpu_gpr[rd], t0, t1); + tcg_gen_remu_i64(cpu_gpr[rd], t0, t1); if (!is_double) { - tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + tcg_gen_ext32s_i64(cpu_gpr[rd], cpu_gpr[rd]); } gen_set_label(l2); =20 @@ -225,22 +225,22 @@ static bool trans_DMODU_G(DisasContext *s, arg_muldiv= *a) static bool gen_lext_MULT_G(DisasContext *s, int rd, int rs, int rt, bool is_double) { - TCGv t0, t1; + TCGv_i64 t0, t1; =20 if (rd =3D=3D 0) { /* Treat as NOP. */ return true; } =20 - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); =20 gen_load_gpr(t0, rs); gen_load_gpr(t1, rt); =20 - tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); + tcg_gen_mul_i64(cpu_gpr[rd], t0, t1); if (!is_double) { - tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + tcg_gen_ext32s_i64(cpu_gpr[rd], cpu_gpr[rd]); } =20 return true; diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_tr= anslate.c index b2eca29e06c..e1f52d444aa 100644 --- a/target/mips/tcg/octeon_translate.c +++ b/target/mips/tcg/octeon_translate.c @@ -15,7 +15,7 @@ =20 static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a) { - TCGv p; + TCGv_i64 p; =20 if (ctx->hflags & MIPS_HFLAG_BMASK) { LOG_DISAS("Branch in delay / forbidden slot at PC 0x%" VADDR_PRIx = "\n", @@ -25,14 +25,14 @@ static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a) } =20 /* Load needed operands */ - TCGv t0 =3D tcg_temp_new(); + TCGv_i64 t0 =3D tcg_temp_new_i64(); gen_load_gpr(t0, a->rs); =20 - p =3D tcg_constant_tl(1ULL << a->p); + p =3D tcg_constant_i64(1ULL << a->p); if (a->set) { - tcg_gen_and_tl(bcond, p, t0); + tcg_gen_and_i64(bcond, p, t0); } else { - tcg_gen_andc_tl(bcond, p, t0); + tcg_gen_andc_i64(bcond, p, t0); } =20 ctx->hflags |=3D MIPS_HFLAG_BC; @@ -43,34 +43,34 @@ static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a) =20 static bool trans_BADDU(DisasContext *ctx, arg_BADDU *a) { - TCGv t0, t1; + TCGv_i64 t0, t1; =20 if (a->rt =3D=3D 0) { /* nop */ return true; } =20 - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); gen_load_gpr(t0, a->rs); gen_load_gpr(t1, a->rt); =20 - tcg_gen_add_tl(t0, t0, t1); + tcg_gen_add_i64(t0, t0, t1); tcg_gen_andi_i64(cpu_gpr[a->rd], t0, 0xff); return true; } =20 static bool trans_DMUL(DisasContext *ctx, arg_DMUL *a) { - TCGv t0, t1; + TCGv_i64 t0, t1; =20 if (a->rt =3D=3D 0) { /* nop */ return true; } =20 - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); gen_load_gpr(t0, a->rs); gen_load_gpr(t1, a->rt); =20 @@ -80,97 +80,97 @@ static bool trans_DMUL(DisasContext *ctx, arg_DMUL *a) =20 static bool trans_EXTS(DisasContext *ctx, arg_EXTS *a) { - TCGv t0; + TCGv_i64 t0; =20 if (a->rt =3D=3D 0) { /* nop */ return true; } =20 - t0 =3D tcg_temp_new(); + t0 =3D tcg_temp_new_i64(); gen_load_gpr(t0, a->rs); - tcg_gen_sextract_tl(t0, t0, a->p, a->lenm1 + 1); + tcg_gen_sextract_i64(t0, t0, a->p, a->lenm1 + 1); gen_store_gpr(t0, a->rt); return true; } =20 static bool trans_CINS(DisasContext *ctx, arg_CINS *a) { - TCGv t0; + TCGv_i64 t0; =20 if (a->rt =3D=3D 0) { /* nop */ return true; } =20 - t0 =3D tcg_temp_new(); + t0 =3D tcg_temp_new_i64(); gen_load_gpr(t0, a->rs); - tcg_gen_deposit_z_tl(t0, t0, a->p, a->lenm1 + 1); + tcg_gen_deposit_z_i64(t0, t0, a->p, a->lenm1 + 1); gen_store_gpr(t0, a->rt); return true; } =20 static bool trans_POP(DisasContext *ctx, arg_POP *a) { - TCGv t0; + TCGv_i64 t0; =20 if (a->rd =3D=3D 0) { /* nop */ return true; } =20 - t0 =3D tcg_temp_new(); + t0 =3D tcg_temp_new_i64(); gen_load_gpr(t0, a->rs); if (!a->dw) { tcg_gen_andi_i64(t0, t0, 0xffffffff); } - tcg_gen_ctpop_tl(t0, t0); + tcg_gen_ctpop_i64(t0, t0); gen_store_gpr(t0, a->rd); return true; } =20 static bool trans_SEQNE(DisasContext *ctx, arg_SEQNE *a) { - TCGv t0, t1; + TCGv_i64 t0, t1; =20 if (a->rd =3D=3D 0) { /* nop */ return true; } =20 - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); =20 gen_load_gpr(t0, a->rs); gen_load_gpr(t1, a->rt); =20 if (a->ne) { - tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr[a->rd], t1, t0); + tcg_gen_setcond_i64(TCG_COND_NE, cpu_gpr[a->rd], t1, t0); } else { - tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr[a->rd], t1, t0); + tcg_gen_setcond_i64(TCG_COND_EQ, cpu_gpr[a->rd], t1, t0); } return true; } =20 static bool trans_SEQNEI(DisasContext *ctx, arg_SEQNEI *a) { - TCGv t0; + TCGv_i64 t0; =20 if (a->rt =3D=3D 0) { /* nop */ return true; } =20 - t0 =3D tcg_temp_new(); + t0 =3D tcg_temp_new_i64(); =20 gen_load_gpr(t0, a->rs); =20 /* Sign-extend to 64 bit value */ target_ulong imm =3D a->imm; if (a->ne) { - tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr[a->rt], t0, imm); + tcg_gen_setcondi_i64(TCG_COND_NE, cpu_gpr[a->rt], t0, imm); } else { - tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr[a->rt], t0, imm); + tcg_gen_setcondi_i64(TCG_COND_EQ, cpu_gpr[a->rt], t0, imm); } return true; } diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_transl= ate.c index ae3f5e19c43..e071c867631 100644 --- a/target/mips/tcg/tx79_translate.c +++ b/target/mips/tcg/tx79_translate.c @@ -241,8 +241,8 @@ static bool trans_parallel_compare(DisasContext *ctx, a= rg_r *a, return true; } =20 - c0 =3D tcg_constant_tl(0); - c1 =3D tcg_constant_tl(0xffffffff); + c0 =3D tcg_constant_i64(0); + c1 =3D tcg_constant_i64(0xffffffff); ax =3D tcg_temp_new_i64(); bx =3D tcg_temp_new_i64(); t0 =3D tcg_temp_new_i64(); @@ -322,7 +322,7 @@ static bool trans_PCEQW(DisasContext *ctx, arg_r *a) static bool trans_LQ(DisasContext *ctx, arg_i *a) { TCGv_i64 t0; - TCGv addr; + TCGv_i64 addr; =20 if (a->rt =3D=3D 0) { /* nop */ @@ -330,14 +330,14 @@ static bool trans_LQ(DisasContext *ctx, arg_i *a) } =20 t0 =3D tcg_temp_new_i64(); - addr =3D tcg_temp_new(); + addr =3D tcg_temp_new_i64(); =20 gen_base_offset_addr(ctx, addr, a->base, a->offset); /* * Clear least-significant four bits of the effective * address, effectively creating an aligned address. */ - tcg_gen_andi_tl(addr, addr, ~0xf); + tcg_gen_andi_i64(addr, addr, ~0xf); =20 /* Lower half */ tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, mo_endian(ctx) | MO_UQ); @@ -353,14 +353,14 @@ static bool trans_LQ(DisasContext *ctx, arg_i *a) static bool trans_SQ(DisasContext *ctx, arg_i *a) { TCGv_i64 t0 =3D tcg_temp_new_i64(); - TCGv addr =3D tcg_temp_new(); + TCGv_i64 addr =3D tcg_temp_new_i64(); =20 gen_base_offset_addr(ctx, addr, a->base, a->offset); /* * Clear least-significant four bits of the effective * address, effectively creating an aligned address. */ - tcg_gen_andi_tl(addr, addr, ~0xf); + tcg_gen_andi_i64(addr, addr, ~0xf); =20 /* Lower half */ gen_load_gpr(t0, a->rt); --=20 2.53.0