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b=TK3mivj3LLs2ce0DucuyX+hDJyClfZRI22ca/OPzTdkF4wWszCEMuIni5eBwhoMNSKwuEU9qG+yijgoTwKAa4QtAhVsbee8scy8PFz/8G1wvozhr53LGctp8nFmI8zBwpJ/SFaeAsl8qyWmWz6ZtIBHCCkFjE8kQXzLRpvrRDtz9o7fQhv269MWNwLabtKhbc44FDlczdQvOdi/WxnUyGhJz7KBEujct37LtX06zxSKjnn0aWbV2odFfONmfzwnz48AgVMu/CF96JDMFRGuGfOvAnucdQ4Z0nqytVMKwP2eUNVufYUP1JehVxr2oIMDbD9mvli3TQzNbFkf69kDErQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; From: Nathan Chen To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Yi Liu , Eric Auger , Zhenzhong Duan , Peter Maydell , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Zhao Liu , Alex Williamson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Shameer Kolothum , Matt Ochs , Nicolin Chen , Nathan Chen Subject: [PATCH 05/11] hw/arm/smmuv3-accel: Implement "auto" value for "ril" Date: Tue, 31 Mar 2026 18:02:25 -0700 Message-ID: <20260401010231.4166776-6-nathanc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260401010231.4166776-1-nathanc@nvidia.com> References: <20260401010231.4166776-1-nathanc@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ2PR07CA0011.namprd07.prod.outlook.com (2603:10b6:a03:505::20) To DS2PR12MB9567.namprd12.prod.outlook.com (2603:10b6:8:27c::8) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PR12MB9567:EE_|CH1PR12MB9647:EE_ X-MS-Office365-Filtering-Correlation-Id: fa383eba-d1ab-429f-a337-08de8f8a61a5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c111::5; envelope-from=nathanc@nvidia.com; helo=DM1PR04CU001.outbound.protection.outlook.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1775005546783154100 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Allow accelerated SMMUv3 Range Invalidation support property to be derived from host IOMMU capabilities. Derive host values using IOMMU_GET_HW_INFO, retrieving RIL capability from IDR3. Signed-off-by: Nathan Chen --- hw/arm/smmuv3-accel.c | 9 ++++++++- hw/arm/smmuv3.c | 7 +------ 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index a835c8f220..9e7ec6a930 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -50,6 +50,12 @@ static void smmuv3_accel_auto_finalise(SMMUv3State *s, FIELD_EX32(info->idr[0], IDR0, ATS)); } =20 + /* Update RIL if auto from info */ + if (s->ril =3D=3D ON_OFF_AUTO_AUTO) { + s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, + FIELD_EX32(info->idr[3], IDR3, RIL)); + } + accel->auto_finalised =3D true; } =20 @@ -945,7 +951,8 @@ void smmuv3_accel_init(SMMUv3State *s) bs->iommu_ops =3D &smmuv3_accel_ops; smmuv3_accel_as_init(s); =20 - if (s->ats =3D=3D ON_OFF_AUTO_AUTO) { + if (s->ats =3D=3D ON_OFF_AUTO_AUTO || + s->ril =3D=3D ON_OFF_AUTO_AUTO) { s->s_accel->auto_mode =3D true; } } diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index f353865187..a2d2f0e3bc 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1973,10 +1973,6 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) } #endif =20 - if (s->ril =3D=3D ON_OFF_AUTO_AUTO) { - error_setg(errp, "ril auto mode is not supported"); - return false; - } if (s->ssidsize =3D=3D SSID_SIZE_MODE_AUTO) { error_setg(errp, "ssidsize auto mode is not supported"); return false; @@ -2188,8 +2184,7 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) "Enable SMMUv3 accelerator support. Allows host SMMUv3 to be " "configured in nested mode for vfio-pci dev assignment"); object_class_property_set_description(klass, "ril", - "Disable range invalidation support (for accel=3Don). ril=3Dauto " - "is not supported."); + "Disable range invalidation support (for accel=3Don)."); object_class_property_set_description(klass, "ats", "Enable/disable ATS support (for accel=3Don). Please ensure host " "platform has ATS support before enabling this."); --=20 2.43.0