From nobody Wed Apr 1 23:52:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774930168536757.3942270728475; Mon, 30 Mar 2026 21:09:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w7QOZ-0001BC-WB; Tue, 31 Mar 2026 00:08:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w7QON-000102-DI; Tue, 31 Mar 2026 00:07:51 -0400 Received: from sgoci-sdnproxy-4.icoremail.net ([129.150.39.64]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w7QOI-0002F2-MM; Tue, 31 Mar 2026 00:07:51 -0400 Received: from prodtpl.icoremail.net (unknown [10.12.1.20]) by hzbj-icmmx-6 (Coremail) with SMTP id AQAAfwDn7qKFSMtpdcg9AA--.20365S2; Tue, 31 Mar 2026 12:07:33 +0800 (CST) Received: from phytium.com.cn (unknown [218.76.62.144]) by mail (Coremail) with SMTP id AQAAf8DwSJR6SMtpYqQHAA--.18366S4; Tue, 31 Mar 2026 12:07:28 +0800 (CST) From: Tao Tang To: Fabiano Rosas , Laurent Vivier , Paolo Bonzini Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Peter Maydell , Chen Baozi , Pierrick Bouvier , Chao Liu , Tao Tang Subject: [PATCH 1/4] tests/qtest: Add attrs support to qtest server memory commands Date: Tue, 31 Mar 2026 12:06:56 +0800 Message-Id: <20260331040659.401397-2-tangtao1634@phytium.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260331040659.401397-1-tangtao1634@phytium.com.cn> References: <20260331040659.401397-1-tangtao1634@phytium.com.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8DwSJR6SMtpYqQHAA--.18366S4 X-CM-SenderInfo: pwdqw3tdrrljuu6sx5pwlxzhxfrphubq/1tbiAQAKBWnJfH8GCQACsg Authentication-Results: hzbj-icmmx-6; spf=neutral smtp.mail=tangtao163 4@phytium.com.cn; X-Coremail-Antispam: 1Uk129KBjvAXoW3uryrCryftrykCrW3tw4DCFg_yoW8Wry7Zo WfKFnIya4Ut3Z7Cr929r1DJ34DXay5ur1DAwsYywn8Kay8Wryq9a98JFsxWa4jqayrGryk X3WfXr4fXFy0v397n29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXasCq-sGcSsGvf J3UbIjqfuFe4nvWSU8nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UU UUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=129.150.39.64; envelope-from=tangtao1634@phytium.com.cn; helo=sgoci-sdnproxy-4.icoremail.net X-Spam_score_int: 1 X-Spam_score: 0.1 X-Spam_bar: / X-Spam_report: (0.1 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1, RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, WEIRD_QUOTING=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1774930170184154100 Content-Type: text/plain; charset="utf-8" Extend qtest memory access commands to accept an optional attrs argument. Supported attrs: - secure (x86/Arm) - space=3Dnon-secure|secure|root|realm (Arm-only) For memory commands, parse attrs, select the corresponding AddressSpace with cpu_asidx_from_attrs(), and issue accesses with the matching MemTxAttrs. Cover scalar and bulk memory commands, including: - read{b,w,l,q} / write{b,w,l,q} - read / write - b64read / b64write - memset Also reject invalid attrs and excessive arguments, and document the new command forms in qtest.c, and use qtest_send_memtx_error() to return ERR for memory access failures. Preserve legacy no-attrs semantics for compatibility: those commands continue to ignore MemTxResult and return OK. Signed-off-by: Tao Tang --- system/qtest.c | 420 +++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 368 insertions(+), 52 deletions(-) diff --git a/system/qtest.c b/system/qtest.c index cf90cd53ad..f330c158d0 100644 --- a/system/qtest.c +++ b/system/qtest.c @@ -22,6 +22,7 @@ #include "hw/core/qdev.h" #include "hw/core/irq.h" #include "hw/core/cpu.h" +#include "hw/arm/arm-security.h" #include "qemu/accel.h" #include "system/cpu-timers.h" #include "qemu/config-file.h" @@ -113,6 +114,14 @@ static void *qtest_server_send_opaque; * PIO and memory access: * """""""""""""""""""""" * + * Memory access commands allow specifying memory transaction attributes, + * which is useful for testing devices that behave differently based on + * security state (e.g., Arm TrustZone/CCA or System Management Mode in x8= 6). + * + * Only the following attributes are supported by the qtest server: + * ``secure`` sets MemTxAttrs.secure=3D1 (x86/Arm). + * ``space=3D...`` is Arm-specific and accepts: non-secure, secure, root, = realm. + * * .. code-block:: none * * > outb ADDR VALUE @@ -208,6 +217,36 @@ static void *qtest_server_send_opaque; * > memset ADDR SIZE VALUE * < OK * + * Memory commands accept an optional ATTRS argument after their existing + * operands: + * + * .. code-block:: none + * + * > read{b,w,l,q} ADDR [ATTRS] + * > write{b,w,l,q} ADDR VALUE [ATTRS] + * > read ADDR SIZE [ATTRS] + * > write ADDR SIZE DATA [ATTRS] + * > b64read ADDR SIZE [ATTRS] + * > b64write ADDR SIZE B64_DATA [ATTRS] + * > memset ADDR SIZE VALUE [ATTRS] + * + * Representative examples: + * + * .. code-block:: none + * + * > readl ADDR secure + * < OK VALUE + * + * .. code-block:: none + * + * > b64read ADDR SIZE space=3Droot + * < OK B64_DATA + * + * .. code-block:: none + * + * > writeq ADDR VALUE space=3Drealm + * < OK + * * ADDR, SIZE, VALUE are all integers parsed with strtoul() with a base of= 0. * For 'memset' a zero size is permitted and does nothing. * @@ -353,6 +392,141 @@ static void qtest_install_gpio_out_intercept(DeviceSt= ate *dev, const char *name, *disconnected =3D qdev_intercept_gpio_out(dev, icpt, name, n); } =20 +static bool qtest_parse_mem_attrs(CharFrontend *chr, const char *arg, + MemTxAttrs *attrs) +{ + if (!arg) { + *attrs =3D MEMTXATTRS_UNSPECIFIED; + return true; + } + + if (strcmp(arg, "secure") =3D=3D 0) { + *attrs =3D (MemTxAttrs){ .secure =3D 1 }; + return true; + } + + if (strncmp(arg, "space=3D", 6) =3D=3D 0) { + const char *space =3D arg + 6; + ARMSecuritySpace sec_space; + + if (!target_arm() && !target_aarch64()) { + qtest_send(chr, "ERR space=3D<...> is Arm-specific\n"); + return false; + } + + if (strcmp(space, "non-secure") =3D=3D 0) { + sec_space =3D ARMSS_NonSecure; + } else if (strcmp(space, "secure") =3D=3D 0) { + sec_space =3D ARMSS_Secure; + } else if (strcmp(space, "root") =3D=3D 0) { + sec_space =3D ARMSS_Root; + } else if (strcmp(space, "realm") =3D=3D 0) { + sec_space =3D ARMSS_Realm; + } else { + qtest_send(chr, "ERR invalid space value. Valid space: " + "secure/non-secure/root/realm\n"); + return false; + } + + *attrs =3D (MemTxAttrs){ + .space =3D sec_space, + .secure =3D arm_space_is_secure(sec_space), + }; + return true; + } + + qtest_send(chr, "ERR invalid attrs argument\n"); + return false; +} + +static bool qtest_get_mem_as(CharFrontend *chr, MemTxAttrs attrs, + AddressSpace **as) +{ + int asidx; + + /* + * cpu_asidx_from_attrs mainly uses attrs to call ->asidx_from_attrs. = We use + * first_cpu as it's readily available. + */ + + asidx =3D cpu_asidx_from_attrs(first_cpu, attrs); + *as =3D cpu_get_address_space(first_cpu, asidx); + if (!*as) { + qtest_send(chr, "ERR address space unavailable for attrs\n"); + return false; + } + + return true; +} + +static void qtest_send_memtx_error(CharFrontend *chr, MemTxResult result) +{ + qtest_sendf(chr, "ERR memory access failed 0x%x\n", result); +} + +static MemTxResult qtest_write_sized(AddressSpace *as, uint64_t addr, + MemTxAttrs attrs, uint64_t value, + char size) +{ + switch (size) { + case 'b': { + uint8_t data =3D value; + return address_space_write(as, addr, attrs, &data, 1); + } + case 'w': { + uint16_t data =3D value; + tswap16s(&data); + return address_space_write(as, addr, attrs, &data, 2); + } + case 'l': { + uint32_t data =3D value; + tswap32s(&data); + return address_space_write(as, addr, attrs, &data, 4); + } + case 'q': { + uint64_t data =3D value; + tswap64s(&data); + return address_space_write(as, addr, attrs, &data, 8); + } + default: + g_assert_not_reached(); + } +} + +static MemTxResult qtest_read_sized(AddressSpace *as, uint64_t addr, + MemTxAttrs attrs, char size, + uint64_t *value) +{ + switch (size) { + case 'b': { + uint8_t data =3D 0; + MemTxResult result =3D address_space_read(as, addr, attrs, &data, = 1); + *value =3D data; + return result; + } + case 'w': { + uint16_t data =3D 0; + MemTxResult result =3D address_space_read(as, addr, attrs, &data, = 2); + *value =3D tswap16(data); + return result; + } + case 'l': { + uint32_t data =3D 0; + MemTxResult result =3D address_space_read(as, addr, attrs, &data, = 4); + *value =3D tswap32(data); + return result; + } + case 'q': { + uint64_t data =3D 0; + MemTxResult result =3D address_space_read(as, addr, attrs, &data, = 8); + *value =3D tswap64(data); + return result; + } + default: + g_assert_not_reached(); + } +} + static void qtest_process_command(CharFrontend *chr, gchar **words) { const gchar *command; @@ -510,33 +684,38 @@ static void qtest_process_command(CharFrontend *chr, = gchar **words) strcmp(words[0], "writeq") =3D=3D 0) { uint64_t addr; uint64_t value; + bool has_attrs; + MemTxResult result; + MemTxAttrs attrs; + AddressSpace *as; int ret; =20 g_assert(words[1] && words[2]); + if (words[3] && words[4]) { + qtest_send(chr, "ERR too many arguments\n"); + return; + } ret =3D qemu_strtou64(words[1], NULL, 0, &addr); g_assert(ret =3D=3D 0); ret =3D qemu_strtou64(words[2], NULL, 0, &value); g_assert(ret =3D=3D 0); + has_attrs =3D words[3] !=3D NULL; + if (!has_attrs) { + qtest_write_sized(first_cpu->as, addr, + MEMTXATTRS_UNSPECIFIED, + value, words[0][5]); + qtest_send(chr, "OK\n"); + return; + } + if (!qtest_parse_mem_attrs(chr, words[3], &attrs) || + !qtest_get_mem_as(chr, attrs, &as)) { + return; + } =20 - if (words[0][5] =3D=3D 'b') { - uint8_t data =3D value; - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIE= D, - &data, 1); - } else if (words[0][5] =3D=3D 'w') { - uint16_t data =3D value; - tswap16s(&data); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIE= D, - &data, 2); - } else if (words[0][5] =3D=3D 'l') { - uint32_t data =3D value; - tswap32s(&data); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIE= D, - &data, 4); - } else if (words[0][5] =3D=3D 'q') { - uint64_t data =3D value; - tswap64s(&data); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIE= D, - &data, 8); + result =3D qtest_write_sized(as, addr, attrs, value, words[0][5]); + if (result !=3D MEMTX_OK) { + qtest_send_memtx_error(chr, result); + return; } qtest_send(chr, "OK\n"); } else if (strcmp(words[0], "readb") =3D=3D 0 || @@ -544,51 +723,83 @@ static void qtest_process_command(CharFrontend *chr, = gchar **words) strcmp(words[0], "readl") =3D=3D 0 || strcmp(words[0], "readq") =3D=3D 0) { uint64_t addr; - uint64_t value =3D UINT64_C(-1); + uint64_t value =3D 0; + bool has_attrs; + MemTxResult result; + MemTxAttrs attrs; + AddressSpace *as; int ret; =20 g_assert(words[1]); + if (words[2] && words[3]) { + qtest_send(chr, "ERR too many arguments\n"); + return; + } ret =3D qemu_strtou64(words[1], NULL, 0, &addr); g_assert(ret =3D=3D 0); + has_attrs =3D words[2] !=3D NULL; + if (!has_attrs) { + qtest_read_sized(first_cpu->as, addr, + MEMTXATTRS_UNSPECIFIED, + words[0][4], &value); + qtest_sendf(chr, "OK 0x%016" PRIx64 "\n", value); + return; + } + if (!qtest_parse_mem_attrs(chr, words[2], &attrs) || + !qtest_get_mem_as(chr, attrs, &as)) { + return; + } =20 - if (words[0][4] =3D=3D 'b') { - uint8_t data; - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - &data, 1); - value =3D data; - } else if (words[0][4] =3D=3D 'w') { - uint16_t data; - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - &data, 2); - value =3D tswap16(data); - } else if (words[0][4] =3D=3D 'l') { - uint32_t data; - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - &data, 4); - value =3D tswap32(data); - } else if (words[0][4] =3D=3D 'q') { - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - &value, 8); - tswap64s(&value); + result =3D qtest_read_sized(as, addr, attrs, words[0][4], &value); + if (result !=3D MEMTX_OK) { + qtest_send_memtx_error(chr, result); + return; } qtest_sendf(chr, "OK 0x%016" PRIx64 "\n", value); } else if (strcmp(words[0], "read") =3D=3D 0) { g_autoptr(GString) enc =3D NULL; uint64_t addr, len; uint8_t *data; + bool has_attrs; + MemTxResult result; + MemTxAttrs attrs; + AddressSpace *as; int ret; =20 g_assert(words[1] && words[2]); + if (words[3] && words[4]) { + qtest_send(chr, "ERR too many arguments\n"); + return; + } ret =3D qemu_strtou64(words[1], NULL, 0, &addr); g_assert(ret =3D=3D 0); ret =3D qemu_strtou64(words[2], NULL, 0, &len); g_assert(ret =3D=3D 0); /* We'd send garbage to libqtest if len is 0 */ g_assert(len); + has_attrs =3D words[3] !=3D NULL; + if (!has_attrs) { + data =3D g_malloc0(len); + address_space_read(first_cpu->as, addr, + MEMTXATTRS_UNSPECIFIED, + data, len); + enc =3D qemu_hexdump_line(NULL, data, len, 0, 0); + qtest_sendf(chr, "OK 0x%s\n", enc->str); + g_free(data); + return; + } + if (!qtest_parse_mem_attrs(chr, words[3], &attrs) || + !qtest_get_mem_as(chr, attrs, &as)) { + return; + } =20 data =3D g_malloc(len); - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, da= ta, - len); + result =3D address_space_read(as, addr, attrs, data, len); + if (result !=3D MEMTX_OK) { + g_free(data); + qtest_send_memtx_error(chr, result); + return; + } =20 enc =3D qemu_hexdump_line(NULL, data, len, 0, 0); =20 @@ -599,17 +810,45 @@ static void qtest_process_command(CharFrontend *chr, = gchar **words) uint64_t addr, len; uint8_t *data; gchar *b64_data; + bool has_attrs; + MemTxResult result; + MemTxAttrs attrs; + AddressSpace *as; int ret; =20 g_assert(words[1] && words[2]); + if (words[3] && words[4]) { + qtest_send(chr, "ERR too many arguments\n"); + return; + } ret =3D qemu_strtou64(words[1], NULL, 0, &addr); g_assert(ret =3D=3D 0); ret =3D qemu_strtou64(words[2], NULL, 0, &len); g_assert(ret =3D=3D 0); + has_attrs =3D words[3] !=3D NULL; + if (!has_attrs) { + data =3D g_malloc0(len); + address_space_read(first_cpu->as, addr, + MEMTXATTRS_UNSPECIFIED, + data, len); + b64_data =3D g_base64_encode(data, len); + qtest_sendf(chr, "OK %s\n", b64_data); + g_free(data); + g_free(b64_data); + return; + } + if (!qtest_parse_mem_attrs(chr, words[3], &attrs) || + !qtest_get_mem_as(chr, attrs, &as)) { + return; + } =20 data =3D g_malloc(len); - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, da= ta, - len); + result =3D address_space_read(as, addr, attrs, data, len); + if (result !=3D MEMTX_OK) { + g_free(data); + qtest_send_memtx_error(chr, result); + return; + } b64_data =3D g_base64_encode(data, len); qtest_sendf(chr, "OK %s\n", b64_data); =20 @@ -619,13 +858,22 @@ static void qtest_process_command(CharFrontend *chr, = gchar **words) uint64_t addr, len, i; uint8_t *data; size_t data_len; + bool has_attrs; + MemTxResult result; + MemTxAttrs attrs; + AddressSpace *as; int ret; =20 g_assert(words[1] && words[2] && words[3]); + if (words[4] && words[5]) { + qtest_send(chr, "ERR too many arguments\n"); + return; + } ret =3D qemu_strtou64(words[1], NULL, 0, &addr); g_assert(ret =3D=3D 0); ret =3D qemu_strtou64(words[2], NULL, 0, &len); g_assert(ret =3D=3D 0); + has_attrs =3D words[4] !=3D NULL; =20 data_len =3D strlen(words[3]); if (data_len < 3) { @@ -642,46 +890,100 @@ static void qtest_process_command(CharFrontend *chr,= gchar **words) data[i] =3D 0; } } - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, d= ata, - len); + if (!has_attrs) { + address_space_write(first_cpu->as, addr, + MEMTXATTRS_UNSPECIFIED, + data, len); + g_free(data); + qtest_send(chr, "OK\n"); + return; + } + if (!qtest_parse_mem_attrs(chr, words[4], &attrs) || + !qtest_get_mem_as(chr, attrs, &as)) { + g_free(data); + return; + } + result =3D address_space_write(as, addr, attrs, data, len); g_free(data); + if (result !=3D MEMTX_OK) { + qtest_send_memtx_error(chr, result); + return; + } =20 qtest_send(chr, "OK\n"); } else if (strcmp(words[0], "memset") =3D=3D 0) { uint64_t addr, len; - uint8_t *data; unsigned long pattern; + bool has_attrs; + MemTxResult result; + MemTxAttrs attrs; + AddressSpace *as; int ret; =20 g_assert(words[1] && words[2] && words[3]); + if (words[4] && words[5]) { + qtest_send(chr, "ERR too many arguments\n"); + return; + } ret =3D qemu_strtou64(words[1], NULL, 0, &addr); g_assert(ret =3D=3D 0); ret =3D qemu_strtou64(words[2], NULL, 0, &len); g_assert(ret =3D=3D 0); ret =3D qemu_strtoul(words[3], NULL, 0, &pattern); g_assert(ret =3D=3D 0); + has_attrs =3D words[4] !=3D NULL; + if (!has_attrs) { + if (len) { + uint8_t *data =3D g_malloc(len); + + memset(data, pattern, len); + address_space_write(first_cpu->as, addr, + MEMTXATTRS_UNSPECIFIED, + data, len); + g_free(data); + } + qtest_send(chr, "OK\n"); + return; + } + if (!qtest_parse_mem_attrs(chr, words[4], &attrs) || + !qtest_get_mem_as(chr, attrs, &as)) { + return; + } =20 if (len) { - data =3D g_malloc(len); + uint8_t *data =3D g_malloc(len); + memset(data, pattern, len); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIE= D, - data, len); + result =3D address_space_write(as, addr, attrs, data, len); g_free(data); + if (result !=3D MEMTX_OK) { + qtest_send_memtx_error(chr, result); + return; + } } =20 qtest_send(chr, "OK\n"); - } else if (strcmp(words[0], "b64write") =3D=3D 0) { + } else if (strcmp(words[0], "b64write") =3D=3D 0) { uint64_t addr, len; uint8_t *data; size_t data_len; gsize out_len; + bool has_attrs; + MemTxResult result; + MemTxAttrs attrs; + AddressSpace *as; int ret; =20 g_assert(words[1] && words[2] && words[3]); + if (words[4] && words[5]) { + qtest_send(chr, "ERR too many arguments\n"); + return; + } ret =3D qemu_strtou64(words[1], NULL, 0, &addr); g_assert(ret =3D=3D 0); ret =3D qemu_strtou64(words[2], NULL, 0, &len); g_assert(ret =3D=3D 0); + has_attrs =3D words[4] !=3D NULL; =20 data_len =3D strlen(words[3]); if (data_len < 3) { @@ -697,8 +999,22 @@ static void qtest_process_command(CharFrontend *chr, g= char **words) out_len =3D MIN(out_len, len); } =20 - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, d= ata, - len); + if (!has_attrs) { + address_space_write(first_cpu->as, addr, + MEMTXATTRS_UNSPECIFIED, + data, len); + qtest_send(chr, "OK\n"); + return; + } + if (!qtest_parse_mem_attrs(chr, words[4], &attrs) || + !qtest_get_mem_as(chr, attrs, &as)) { + return; + } + result =3D address_space_write(as, addr, attrs, data, len); + if (result !=3D MEMTX_OK) { + qtest_send_memtx_error(chr, result); + return; + } =20 qtest_send(chr, "OK\n"); } else if (strcmp(words[0], "endianness") =3D=3D 0) { --=20 2.34.1 From nobody Wed Apr 1 23:52:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774930107799834.8892608204474; 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charset="utf-8" Expose libqtest APIs for qtest memory commands with optional attrs: - qtest_{read,write}{b,w,l,q}_attrs() - qtest_mem{read,write,set}_attrs() - qtest_buf{read,write}_attrs() Keep the existing libqtest memory access helpers as wrappers passing NULL attrs, so current users remain unchanged. Also add matching libqtest-single shortcut wrappers for the *_attrs helpers. Refactor libqtest response parsing by splitting qtest_rsp_args() into a raw tokenizing helper, qtest_rsp_words(), and the existing OK-checking wrapper. Add qtest_raw_cmd() on top of qtest_rsp_words() so tests can send raw qtest protocol commands and inspect non-OK responses such as ERR and FAIL. Signed-off-by: Tao Tang Reviewed-by: Chao Liu --- tests/qtest/libqtest-single.h | 156 +++++++++++++++++++++ tests/qtest/libqtest.c | 246 ++++++++++++++++++++++++++-------- tests/qtest/libqtest.h | 177 ++++++++++++++++++++++++ 3 files changed, 524 insertions(+), 55 deletions(-) diff --git a/tests/qtest/libqtest-single.h b/tests/qtest/libqtest-single.h index 851724cbcb..2812b86bd4 100644 --- a/tests/qtest/libqtest-single.h +++ b/tests/qtest/libqtest-single.h @@ -291,6 +291,162 @@ static inline void memwrite(uint64_t addr, const void= *data, size_t size) qtest_memwrite(global_qtest, addr, data, size); } =20 +/** + * writeb_attrs: + * @addr: Guest address to write to. + * @value: Value being written. + * @attrs: Optional transaction attributes string. + * + * Writes an 8-bit value to guest memory with optional transaction attribu= tes. + */ +static inline void writeb_attrs(uint64_t addr, uint8_t value, const char *= attrs) +{ + qtest_writeb_attrs(global_qtest, addr, value, attrs); +} + +/** + * writew_attrs: + * @addr: Guest address to write to. + * @value: Value being written. + * @attrs: Optional transaction attributes string. + * + * Writes a 16-bit value to guest memory with optional transaction attribu= tes. + */ +static inline void writew_attrs(uint64_t addr, uint16_t value, + const char *attrs) +{ + qtest_writew_attrs(global_qtest, addr, value, attrs); +} + +/** + * writel_attrs: + * @addr: Guest address to write to. + * @value: Value being written. + * @attrs: Optional transaction attributes string. + * + * Writes a 32-bit value to guest memory with optional transaction attribu= tes. + */ +static inline void writel_attrs(uint64_t addr, uint32_t value, + const char *attrs) +{ + qtest_writel_attrs(global_qtest, addr, value, attrs); +} + +/** + * writeq_attrs: + * @addr: Guest address to write to. + * @value: Value being written. + * @attrs: Optional transaction attributes string. + * + * Writes a 64-bit value to guest memory with optional transaction attribu= tes. + */ +static inline void writeq_attrs(uint64_t addr, uint64_t value, + const char *attrs) +{ + qtest_writeq_attrs(global_qtest, addr, value, attrs); +} + +/** + * readb_attrs: + * @addr: Guest address to read from. + * @attrs: Optional transaction attributes string. + * + * Reads an 8-bit value from guest memory with optional transaction attrib= utes. + * + * Returns: Value read. + */ +static inline uint8_t readb_attrs(uint64_t addr, const char *attrs) +{ + return qtest_readb_attrs(global_qtest, addr, attrs); +} + +/** + * readw_attrs: + * @addr: Guest address to read from. + * @attrs: Optional transaction attributes string. + * + * Reads a 16-bit value from guest memory with optional transaction attrib= utes. + * + * Returns: Value read. + */ +static inline uint16_t readw_attrs(uint64_t addr, const char *attrs) +{ + return qtest_readw_attrs(global_qtest, addr, attrs); +} + +/** + * readl_attrs: + * @addr: Guest address to read from. + * @attrs: Optional transaction attributes string. + * + * Reads a 32-bit value from guest memory with optional transaction attrib= utes. + * + * Returns: Value read. + */ +static inline uint32_t readl_attrs(uint64_t addr, const char *attrs) +{ + return qtest_readl_attrs(global_qtest, addr, attrs); +} + +/** + * readq_attrs: + * @addr: Guest address to read from. + * @attrs: Optional transaction attributes string. + * + * Reads a 64-bit value from guest memory with optional transaction attrib= utes. + * + * Returns: Value read. + */ +static inline uint64_t readq_attrs(uint64_t addr, const char *attrs) +{ + return qtest_readq_attrs(global_qtest, addr, attrs); +} + +/** + * memread_attrs: + * @addr: Guest address to read from. + * @data: Pointer to where memory contents will be stored. + * @size: Number of bytes to read. + * @attrs: Optional transaction attributes string. + * + * Read guest memory into a buffer with optional transaction attributes. + */ +static inline void memread_attrs(uint64_t addr, void *data, size_t size, + const char *attrs) +{ + qtest_memread_attrs(global_qtest, addr, data, size, attrs); +} + +/** + * memwrite_attrs: + * @addr: Guest address to write to. + * @data: Pointer to the bytes that will be written to guest memory. + * @size: Number of bytes to write. + * @attrs: Optional transaction attributes string. + * + * Write a buffer to guest memory with optional transaction attributes. + */ +static inline void memwrite_attrs(uint64_t addr, const void *data, size_t = size, + const char *attrs) +{ + qtest_memwrite_attrs(global_qtest, addr, data, size, attrs); +} + +/** + * memset_attrs: + * @addr: Guest address to write to. + * @pattern: Byte pattern to fill the guest memory region with. + * @size: Number of bytes to write. + * @attrs: Optional transaction attributes string. + * + * Write a pattern to guest memory with optional transaction attributes. + */ +static inline void memset_attrs(uint64_t addr, uint8_t pattern, size_t siz= e, + const char *attrs) +{ + qtest_memset_attrs(global_qtest, addr, pattern, size, attrs); +} + /** * clock_step_next: * diff --git a/tests/qtest/libqtest.c b/tests/qtest/libqtest.c index 051faf31e1..b67786f1ad 100644 --- a/tests/qtest/libqtest.c +++ b/tests/qtest/libqtest.c @@ -747,11 +747,10 @@ static GString *qtest_client_socket_recv_line(QTestSt= ate *s) return line; } =20 -static gchar **qtest_rsp_args(QTestState *s, int expected_args) +static gchar **qtest_rsp_words(QTestState *s) { GString *line; gchar **words; - int i; =20 redo: line =3D s->ops.recv_line(s); @@ -781,6 +780,15 @@ redo: } =20 g_assert(words[0] !=3D NULL); + + return words; +} + +static gchar **qtest_rsp_args(QTestState *s, int expected_args) +{ + gchar **words =3D qtest_rsp_words(s); + int i; + g_assert_cmpstr(words[0], =3D=3D, "OK"); =20 for (i =3D 0; i < expected_args; i++) { @@ -790,6 +798,21 @@ redo: return words; } =20 +gchar **qtest_raw_cmd(QTestState *s, const char *fmt, ...) +{ + va_list ap; + gchar *str; + + va_start(ap, fmt); + str =3D g_strdup_vprintf(fmt, ap); + va_end(ap); + + s->ops.send(s, str); + g_free(str); + + return qtest_rsp_words(s); +} + static void qtest_rsp(QTestState *s) { gchar **words =3D qtest_rsp_args(s, 0); @@ -1232,66 +1255,44 @@ uint32_t qtest_inl(QTestState *s, uint16_t addr) return qtest_big_endian(s) ? bswap32(v) : v; } =20 -static void qtest_write(QTestState *s, const char *cmd, uint64_t addr, - uint64_t value) -{ - qtest_sendf(s, "%s 0x%" PRIx64 " 0x%" PRIx64 "\n", cmd, addr, value); - qtest_rsp(s); -} - void qtest_writeb(QTestState *s, uint64_t addr, uint8_t value) { - qtest_write(s, "writeb", addr, value); + qtest_writeb_attrs(s, addr, value, NULL); } =20 void qtest_writew(QTestState *s, uint64_t addr, uint16_t value) { - qtest_write(s, "writew", addr, value); + qtest_writew_attrs(s, addr, value, NULL); } =20 void qtest_writel(QTestState *s, uint64_t addr, uint32_t value) { - qtest_write(s, "writel", addr, value); + qtest_writel_attrs(s, addr, value, NULL); } =20 void qtest_writeq(QTestState *s, uint64_t addr, uint64_t value) { - qtest_write(s, "writeq", addr, value); -} - -static uint64_t qtest_read(QTestState *s, const char *cmd, uint64_t addr) -{ - gchar **args; - int ret; - uint64_t value; - - qtest_sendf(s, "%s 0x%" PRIx64 "\n", cmd, addr); - args =3D qtest_rsp_args(s, 2); - ret =3D qemu_strtou64(args[1], NULL, 0, &value); - g_assert(!ret); - g_strfreev(args); - - return value; + qtest_writeq_attrs(s, addr, value, NULL); } =20 uint8_t qtest_readb(QTestState *s, uint64_t addr) { - return qtest_read(s, "readb", addr); + return qtest_readb_attrs(s, addr, NULL); } =20 uint16_t qtest_readw(QTestState *s, uint64_t addr) { - return qtest_read(s, "readw", addr); + return qtest_readw_attrs(s, addr, NULL); } =20 uint32_t qtest_readl(QTestState *s, uint64_t addr) { - return qtest_read(s, "readl", addr); + return qtest_readl_attrs(s, addr, NULL); } =20 uint64_t qtest_readq(QTestState *s, uint64_t addr) { - return qtest_read(s, "readq", addr); + return qtest_readq_attrs(s, addr, NULL); } =20 static int hex2nib(char ch) @@ -1309,23 +1310,7 @@ static int hex2nib(char ch) =20 void qtest_memread(QTestState *s, uint64_t addr, void *data, size_t size) { - uint8_t *ptr =3D data; - gchar **args; - size_t i; - - if (!size) { - return; - } - - qtest_sendf(s, "read 0x%" PRIx64 " 0x%zx\n", addr, size); - args =3D qtest_rsp_args(s, 2); - - for (i =3D 0; i < size; i++) { - ptr[i] =3D hex2nib(args[1][2 + (i * 2)]) << 4; - ptr[i] |=3D hex2nib(args[1][2 + (i * 2) + 1]); - } - - g_strfreev(args); + qtest_memread_attrs(s, addr, data, size, NULL); } =20 uint64_t qtest_rtas_call(QTestState *s, const char *name, @@ -1390,23 +1375,58 @@ void qtest_add_data_func(const char *str, const voi= d *data, } =20 void qtest_bufwrite(QTestState *s, uint64_t addr, const void *data, size_t= size) +{ + qtest_bufwrite_attrs(s, addr, data, size, NULL); +} + +void qtest_bufread(QTestState *s, uint64_t addr, void *data, size_t size) +{ + qtest_bufread_attrs(s, addr, data, size, NULL); +} + +void qtest_memwrite(QTestState *s, uint64_t addr, const void *data, size_t= size) +{ + qtest_memwrite_attrs(s, addr, data, size, NULL); +} + +void qtest_memset(QTestState *s, uint64_t addr, uint8_t pattern, size_t si= ze) +{ + qtest_memset_attrs(s, addr, pattern, size, NULL); +} + +static bool qtest_has_attrs(const char *attrs) +{ + return attrs && attrs[0]; +} + +void qtest_bufwrite_attrs(QTestState *s, uint64_t addr, const void *data, + size_t size, const char *attrs) { gchar *bdata; =20 bdata =3D g_base64_encode(data, size); qtest_sendf(s, "b64write 0x%" PRIx64 " 0x%zx ", addr, size); s->ops.send(s, bdata); + if (qtest_has_attrs(attrs)) { + s->ops.send(s, " "); + s->ops.send(s, attrs); + } s->ops.send(s, "\n"); qtest_rsp(s); g_free(bdata); } =20 -void qtest_bufread(QTestState *s, uint64_t addr, void *data, size_t size) +void qtest_bufread_attrs(QTestState *s, uint64_t addr, void *data, size_t = size, + const char *attrs) { gchar **args; size_t len; =20 - qtest_sendf(s, "b64read 0x%" PRIx64 " 0x%zx\n", addr, size); + if (qtest_has_attrs(attrs)) { + qtest_sendf(s, "b64read 0x%" PRIx64 " 0x%zx %s\n", addr, size, att= rs); + } else { + qtest_sendf(s, "b64read 0x%" PRIx64 " 0x%zx\n", addr, size); + } args =3D qtest_rsp_args(s, 2); =20 g_base64_decode_inplace(args[1], &len); @@ -1420,7 +1440,111 @@ void qtest_bufread(QTestState *s, uint64_t addr, vo= id *data, size_t size) g_strfreev(args); } =20 -void qtest_memwrite(QTestState *s, uint64_t addr, const void *data, size_t= size) +static void qtest_write_attrs(QTestState *s, const char *cmd, + uint64_t addr, uint64_t value, + const char *attrs) +{ + if (qtest_has_attrs(attrs)) { + qtest_sendf(s, "%s 0x%" PRIx64 " 0x%" PRIx64 " %s\n", + cmd, addr, value, attrs); + } else { + qtest_sendf(s, "%s 0x%" PRIx64 " 0x%" PRIx64 "\n", cmd, addr, valu= e); + } + qtest_rsp(s); +} + +static uint64_t qtest_read_attrs(QTestState *s, const char *cmd, + uint64_t addr, const char *attrs) +{ + gchar **args; + int ret; + uint64_t value; + + if (qtest_has_attrs(attrs)) { + qtest_sendf(s, "%s 0x%" PRIx64 " %s\n", cmd, addr, attrs); + } else { + qtest_sendf(s, "%s 0x%" PRIx64 "\n", cmd, addr); + } + args =3D qtest_rsp_args(s, 2); + ret =3D qemu_strtou64(args[1], NULL, 0, &value); + g_assert(!ret); + g_strfreev(args); + + return value; +} + +void qtest_writeb_attrs(QTestState *s, uint64_t addr, uint8_t value, + const char *attrs) +{ + qtest_write_attrs(s, "writeb", addr, value, attrs); +} + +void qtest_writew_attrs(QTestState *s, uint64_t addr, uint16_t value, + const char *attrs) +{ + qtest_write_attrs(s, "writew", addr, value, attrs); +} + +void qtest_writel_attrs(QTestState *s, uint64_t addr, uint32_t value, + const char *attrs) +{ + qtest_write_attrs(s, "writel", addr, value, attrs); +} + +void qtest_writeq_attrs(QTestState *s, uint64_t addr, uint64_t value, + const char *attrs) +{ + qtest_write_attrs(s, "writeq", addr, value, attrs); +} + +uint8_t qtest_readb_attrs(QTestState *s, uint64_t addr, const char *attrs) +{ + return qtest_read_attrs(s, "readb", addr, attrs); +} + +uint16_t qtest_readw_attrs(QTestState *s, uint64_t addr, const char *attrs) +{ + return qtest_read_attrs(s, "readw", addr, attrs); +} + +uint32_t qtest_readl_attrs(QTestState *s, uint64_t addr, const char *attrs) +{ + return qtest_read_attrs(s, "readl", addr, attrs); +} + +uint64_t qtest_readq_attrs(QTestState *s, uint64_t addr, const char *attrs) +{ + return qtest_read_attrs(s, "readq", addr, attrs); +} + +void qtest_memread_attrs(QTestState *s, uint64_t addr, void *data, + size_t size, const char *attrs) +{ + uint8_t *ptr =3D data; + gchar **args; + size_t i; + + if (!size) { + return; + } + + if (qtest_has_attrs(attrs)) { + qtest_sendf(s, "read 0x%" PRIx64 " 0x%zx %s\n", addr, size, attrs); + } else { + qtest_sendf(s, "read 0x%" PRIx64 " 0x%zx\n", addr, size); + } + args =3D qtest_rsp_args(s, 2); + + for (i =3D 0; i < size; i++) { + ptr[i] =3D hex2nib(args[1][2 + (i * 2)]) << 4; + ptr[i] |=3D hex2nib(args[1][2 + (i * 2) + 1]); + } + + g_strfreev(args); +} + +void qtest_memwrite_attrs(QTestState *s, uint64_t addr, const void *data, + size_t size, const char *attrs) { const uint8_t *ptr =3D data; size_t i; @@ -1436,14 +1560,26 @@ void qtest_memwrite(QTestState *s, uint64_t addr, c= onst void *data, size_t size) sprintf(&enc[i * 2], "%02x", ptr[i]); } =20 - qtest_sendf(s, "write 0x%" PRIx64 " 0x%zx 0x%s\n", addr, size, enc); + if (qtest_has_attrs(attrs)) { + qtest_sendf(s, "write 0x%" PRIx64 " 0x%zx 0x%s %s\n", + addr, size, enc, attrs); + } else { + qtest_sendf(s, "write 0x%" PRIx64 " 0x%zx 0x%s\n", addr, size, enc= ); + } qtest_rsp(s); g_free(enc); } =20 -void qtest_memset(QTestState *s, uint64_t addr, uint8_t pattern, size_t si= ze) +void qtest_memset_attrs(QTestState *s, uint64_t addr, uint8_t pattern, + size_t size, const char *attrs) { - qtest_sendf(s, "memset 0x%" PRIx64 " 0x%zx 0x%02x\n", addr, size, patt= ern); + if (qtest_has_attrs(attrs)) { + qtest_sendf(s, "memset 0x%" PRIx64 " 0x%zx 0x%02x %s\n", + addr, size, pattern, attrs); + } else { + qtest_sendf(s, "memset 0x%" PRIx64 " 0x%zx 0x%02x\n", + addr, size, pattern); + } qtest_rsp(s); } =20 diff --git a/tests/qtest/libqtest.h b/tests/qtest/libqtest.h index 9c118c89ca..cee74cf2a4 100644 --- a/tests/qtest/libqtest.h +++ b/tests/qtest/libqtest.h @@ -239,6 +239,19 @@ void qtest_qmp_send(QTestState *s, const char *fmt, ..= .) void qtest_qmp_send_raw(QTestState *s, const char *fmt, ...) G_GNUC_PRINTF(2, 3); =20 +/** + * qtest_raw_cmd: + * @s: #QTestState instance to operate on. + * @fmt: raw qtest protocol text to send, formatted like sprintf(). + * + * Sends a raw qtest command and returns the response split on spaces. + * The response is not required to start with ``OK``; callers can inspect + * ``args[0]`` for ``OK``, ``ERR``, or ``FAIL`` and must free the returned + * vector with g_strfreev(). + */ +gchar **qtest_raw_cmd(QTestState *s, const char *fmt, ...) + G_GNUC_PRINTF(2, 3); + /** * qtest_socket_server: * @socket_path: the UNIX domain socket path @@ -671,6 +684,20 @@ uint64_t qtest_csr_call(QTestState *s, const char *nam= e, */ void qtest_bufread(QTestState *s, uint64_t addr, void *data, size_t size); =20 +/** + * qtest_bufread_attrs: + * @s: #QTestState instance to operate on. + * @addr: Guest address to read from. + * @data: Pointer to where memory contents will be stored. + * @size: Number of bytes to read. + * @attrs: Optional transaction attributes string. + * + * Read guest memory into a buffer and receive using a base64 encoding with + * optional transaction attributes. + */ +void qtest_bufread_attrs(QTestState *s, uint64_t addr, void *data, size_t = size, + const char *attrs); + /** * qtest_memwrite: * @s: #QTestState instance to operate on. @@ -694,6 +721,21 @@ void qtest_memwrite(QTestState *s, uint64_t addr, cons= t void *data, size_t size) void qtest_bufwrite(QTestState *s, uint64_t addr, const void *data, size_t size); =20 +/** + * qtest_bufwrite_attrs: + * @s: #QTestState instance to operate on. + * @addr: Guest address to write to. + * @data: Pointer to the bytes that will be written to guest memory. + * @size: Number of bytes to write. + * @attrs: Optional transaction attributes string. + * + * Write a buffer to guest memory and transmit using a base64 encoding with + * optional transaction attributes. + */ +void qtest_bufwrite_attrs(QTestState *s, uint64_t addr, + const void *data, size_t size, + const char *attrs); + /** * qtest_memset: * @s: #QTestState instance to operate on. @@ -705,6 +747,141 @@ void qtest_bufwrite(QTestState *s, uint64_t addr, */ void qtest_memset(QTestState *s, uint64_t addr, uint8_t patt, size_t size); =20 +/** + * qtest_writeb_attrs: + * @s: #QTestState instance to operate on. + * @addr: Guest address to write to. + * @value: Value being written. + * @attrs: Optional transaction attributes string. + * + * Writes an 8-bit value to guest memory with optional transaction attribu= tes. + */ +void qtest_writeb_attrs(QTestState *s, uint64_t addr, uint8_t value, + const char *attrs); + +/** + * qtest_writew_attrs: + * @s: #QTestState instance to operate on. + * @addr: Guest address to write to. + * @value: Value being written. + * @attrs: Optional transaction attributes string. + * + * Writes a 16-bit value to guest memory with optional transaction attribu= tes. + */ +void qtest_writew_attrs(QTestState *s, uint64_t addr, uint16_t value, + const char *attrs); + +/** + * qtest_writel_attrs: + * @s: #QTestState instance to operate on. + * @addr: Guest address to write to. + * @value: Value being written. + * @attrs: Optional transaction attributes string. + * + * Writes a 32-bit value to guest memory with optional transaction attribu= tes. + */ +void qtest_writel_attrs(QTestState *s, uint64_t addr, uint32_t value, + const char *attrs); + +/** + * qtest_writeq_attrs: + * @s: #QTestState instance to operate on. + * @addr: Guest address to write to. + * @value: Value being written. + * @attrs: Optional transaction attributes string. + * + * Writes a 64-bit value to guest memory with optional transaction attribu= tes. + */ +void qtest_writeq_attrs(QTestState *s, uint64_t addr, uint64_t value, + const char *attrs); + +/** + * qtest_readb_attrs: + * @s: #QTestState instance to operate on. + * @addr: Guest address to read from. + * @attrs: Optional transaction attributes string. + * + * Reads an 8-bit value from guest memory with optional transaction attrib= utes. + * + * Returns: Value read. + */ +uint8_t qtest_readb_attrs(QTestState *s, uint64_t addr, const char *attrs); + +/** + * qtest_readw_attrs: + * @s: #QTestState instance to operate on. + * @addr: Guest address to read from. + * @attrs: Optional transaction attributes string. + * + * Reads a 16-bit value from guest memory with optional transaction attrib= utes. + * + * Returns: Value read. + */ +uint16_t qtest_readw_attrs(QTestState *s, uint64_t addr, const char *attrs= ); + +/** + * qtest_readl_attrs: + * @s: #QTestState instance to operate on. + * @addr: Guest address to read from. + * @attrs: Optional transaction attributes string. + * + * Reads a 32-bit value from guest memory with optional transaction attrib= utes. + * + * Returns: Value read. + */ +uint32_t qtest_readl_attrs(QTestState *s, uint64_t addr, const char *attrs= ); + +/** + * qtest_readq_attrs: + * @s: #QTestState instance to operate on. + * @addr: Guest address to read from. + * @attrs: Optional transaction attributes string. + * + * Reads a 64-bit value from guest memory with optional transaction attrib= utes. + * + * Returns: Value read. + */ +uint64_t qtest_readq_attrs(QTestState *s, uint64_t addr, const char *attrs= ); + +/** + * qtest_memread_attrs: + * @s: #QTestState instance to operate on. + * @addr: Guest address to read from. + * @data: Pointer to where memory contents will be stored. + * @size: Number of bytes to read. + * @attrs: Optional transaction attributes string. + * + * Read guest memory into a buffer with optional transaction attributes. + */ +void qtest_memread_attrs(QTestState *s, uint64_t addr, void *data, size_t = size, + const char *attrs); + +/** + * qtest_memwrite_attrs: + * @s: #QTestState instance to operate on. + * @addr: Guest address to write to. + * @data: Pointer to the bytes that will be written to guest memory. + * @size: Number of bytes to write. + * @attrs: Optional transaction attributes string. + * + * Write a buffer to guest memory with optional transaction attributes. + */ +void qtest_memwrite_attrs(QTestState *s, uint64_t addr, const void *data, + size_t size, const char *attrs); + +/** + * qtest_memset_attrs: + * @s: #QTestState instance to operate on. + * @addr: Guest address to write to. + * @patt: Byte pattern to fill the guest memory region with. + * @size: Number of bytes to write. + * @attrs: Optional transaction attributes string. + * + * Write a pattern to guest memory with optional transaction attributes. + */ +void qtest_memset_attrs(QTestState *s, uint64_t addr, uint8_t patt, size_t= size, + const char *attrs); + /** * qtest_clock_step_next: * @s: #QTestState instance to operate on. --=20 2.34.1 From nobody Wed Apr 1 23:52:05 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774930149866471.99189149158497; Mon, 30 Mar 2026 21:09:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w7QOS-00011t-K9; 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charset="utf-8" Add qtest-attrs-test to exercise qtest memory access commands with attrs on both aarch64 and x86. The test covers: - Arm virt,secure=3Don: scalar and bulk accesses across non-secure, secure, and root spaces, plus negative coverage for realm and for non-secure accesses into secure-only RAM - x86 q35: normal accesses - libqtest-single *_attrs shortcut wrappers For negative cases, use qtest_raw_cmd() to check that accesses which miss the intended AddressSpace fail with ERR responses emitted via qtest_send_memtx_error(). On Arm, the test targets the virt machine's secure-only RAM window so that the requested attrs must select the correct address space. Also wire qtest-attrs-test into the aarch64 and i386/x86_64 qtest builds. Signed-off-by: Tao Tang --- tests/qtest/meson.build | 7 +- tests/qtest/qtest-attrs-test.c | 350 +++++++++++++++++++++++++++++++++ 2 files changed, 355 insertions(+), 2 deletions(-) create mode 100644 tests/qtest/qtest-attrs-test.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index be4fa627b5..87aa104d23 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -115,6 +115,7 @@ qtests_i386 =3D \ 'drive_del-test', 'cpu-plug-test', 'migration-test', + 'qtest-attrs-test', ] =20 if dbus_display and config_all_devices.has_key('CONFIG_VGA') @@ -249,7 +250,8 @@ qtests_arm =3D \ (config_all_devices.has_key('CONFIG_STM32L4X5_SOC') and config_all_devices.has_key('CONFIG_DM163')? ['dm163-test'] : []) + \ ['arm-cpu-features', - 'boot-serial-test'] + 'boot-serial-test', + 'qtest-attrs-test',] =20 # TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-tes= t unconditional qtests_aarch64 =3D \ @@ -270,7 +272,8 @@ qtests_aarch64 =3D \ ['arm-cpu-features', 'numa-test', 'boot-serial-test', - 'migration-test'] + 'migration-test', + 'qtest-attrs-test'] =20 qtests_s390x =3D \ qtests_filter + \ diff --git a/tests/qtest/qtest-attrs-test.c b/tests/qtest/qtest-attrs-test.c new file mode 100644 index 0000000000..cd6b81e505 --- /dev/null +++ b/tests/qtest/qtest-attrs-test.c @@ -0,0 +1,350 @@ +/* + * QTest for memory access with transaction attributes + * + * Verify optional attrs argument support for qtest memory commands. + * + * Copyright (c) 2026 Phytium Technology + * + * Author: + * Tao Tang + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "libqtest.h" +#include "libqtest-single.h" + +/* + * The Arm virt test uses both the default non-secure RAM at 0x4000_0000 a= nd + * the secure-only RAM window at 0x0e00_0000. The x86 q35 test only exerci= ses + * regular RAM that is visible from both the default and SMM address space= s. + */ +#define TEST_ADDR_OFFSET_NS 0x1000ULL +#define TEST_ADDR_OFFSET_S 0xe000000ULL +#define TEST_ARM_SEC_BASE 0x0ULL +#define TEST_ARM_NS_BASE 0x40000000ULL +#define TEST_X86_BASE 0x0ULL + +#define TEST_ADDR_ARM_S (TEST_ARM_SEC_BASE + TEST_ADDR_OFFSET_S) +#define TEST_ADDR_ARM_NS (TEST_ARM_NS_BASE + TEST_ADDR_OFFSET_NS) +#define TEST_ADDR_X86 (TEST_X86_BASE + TEST_ADDR_OFFSET_NS) + +#define ARM_MACHINE_ARGS "-machine virt,secure=3Don -accel tcg" +#define X86_MACHINE_ARGS "-machine q35,smm=3Don -m 1G -accel tcg" + +static void G_GNUC_PRINTF(3, 4) assert_qtest_response(QTestState *qts, + const char *expected, + const char *fmt, ...) +{ + va_list ap; + g_autofree gchar *cmd =3D NULL; + g_autofree gchar *line =3D NULL; + g_auto(GStrv) response =3D NULL; + + va_start(ap, fmt); + cmd =3D g_strdup_vprintf(fmt, ap); + va_end(ap); + + response =3D qtest_raw_cmd(qts, "%s", cmd); + line =3D g_strjoinv(" ", response); + g_assert_cmpstr(line, =3D=3D, expected); +} + +static void G_GNUC_PRINTF(2, 3) assert_qtest_error_prefix(QTestState *qts, + const char *fmt,= ...) +{ + va_list ap; + g_autofree gchar *cmd =3D NULL; + g_auto(GStrv) response =3D NULL; + + va_start(ap, fmt); + cmd =3D g_strdup_vprintf(fmt, ap); + va_end(ap); + + response =3D qtest_raw_cmd(qts, "%s", cmd); + g_assert_cmpstr(response[0], =3D=3D, "ERR"); +} + +static void test_arm_scalar_attrs(void) +{ + QTestState *qts; + uint8_t val; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qts =3D qtest_init(ARM_MACHINE_ARGS); + + qtest_writeb_attrs(qts, TEST_ADDR_ARM_NS, 0x11, NULL); + val =3D qtest_readb_attrs(qts, TEST_ADDR_ARM_NS, NULL); + g_assert_cmpuint(val, =3D=3D, 0x11); + + qtest_writeb_attrs(qts, TEST_ADDR_ARM_NS + 0x1, 0x22, "space=3Dnon-sec= ure"); + val =3D qtest_readb_attrs(qts, TEST_ADDR_ARM_NS + 0x1, "space=3Dnon-se= cure"); + g_assert_cmpuint(val, =3D=3D, 0x22); + + qtest_writeb_attrs(qts, TEST_ADDR_ARM_S + 0x2, 0x33, "secure"); + val =3D qtest_readb_attrs(qts, TEST_ADDR_ARM_S + 0x2, "secure"); + g_assert_cmpuint(val, =3D=3D, 0x33); + + assert_qtest_response(qts, "ERR invalid attrs argument", + "readb 0x%" PRIx64 " invalid\n", + (uint64_t)(TEST_ADDR_ARM_NS + 0x2)); + assert_qtest_response(qts, + "ERR invalid space value. Valid space: " + "secure/non-secure/root/realm", + "readb 0x%" PRIx64 " space=3Dinvalid\n", + (uint64_t)(TEST_ADDR_ARM_NS + 0x2)); + assert_qtest_response(qts, "ERR too many arguments", + "writeb 0x%" PRIx64 " 0x44 secure extra\n", + (uint64_t)(TEST_ADDR_ARM_NS + 0x2)); + + assert_qtest_error_prefix(qts, "writeb 0x%" PRIx64 " 0x44 space=3Dreal= m\n", + (uint64_t)(TEST_ADDR_ARM_S + 0x3)); + assert_qtest_error_prefix(qts, "readb 0x%" PRIx64 " space=3Drealm\n", + (uint64_t)(TEST_ADDR_ARM_S + 0x3)); + + qtest_writeb_attrs(qts, TEST_ADDR_ARM_S + 0x4, 0x55, "space=3Droot"); + val =3D qtest_readb_attrs(qts, TEST_ADDR_ARM_S + 0x4, "space=3Droot"); + g_assert_cmpuint(val, =3D=3D, 0x55); + + qtest_writeb_attrs(qts, TEST_ADDR_ARM_S + 0x5, 0x66, "space=3Dsecure"); + val =3D qtest_readb_attrs(qts, TEST_ADDR_ARM_S + 0x5, "space=3Dsecure"= ); + g_assert_cmpuint(val, =3D=3D, 0x66); + + qtest_writeb(qts, TEST_ADDR_ARM_NS + 0x6, 0x77); + val =3D qtest_readb(qts, TEST_ADDR_ARM_NS + 0x6); + g_assert_cmpuint(val, =3D=3D, 0x77); + val =3D qtest_readb_attrs(qts, TEST_ADDR_ARM_NS + 0x6, "space=3Dnon-se= cure"); + g_assert_cmpuint(val, =3D=3D, 0x77); + + assert_qtest_error_prefix(qts, + "writeb 0x%" PRIx64 " 0x77 space=3Dnon-secur= e\n", + (uint64_t)(TEST_ADDR_ARM_S + 0x7)); + assert_qtest_error_prefix(qts, "readb 0x%" PRIx64 " space=3Dnon-secure= \n", + (uint64_t)(TEST_ADDR_ARM_S + 0x7)); + + qtest_quit(qts); +} + +static void test_arm_bulk_attrs(void) +{ + QTestState *qts; + uint8_t wbuf[16] =3D { + 0x00, 0x11, 0x22, 0x33, + 0x44, 0x55, 0x66, 0x77, + 0x88, 0x99, 0xaa, 0xbb, + 0xcc, 0xdd, 0xee, 0xff, + }; + uint8_t rbuf[16]; + size_t i; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qts =3D qtest_init(ARM_MACHINE_ARGS); + + qtest_memwrite_attrs(qts, TEST_ADDR_ARM_NS + 0x100, + wbuf, sizeof(wbuf), NULL); + qtest_memread_attrs(qts, TEST_ADDR_ARM_NS + 0x100, + rbuf, sizeof(rbuf), NULL); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_memwrite_attrs(qts, TEST_ADDR_ARM_NS + 0x200, + wbuf, sizeof(wbuf), "space=3Dnon-secure"); + qtest_memread_attrs(qts, TEST_ADDR_ARM_NS + 0x200, + rbuf, sizeof(rbuf), "space=3Dnon-secure"); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_memwrite_attrs(qts, TEST_ADDR_ARM_S + 0x300, + wbuf, sizeof(wbuf), "secure"); + qtest_memread_attrs(qts, TEST_ADDR_ARM_S + 0x300, + rbuf, sizeof(rbuf), "secure"); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_memset_attrs(qts, TEST_ADDR_ARM_S + 0x400, + 0xa5, sizeof(rbuf), "space=3Droot"); + qtest_memread_attrs(qts, TEST_ADDR_ARM_S + 0x400, + rbuf, sizeof(rbuf), "space=3Droot"); + for (i =3D 0; i < sizeof(rbuf); i++) { + g_assert_cmpuint(rbuf[i], =3D=3D, 0xa5); + } + + qtest_bufwrite_attrs(qts, TEST_ADDR_ARM_NS + 0x500, + wbuf, sizeof(wbuf), "space=3Dnon-secure"); + qtest_bufread_attrs(qts, TEST_ADDR_ARM_NS + 0x500, + rbuf, sizeof(rbuf), "space=3Dnon-secure"); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_bufwrite_attrs(qts, TEST_ADDR_ARM_S + 0x600, + wbuf, sizeof(wbuf), "secure"); + qtest_bufread_attrs(qts, TEST_ADDR_ARM_S + 0x600, + rbuf, sizeof(rbuf), "secure"); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_memwrite(qts, TEST_ADDR_ARM_NS + 0x700, wbuf, 4); + qtest_memread(qts, TEST_ADDR_ARM_NS + 0x700, rbuf, 4); + g_assert(memcmp(wbuf, rbuf, 4) =3D=3D 0); + + qtest_memset(qts, TEST_ADDR_ARM_NS + 0x710, 0xa5, 4); + qtest_memread(qts, TEST_ADDR_ARM_NS + 0x710, rbuf, 4); + for (i =3D 0; i < 4; i++) { + g_assert_cmpuint(rbuf[i], =3D=3D, 0xa5); + } + + qtest_bufwrite(qts, TEST_ADDR_ARM_NS + 0x720, wbuf, 4); + qtest_bufread(qts, TEST_ADDR_ARM_NS + 0x720, rbuf, 4); + g_assert(memcmp(wbuf, rbuf, 4) =3D=3D 0); + + assert_qtest_error_prefix(qts, "write 0x%" PRIx64 " 0x%zx 0x00112233 " + "space=3Dnon-secure\n", + (uint64_t)(TEST_ADDR_ARM_S + 0x730), + (size_t)4); + assert_qtest_error_prefix(qts, "read 0x%" PRIx64 " 0x%zx " + "space=3Dnon-secure\n", + (uint64_t)(TEST_ADDR_ARM_S + 0x730), (size_t= )4); + assert_qtest_error_prefix(qts, "memset 0x%" PRIx64 " 0x%zx 0xa5 " + "space=3Dnon-secure\n", + (uint64_t)(TEST_ADDR_ARM_S + 0x740), + (size_t)4); + assert_qtest_error_prefix(qts, "b64write 0x%" PRIx64 " 0x%zx AQIDBA=3D= =3D " + "space=3Dnon-secure\n", + (uint64_t)(TEST_ADDR_ARM_S + 0x750), + (size_t)4); + assert_qtest_error_prefix(qts, "b64read 0x%" PRIx64 " 0x%zx " + "space=3Dnon-secure\n", + (uint64_t)(TEST_ADDR_ARM_S + 0x750), (size_t= )4); + assert_qtest_response(qts, "ERR too many arguments", + "write 0x%" PRIx64 " 0x%zx 0x00112233 secure " + "extra\n", + (uint64_t)(TEST_ADDR_ARM_NS + 0x760), + (size_t)4); + + qtest_quit(qts); +} + +static void test_arm_single_shortcuts_attrs(void) +{ + uint8_t val; + uint8_t wbuf[4] =3D { 0x10, 0x20, 0x30, 0x40 }; + uint8_t rbuf[4]; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qtest_start(ARM_MACHINE_ARGS); + + writeb_attrs(TEST_ADDR_ARM_S + 0x700, 0x5a, "secure"); + val =3D readb_attrs(TEST_ADDR_ARM_S + 0x700, "secure"); + g_assert_cmpuint(val, =3D=3D, 0x5a); + + writel_attrs(TEST_ADDR_ARM_S + 0x704, + 0xa5a5a5a5, "space=3Droot"); + g_assert_cmphex(readl_attrs(TEST_ADDR_ARM_S + 0x704, "space=3Droot"), = =3D=3D, + 0xa5a5a5a5U); + + memwrite_attrs(TEST_ADDR_ARM_NS + 0x708, + wbuf, sizeof(wbuf), "space=3Dnon-secure"); + memread_attrs(TEST_ADDR_ARM_NS + 0x708, + rbuf, sizeof(rbuf), "space=3Dnon-secure"); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_end(); +} + +static void test_x86_scalar_attrs(void) +{ + QTestState *qts; + uint8_t val; + + if (!qtest_has_machine("q35")) { + g_test_skip("q35 machine not available"); + return; + } + + qts =3D qtest_init(X86_MACHINE_ARGS); + + qtest_writeb_attrs(qts, TEST_ADDR_X86, 0x11, NULL); + val =3D qtest_readb_attrs(qts, TEST_ADDR_X86, NULL); + g_assert_cmpuint(val, =3D=3D, 0x11); + val =3D qtest_readb_attrs(qts, TEST_ADDR_X86, "secure"); + g_assert_cmpuint(val, =3D=3D, 0x11); + + qtest_writeb_attrs(qts, TEST_ADDR_X86 + 0x1, 0x22, "secure"); + val =3D qtest_readb_attrs(qts, TEST_ADDR_X86 + 0x1, "secure"); + g_assert_cmpuint(val, =3D=3D, 0x22); + val =3D qtest_readb_attrs(qts, TEST_ADDR_X86 + 0x1, NULL); + g_assert_cmpuint(val, =3D=3D, 0x22); + assert_qtest_response(qts, "ERR space=3D<...> is Arm-specific", + "readb 0x%" PRIx64 " space=3Dsecure\n", + (uint64_t)(TEST_ADDR_X86 + 0x2)); + + qtest_quit(qts); +} + +static void test_x86_bulk_attrs(void) +{ + QTestState *qts; + uint8_t wbuf[8] =3D { 1, 2, 3, 4, 5, 6, 7, 8 }; + uint8_t rbuf[8]; + size_t i; + + if (!qtest_has_machine("q35")) { + g_test_skip("q35 machine not available"); + return; + } + + qts =3D qtest_init(X86_MACHINE_ARGS); + + qtest_memwrite_attrs(qts, TEST_ADDR_X86 + 0x100, wbuf, sizeof(wbuf), N= ULL); + qtest_memread_attrs(qts, TEST_ADDR_X86 + 0x100, + rbuf, sizeof(rbuf), "secure"); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_memwrite_attrs(qts, TEST_ADDR_X86 + 0x180, + wbuf, sizeof(wbuf), "secure"); + qtest_memread_attrs(qts, TEST_ADDR_X86 + 0x180, + rbuf, sizeof(rbuf), NULL); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_memset_attrs(qts, TEST_ADDR_X86 + 0x200, + 0x3c, sizeof(rbuf), "secure"); + qtest_memread_attrs(qts, TEST_ADDR_X86 + 0x200, + rbuf, sizeof(rbuf), NULL); + for (i =3D 0; i < sizeof(rbuf); i++) { + g_assert_cmpuint(rbuf[i], =3D=3D, 0x3c); + } + + qtest_bufwrite_attrs(qts, TEST_ADDR_X86 + 0x280, + wbuf, sizeof(wbuf), NULL); + qtest_bufread_attrs(qts, TEST_ADDR_X86 + 0x280, + rbuf, sizeof(rbuf), "secure"); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + assert_qtest_response(qts, "ERR too many arguments", + "read 0x%" PRIx64 " 0x%zx secure extra\n", + (uint64_t)(TEST_ADDR_X86 + 0x300), + sizeof(rbuf)); + + qtest_quit(qts); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + qtest_add_func("/qtest/arm/attrs/scalar", test_arm_scalar_attrs); + qtest_add_func("/qtest/arm/attrs/bulk", test_arm_bulk_attrs); + qtest_add_func("/qtest/arm/attrs/single_shortcuts", + test_arm_single_shortcuts_attrs); + qtest_add_func("/qtest/x86/attrs/scalar", test_x86_scalar_attrs); + qtest_add_func("/qtest/x86/attrs/bulk", test_x86_bulk_attrs); + + return g_test_run(); +} --=20 2.34.1 From nobody Wed Apr 1 23:52:05 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177493015082141.528882008033975; Mon, 30 Mar 2026 21:09:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w7QOT-000133-9m; Tue, 31 Mar 2026 00:07:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w7QOL-0000zZ-Qa; Tue, 31 Mar 2026 00:07:50 -0400 Received: from zg8tmtyylji0my4xnjqumte4.icoremail.net ([162.243.164.118]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w7QOI-0002Gy-EZ; Tue, 31 Mar 2026 00:07:49 -0400 Received: from prodtpl.icoremail.net (unknown [10.12.1.20]) by hzbj-icmmx-7 (Coremail) with SMTP id AQAAfwB3fpqNSMtp8YjBCA--.55S2; Tue, 31 Mar 2026 12:07:41 +0800 (CST) Received: from phytium.com.cn (unknown [218.76.62.144]) by mail (Coremail) with SMTP id AQAAf8DwSJR6SMtpYqQHAA--.18366S7; Tue, 31 Mar 2026 12:07:39 +0800 (CST) From: Tao Tang To: Fabiano Rosas , Laurent Vivier , Paolo Bonzini Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Peter Maydell , Chen Baozi , Pierrick Bouvier , Chao Liu , Tao Tang Subject: [PATCH 4/4] [NOT-MERGE] tests/qtest: add q35 SMM-only x86 attrs coverage Date: Tue, 31 Mar 2026 12:06:59 +0800 Message-Id: <20260331040659.401397-5-tangtao1634@phytium.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260331040659.401397-1-tangtao1634@phytium.com.cn> References: <20260331040659.401397-1-tangtao1634@phytium.com.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8DwSJR6SMtpYqQHAA--.18366S7 X-CM-SenderInfo: pwdqw3tdrrljuu6sx5pwlxzhxfrphubq/1tbiAQALBWnKzfEBswABsj Authentication-Results: hzbj-icmmx-7; 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charset="utf-8" Add a q35-only test path for x86 secure attrs by introducing an optional test-only RAM region that is mapped only into the SMM address space. The new qtest-x86-attrs-test enables this region with `-global mch.x-smm-test-ram=3Don` and verifies that accesses with the `secure` attribute reach the SMM-only region, while default accesses do not. This provides the x86 cross-verification that qtest-attrs-test does not cover, where normal RAM is visible from both the default and SMM address spaces. This is a NOT-MERGE commit. Signed-off-by: Tao Tang --- hw/pci-host/q35.c | 26 +++++ include/hw/pci-host/q35.h | 8 ++ tests/qtest/meson.build | 1 + tests/qtest/qtest-x86-attrs-test.c | 170 +++++++++++++++++++++++++++++ 4 files changed, 205 insertions(+) create mode 100644 tests/qtest/qtest-x86-attrs-test.c diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index e85e4227b3..5b222847b3 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -566,12 +566,19 @@ static void mch_realize(PCIDevice *d, Error **errp) int i; MCHPCIState *mch =3D MCH_PCI_DEVICE(d); =20 + ERRP_GUARD(); + if (mch->ext_tseg_mbytes > MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX) { error_setg(errp, "invalid extended-tseg-mbytes value: %" PRIu16, mch->ext_tseg_mbytes); return; } =20 + if (mch->enable_smm_test_ram && !mch->has_smm_ranges) { + error_setg(errp, "x-smm-test-ram requires SMM support"); + return; + } + /* setup pci memory mapping */ pc_pci_as_mapping_init(mch->system_memory, mch->pci_address_space); =20 @@ -653,6 +660,23 @@ static void mch_realize(PCIDevice *d, Error **errp) memory_region_add_subregion(&mch->smram, MCH_HOST_BRIDGE_SMBASE_ADDR, &mch->smbase_window); =20 + if (mch->enable_smm_test_ram) { + /* + * This is a QEMU-specific, test-only region. It is mapped only in= to + * mch->smram so qtest can verify that x86 secure attrs select the= SMM + * address space rather than the default one. + */ + memory_region_init_ram(&mch->smm_test_ram, OBJECT(mch), + "smm-test-ram", + MCH_HOST_BRIDGE_SMM_TEST_RAM_SIZE, errp); + if (*errp) { + return; + } + memory_region_add_subregion(&mch->smram, + MCH_HOST_BRIDGE_SMM_TEST_RAM_BASE, + &mch->smm_test_ram); + } + object_property_add_const_link(qdev_get_machine(), "smram", OBJECT(&mch->smram)); } @@ -661,6 +685,8 @@ static const Property mch_props[] =3D { DEFINE_PROP_UINT16("extended-tseg-mbytes", MCHPCIState, ext_tseg_mbyte= s, 64), DEFINE_PROP_BOOL("smbase-smram", MCHPCIState, has_smram_at_smbase, tru= e), + DEFINE_PROP_BOOL("x-smm-test-ram", MCHPCIState, enable_smm_test_ram, + false), }; =20 static void mch_class_init(ObjectClass *klass, const void *data) diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h index ddafc3f2e3..1ca26f0e63 100644 --- a/include/hw/pci-host/q35.h +++ b/include/hw/pci-host/q35.h @@ -49,8 +49,10 @@ struct MCHPCIState { MemoryRegion smram, low_smram, high_smram; MemoryRegion tseg_blackhole, tseg_window; MemoryRegion smbase_blackhole, smbase_window; + MemoryRegion smm_test_ram; bool has_smram_at_smbase; bool has_smm_ranges; + bool enable_smm_test_ram; Range pci_hole; uint64_t below_4g_mem_size; uint64_t above_4g_mem_size; @@ -99,6 +101,12 @@ struct Q35PCIHost { #define MCH_HOST_BRIDGE_PCIEXBAR_SIZE 8 /* 64bit register */ #define MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT 0xb0000000 #define MCH_HOST_BRIDGE_PCIEXBAR_MAX (0x10000000) /* 256M */ +/* + * Optional qtest-only RAM window used to expose an address that exists on= ly + * in the SMM address space, so x86 secure attrs can be cross-checked. + */ +#define MCH_HOST_BRIDGE_SMM_TEST_RAM_BASE 0xfef00000 +#define MCH_HOST_BRIDGE_SMM_TEST_RAM_SIZE (64 * KiB) #define MCH_HOST_BRIDGE_PCIEXBAR_ADMSK Q35_MASK(64, 35, 28) #define MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK ((uint64_t)(1 << 26)) #define MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK ((uint64_t)(1 << 25)) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 87aa104d23..fcdd95bf7f 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -116,6 +116,7 @@ qtests_i386 =3D \ 'cpu-plug-test', 'migration-test', 'qtest-attrs-test', + 'qtest-x86-attrs-test', ] =20 if dbus_display and config_all_devices.has_key('CONFIG_VGA') diff --git a/tests/qtest/qtest-x86-attrs-test.c b/tests/qtest/qtest-x86-att= rs-test.c new file mode 100644 index 0000000000..068ee8b7d3 --- /dev/null +++ b/tests/qtest/qtest-x86-attrs-test.c @@ -0,0 +1,170 @@ +/* + * QTest for x86 memory access with transaction attributes + * + * Verify q35 SMM address-space access with the secure attribute. + * + * Copyright (c) 2026 Phytium Technology + * + * Author: + * Tao Tang + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/cutils.h" +#include "libqtest.h" + +#define TEST_ADDR_OFFSET_NS 0x1000ULL +#define TEST_X86_BASE 0x0ULL +#define TEST_X86_SMM_BASE 0xfef00000ULL + +#define TEST_ADDR_X86 (TEST_X86_BASE + TEST_ADDR_OFFSET_NS) + +#define X86_MACHINE_ARGS "-machine q35,smm=3Don -m 1G -accel tcg " \ + "-global mch.x-smm-test-ram=3Don" + +static void assert_default_scalar_read_isolated(QTestState *qts, uint64_t = addr, + char **before, + uint8_t secure_value) +{ + g_auto(GStrv) after =3D NULL; + uint64_t value; + int ret; + + after =3D qtest_raw_cmd(qts, "readb 0x%" PRIx64 "\n", addr); + + if (g_strcmp0(before[0], "ERR") =3D=3D 0) { + g_assert_cmpstr(after[0], =3D=3D, "ERR"); + return; + } + + g_assert_cmpstr(before[0], =3D=3D, "OK"); + g_assert_nonnull(before[1]); + g_assert_cmpstr(after[0], =3D=3D, "OK"); + g_assert_nonnull(after[1]); + g_assert_cmpstr(after[1], =3D=3D, before[1]); + + ret =3D qemu_strtou64(after[1], NULL, 0, &value); + g_assert_cmpint(ret, =3D=3D, 0); + g_assert_cmpuint(value, !=3D, secure_value); +} + +static void assert_default_bulk_read_isolated(QTestState *qts, uint64_t ad= dr, + char **before, + const uint8_t *expected, + size_t len) +{ + g_auto(GStrv) after =3D NULL; + g_autofree gchar *expected_b64 =3D NULL; + + expected_b64 =3D g_base64_encode(expected, len); + after =3D qtest_raw_cmd(qts, "b64read 0x%" PRIx64 " 0x%zx\n", addr, le= n); + + if (g_strcmp0(before[0], "ERR") =3D=3D 0) { + g_assert_cmpstr(after[0], =3D=3D, "ERR"); + return; + } + + g_assert_cmpstr(before[0], =3D=3D, "OK"); + g_assert_nonnull(before[1]); + g_assert_cmpstr(after[0], =3D=3D, "OK"); + g_assert_nonnull(after[1]); + g_assert_cmpstr(after[1], =3D=3D, before[1]); + g_assert_cmpstr(after[1], !=3D, expected_b64); +} + +static void test_x86_scalar_attrs(void) +{ + QTestState *qts; + g_auto(GStrv) before =3D NULL; + uint8_t val; + + if (!qtest_has_machine("q35")) { + g_test_skip("q35 machine not available"); + return; + } + + qts =3D qtest_init(X86_MACHINE_ARGS); + + qtest_writeb_attrs(qts, TEST_ADDR_X86, 0x11, NULL); + val =3D qtest_readb_attrs(qts, TEST_ADDR_X86, NULL); + g_assert_cmpuint(val, =3D=3D, 0x11); + + qtest_writeb_attrs(qts, TEST_ADDR_X86 + 0x1, 0x22, "secure"); + val =3D qtest_readb_attrs(qts, TEST_ADDR_X86 + 0x1, "secure"); + g_assert_cmpuint(val, =3D=3D, 0x22); + + before =3D qtest_raw_cmd(qts, "readb 0x%" PRIx64 "\n", + (uint64_t)(TEST_X86_SMM_BASE + 0x2)); + qtest_writeb_attrs(qts, TEST_X86_SMM_BASE + 0x2, 0x33, "secure"); + val =3D qtest_readb_attrs(qts, TEST_X86_SMM_BASE + 0x2, "secure"); + g_assert_cmpuint(val, =3D=3D, 0x33); + assert_default_scalar_read_isolated(qts, TEST_X86_SMM_BASE + 0x2, + before, 0x33); + + qtest_quit(qts); +} + +static void test_x86_bulk_attrs(void) +{ + QTestState *qts; + g_auto(GStrv) before =3D NULL; + uint8_t wbuf[8] =3D { 1, 2, 3, 4, 5, 6, 7, 8 }; + uint8_t rbuf[8]; + size_t i; + + if (!qtest_has_machine("q35")) { + g_test_skip("q35 machine not available"); + return; + } + + qts =3D qtest_init(X86_MACHINE_ARGS); + + qtest_memwrite_attrs(qts, TEST_ADDR_X86 + 0x100, wbuf, sizeof(wbuf), N= ULL); + qtest_memread_attrs(qts, TEST_ADDR_X86 + 0x100, rbuf, sizeof(rbuf), NU= LL); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_memwrite_attrs(qts, TEST_ADDR_X86 + 0x180, + wbuf, sizeof(wbuf), "secure"); + qtest_memread_attrs(qts, TEST_ADDR_X86 + 0x180, + rbuf, sizeof(rbuf), "secure"); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + before =3D qtest_raw_cmd(qts, "b64read 0x%" PRIx64 " 0x%zx\n", + (uint64_t)(TEST_X86_SMM_BASE + 0x100), + sizeof(wbuf)); + qtest_memwrite_attrs(qts, TEST_X86_SMM_BASE + 0x100, + wbuf, sizeof(wbuf), "secure"); + qtest_memread_attrs(qts, TEST_X86_SMM_BASE + 0x100, + rbuf, sizeof(rbuf), "secure"); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + assert_default_bulk_read_isolated(qts, TEST_X86_SMM_BASE + 0x100, befo= re, + wbuf, sizeof(wbuf)); + + qtest_memset_attrs(qts, TEST_X86_SMM_BASE + 0x120, + 0x5a, sizeof(rbuf), "secure"); + qtest_memread_attrs(qts, TEST_X86_SMM_BASE + 0x120, + rbuf, sizeof(rbuf), "secure"); + for (i =3D 0; i < sizeof(rbuf); i++) { + g_assert_cmpuint(rbuf[i], =3D=3D, 0x5a); + } + + qtest_bufwrite_attrs(qts, TEST_X86_SMM_BASE + 0x200, + wbuf, sizeof(wbuf), "secure"); + qtest_bufread_attrs(qts, TEST_X86_SMM_BASE + 0x200, + rbuf, sizeof(rbuf), "secure"); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_quit(qts); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + qtest_add_func("/qtest/x86/attrs/scalar", test_x86_scalar_attrs); + qtest_add_func("/qtest/x86/attrs/bulk", test_x86_bulk_attrs); + + return g_test_run(); +} --=20 2.34.1