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Mon, 30 Mar 2026 15:29:09 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Gerd Hoffmann Subject: [RFC PATCH] hw/display: modernise the vga debug code (!!GenAI!!) Date: Mon, 30 Mar 2026 23:28:59 +0100 Message-ID: <20260330222900.982404-1-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <6c3214ac-1679-d9db-2fed-c934fde8ddf2@eik.bme.hu> References: <6c3214ac-1679-d9db-2fed-c934fde8ddf2@eik.bme.hu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774909794171158500 Remove dead code, replace debug prints with trace points. Link: https://patchew.org/QEMU/20260330140656.46FE55969F2@zero.eik.bme.hu/ Signed-off-by: Alex Benn=C3=A9e --- As an experiment I prompted Gemini with the thread contents and asked it to make the changes. It cost about 9p in inference and I would argue this barely counts as copyrightable as it is a simple transformation of existing patterns. --- hw/display/vga.c | 89 ++++++++--------------------------------- hw/display/trace-events | 11 +++++ 2 files changed, 27 insertions(+), 73 deletions(-) diff --git a/hw/display/vga.c b/hw/display/vga.c index ee7d97b5c21..081a3b2576c 100644 --- a/hw/display/vga.c +++ b/hw/display/vga.c @@ -40,9 +40,6 @@ #include "migration/vmstate.h" #include "trace.h" =20 -//#define DEBUG_VGA_MEM -//#define DEBUG_VGA_REG - bool have_vga =3D true; =20 /* 16 state changes per vertical frame @60 Hz */ @@ -201,9 +198,6 @@ static void vga_precise_update_retrace_info(VGACommonSt= ate *s) int vretr_end_line; =20 int dots; -#if 0 - int div2, sldiv2; -#endif int clocking_mode; int clock_sel; const int clk_hz[] =3D {25175000, 28322000, 25175000, 25175000}; @@ -245,40 +239,9 @@ static void vga_precise_update_retrace_info(VGACommonS= tate *s) r->hend =3D r->hstart + hretr_end_char + 1; r->htotal =3D htotal_chars; =20 -#if 0 - div2 =3D (s->cr[VGA_CRTC_MODE] >> 2) & 1; - sldiv2 =3D (s->cr[VGA_CRTC_MODE] >> 3) & 1; - printf ( - "hz=3D%f\n" - "htotal =3D %d\n" - "hretr_start =3D %d\n" - "hretr_skew =3D %d\n" - "hretr_end =3D %d\n" - "vtotal =3D %d\n" - "vretr_start =3D %d\n" - "vretr_end =3D %d\n" - "div2 =3D %d sldiv2 =3D %d\n" - "clocking_mode =3D %d\n" - "clock_sel =3D %d %d\n" - "dots =3D %d\n" - "ticks/char =3D %" PRId64 "\n" - "\n", - (double) NANOSECONDS_PER_SECOND / (r->ticks_per_char * r->total_ch= ars), - htotal_chars, - hretr_start_char, - hretr_skew_chars, - hretr_end_char, - vtotal_lines, - vretr_start_line, - vretr_end_line, - div2, sldiv2, - clocking_mode, - clock_sel, - clk_hz[clock_sel], - dots, - r->ticks_per_char - ); -#endif + trace_vga_update_retrace_info(htotal_chars, vtotal_lines, + vretr_start_line, vretr_end_line, + dots, r->ticks_per_char); } =20 static uint8_t vga_precise_retrace(VGACommonState *s) @@ -358,9 +321,7 @@ uint32_t vga_ioport_read(void *opaque, uint32_t addr) break; case VGA_SEQ_D: val =3D s->sr[s->sr_index]; -#ifdef DEBUG_VGA_REG - printf("vga: read SR%x =3D 0x%02x\n", s->sr_index, val); -#endif + trace_vga_read_sr(s->sr_index, val); break; case VGA_PEL_IR: val =3D s->dac_state; @@ -386,9 +347,7 @@ uint32_t vga_ioport_read(void *opaque, uint32_t addr) break; case VGA_GFX_D: val =3D s->gr[s->gr_index]; -#ifdef DEBUG_VGA_REG - printf("vga: read GR%x =3D 0x%02x\n", s->gr_index, val); -#endif + trace_vga_read_gr(s->gr_index, val); break; case VGA_CRT_IM: case VGA_CRT_IC: @@ -397,9 +356,7 @@ uint32_t vga_ioport_read(void *opaque, uint32_t addr) case VGA_CRT_DM: case VGA_CRT_DC: val =3D s->cr[s->cr_index]; -#ifdef DEBUG_VGA_REG - printf("vga: read CR%x =3D 0x%02x\n", s->cr_index, val); -#endif + trace_vga_read_cr(s->cr_index, val); break; case VGA_IS1_RM: case VGA_IS1_RC: @@ -467,9 +424,7 @@ void vga_ioport_write(void *opaque, uint32_t addr, uint= 32_t val) s->sr_index =3D val & 7; break; case VGA_SEQ_D: -#ifdef DEBUG_VGA_REG - printf("vga: write SR%x =3D 0x%02x\n", s->sr_index, val); -#endif + trace_vga_write_sr(s->sr_index, val); s->sr[s->sr_index] =3D val & sr_mask[s->sr_index]; if (s->sr_index =3D=3D VGA_SEQ_CLOCK_MODE) { s->update_retrace_info(s); @@ -498,9 +453,7 @@ void vga_ioport_write(void *opaque, uint32_t addr, uint= 32_t val) s->gr_index =3D val & 0x0f; break; case VGA_GFX_D: -#ifdef DEBUG_VGA_REG - printf("vga: write GR%x =3D 0x%02x\n", s->gr_index, val); -#endif + trace_vga_write_gr(s->gr_index, val); s->gr[s->gr_index] =3D val & gr_mask[s->gr_index]; vbe_update_vgaregs(s); vga_update_memory_access(s); @@ -511,9 +464,7 @@ void vga_ioport_write(void *opaque, uint32_t addr, uint= 32_t val) break; case VGA_CRT_DM: case VGA_CRT_DC: -#ifdef DEBUG_VGA_REG - printf("vga: write CR%x =3D 0x%02x\n", s->cr_index, val); -#endif + trace_vga_write_cr(s->cr_index, val); /* handle CR0-7 protection */ if ((s->cr[VGA_CRTC_V_SYNC_END] & VGA_CR11_LOCK_CR0_CR7) && s->cr_index <=3D VGA_CRTC_OVERFLOW) { @@ -873,9 +824,7 @@ void vga_mem_writeb(VGACommonState *s, hwaddr addr, uin= t32_t val) uint32_t write_mask, bit_mask, set_mask; int plane =3D 0; =20 -#ifdef DEBUG_VGA_MEM - printf("vga: [0x" HWADDR_FMT_plx "] =3D 0x%02x\n", addr, val); -#endif + trace_vga_vram_write(addr, val); /* convert to VGA memory offset */ memory_map_mode =3D (s->gr[VGA_GFX_MISC] >> 2) & 3; addr &=3D 0x1ffff; @@ -945,9 +894,7 @@ void vga_mem_writeb(VGACommonState *s, hwaddr addr, uin= t32_t val) if (sr(s, VGA_SEQ_MEMORY_MODE) & VGA_SR04_CHN_4M) { if (mask) { s->vram_ptr[(addr << 2) | plane] =3D val; -#ifdef DEBUG_VGA_MEM - printf("vga: chain4: [0x" HWADDR_FMT_plx "]\n", addr); -#endif + trace_vga_vram_write((addr << 2) | plane, val); s->plane_updated |=3D mask; /* only used to detect font change= */ memory_region_set_dirty(&s->vram, addr, 1); } @@ -1021,10 +968,7 @@ do_write: ((uint32_t *)s->vram_ptr)[addr] =3D (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) | (val & write_mask); -#ifdef DEBUG_VGA_MEM - printf("vga: latch: [0x" HWADDR_FMT_plx "] mask=3D0x%08x val=3D0x%08x\= n", - addr * 4, write_mask, val); -#endif + trace_vga_vram_latch_write(addr << 2, write_mask, val); memory_region_set_dirty(&s->vram, addr << 2, sizeof(uint32_t)); } =20 @@ -1660,11 +1604,10 @@ static void vga_draw_graphic(VGACommonState *s, int= full_update) s->cursor_invalidate(s); } =20 -#if 0 - printf("w=3D%d h=3D%d v=3D%d line_offset=3D%d cr[0x09]=3D0x%02x cr[0x1= 7]=3D0x%02x linecmp=3D%d sr[0x01]=3D0x%02x\n", - width, height, v, line_offset, s->cr[9], s->cr[VGA_CRTC_MODE], - s->params.line_compare, sr(s, VGA_SEQ_CLOCK_MODE)); -#endif + trace_vga_draw_graphic(width, height, v, s->params.line_offset, + s->cr[9], s->cr[VGA_CRTC_MODE], + s->params.line_compare, sr(s, VGA_SEQ_CLOCK_MOD= E)); + addr1 =3D (s->params.start_addr * 4); y_start =3D -1; d =3D surface_data(surface); diff --git a/hw/display/trace-events b/hw/display/trace-events index 4bfc457fbac..c6591c90ca8 100644 --- a/hw/display/trace-events +++ b/hw/display/trace-events @@ -130,6 +130,17 @@ vga_std_read_io(uint32_t addr, uint32_t val) "addr 0x%= x, val 0x%x" vga_std_write_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x" vga_vbe_read(uint32_t index, uint32_t val) "index 0x%x, val 0x%x" vga_vbe_write(uint32_t index, uint32_t val) "index 0x%x, val 0x%x" +vga_vram_read(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%x" +vga_vram_write(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%x" +vga_vram_latch_write(uint64_t addr, uint32_t mask, uint32_t val) "addr 0x%= "PRIx64" mask 0x%08x val 0x%08x" +vga_read_sr(uint32_t index, uint32_t val) "index 0x%x, val 0x%x" +vga_write_sr(uint32_t index, uint32_t val) "index 0x%x, val 0x%x" +vga_read_gr(uint32_t index, uint32_t val) "index 0x%x, val 0x%x" +vga_write_gr(uint32_t index, uint32_t val) "index 0x%x, val 0x%x" +vga_read_cr(uint32_t index, uint32_t val) "index 0x%x, val 0x%x" +vga_write_cr(uint32_t index, uint32_t val) "index 0x%x, val 0x%x" +vga_draw_graphic(uint32_t w, uint32_t h, uint32_t v, uint32_t line_offset,= uint32_t cr09, uint32_t cr17, uint32_t linecmp, uint32_t sr01) "w=3D%u h= =3D%u v=3D%u line_offset=3D%u cr[0x09]=3D0x%02x cr[0x17]=3D0x%02x linecmp= =3D%u sr[0x01]=3D0x%02x" +vga_update_retrace_info(uint32_t htotal, uint32_t vtotal, uint32_t vretr_s= tart, uint32_t vretr_end, uint32_t dots, uint64_t ticks_per_char) "htotal %= u, vtotal %u, vretr_start %u, vretr_end %u, dots %u, ticks/char %"PRIu64 =20 # cirrus_vga.c vga_cirrus_read_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x" --=20 2.47.3