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Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5.c | 58 ++++++++++++++++++++++++++++++ hw/intc/trace-events | 1 + include/hw/intc/arm_gicv5_stream.h | 23 ++++++++++++ 3 files changed, 82 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 605cf6fd6f..942f3eba2e 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -1095,6 +1095,64 @@ uint64_t gicv5_request_config(GICv5Common *cs, uint3= 2_t id, GICv5Domain domain, } } =20 +void gicv5_activate(GICv5Common *cs, uint32_t id, GICv5Domain domain, + GICv5IntType type, bool virtual) +{ + GICv5 *s =3D ARM_GICV5(cs); + uint32_t iaffid; + + trace_gicv5_activate(domain_name[domain], inttype_name(type), virtual,= id); + + if (virtual) { + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_activate: tried to " + "activate a virtual interrupt\n"); + return; + } + + switch (type) { + case GICV5_LPI: + { + const GICv5ISTConfig *cfg =3D &s->phys_lpi_config[domain]; + L2_ISTE_Handle h; + uint32_t *l2_iste_p =3D get_l2_iste(cs, cfg, id, &h); + + if (!l2_iste_p) { + return; + } + *l2_iste_p =3D FIELD_DP32(*l2_iste_p, L2_ISTE, ACTIVE, true); + if (FIELD_EX32(*l2_iste_p, L2_ISTE, HM) =3D=3D GICV5_EDGE) { + *l2_iste_p =3D FIELD_DP32(*l2_iste_p, L2_ISTE, PENDING, false); + } + iaffid =3D FIELD_EX32(*l2_iste_p, L2_ISTE, IAFFID); + put_l2_iste(cs, cfg, &h); + break; + } + case GICV5_SPI: + { + GICv5SPIState *spi =3D gicv5_spi_state(cs, id, domain); + + if (!spi) { + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_activate: tried to " + "activate unreachable SPI %d\n", id); + return; + } + + spi->active =3D true; + if (spi->hm =3D=3D GICV5_EDGE) { + spi->pending =3D false; + } + iaffid =3D spi->iaffid; + break; + } + default: + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_activate: tried to " + "activate bad interrupt type %d\n", type); + return; + } + + irs_recalc_hppi(s, domain, iaffid); +} + static void irs_map_l2_istr_write(GICv5 *s, GICv5Domain domain, uint64_t v= alue) { GICv5Common *cs =3D ARM_GICV5_COMMON(s); diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 6475ba5959..636c598970 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -241,6 +241,7 @@ gicv5_set_pending(const char *domain, const char *type,= bool virtual, uint32_t i gicv5_set_handling(const char *domain, const char *type, bool virtual, uin= t32_t id, int handling) "GICv5 IRS SetHandling %s %s virtual:%d ID %u handl= ing %d" gicv5_set_target(const char *domain, const char *type, bool virtual, uint3= 2_t id, uint32_t iaffid, int irm) "GICv5 IRS SetTarget %s %s virtual:%d ID = %u IAFFID %u routingmode %d" gicv5_request_config(const char *domain, const char *type, bool virtual, u= int32_t id, uint64_t icsr) "GICv5 IRS RequestConfig %s %s virtual:%d ID %u = ICSR 0x%" PRIx64 +gicv5_activate(const char *domain, const char *type, bool virtual, uint32_= t id) "GICv5 IRS Activate %s %s virtual:%d ID %u" gicv5_spi_state(uint32_t spi_id, bool level, bool pending, bool active) "G= ICv5 IRS SPI ID %u now level %d pending %d active %d" gicv5_irs_recalc_hppi_fail(const char *domain, uint32_t iaffid, const char= *reason) "GICv5 IRS %s IAFFID %u: no HPPI: %s" gicv5_irs_recalc_hppi(const char *domain, uint32_t iaffid, uint32_t id, ui= nt8_t prio) "GICv5 IRS %s IAFFID %u: new HPPI ID 0x%x prio %u" diff --git a/include/hw/intc/arm_gicv5_stream.h b/include/hw/intc/arm_gicv5= _stream.h index cc1c7cc438..7ac24f0f09 100644 --- a/include/hw/intc/arm_gicv5_stream.h +++ b/include/hw/intc/arm_gicv5_stream.h @@ -151,6 +151,29 @@ void gicv5_set_target(GICv5Common *cs, uint32_t id, ui= nt32_t iaffid, uint64_t gicv5_request_config(GICv5Common *cs, uint32_t id, GICv5Domain do= main, GICv5IntType type, bool virtual); =20 +/** + * gicv5_activate + * @cs: GIC IRS to send command to + * @id: interrupt ID + * @domain: interrupt domain to act on + * @type: interrupt type (LPI or SPI) + * @virtual: true if this is a virtual interrupt + * + * Activate the IRS's highest priority pending interrupt; matches the + * stream interface's Activate command. + * + * In the stream interface, the command has only the domain and + * virtual fields, because both the IRS and the CPUIF keep track of + * the IRS's current HPPI. In QEMU, we also have arguments here for + * @id and @type which are telling the IRS something that in hardware + * it already knows. This is because we have them to hand in the cpuif + * code, and it means we don't need to pass in an iaffid argument to + * tell the IRS which CPU we are so it can find the right element in + * its hppi[][] array. + */ +void gicv5_activate(GICv5Common *cs, uint32_t id, GICv5Domain domain, + GICv5IntType type, bool virtual); + /** * gicv5_forward_interrupt * @cpu: CPU interface to forward interrupt to --=20 2.43.0