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These hold the physical priority mask for each interrupt domain -- an HPPI is only sufficiently high priority to preempt if it is higher priority than this mask value. Here we just implement the access to this data. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- target/arm/cpu.h | 1 + target/arm/tcg/gicv5-cpuif.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1263841a1d..651fccd59b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -606,6 +606,7 @@ typedef struct CPUArchState { uint64_t icc_icsr_el1; uint64_t icc_apr[NUM_GICV5_DOMAINS]; uint64_t icc_cr0[NUM_GICV5_DOMAINS]; + uint64_t icc_pcr[NUM_GICV5_DOMAINS]; /* Most PPI registers have 1 bit per PPI, so 64 PPIs to a register= */ uint64_t ppi_active[GICV5_NUM_PPIS / 64]; uint64_t ppi_hm[GICV5_NUM_PPIS / 64]; diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 50aa81d74f..b44b0d5398 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -49,6 +49,8 @@ FIELD(ICC_CR0, LINK_IDLE, 2, 1) FIELD(ICC_CR0, IPPT, 32, 6) FIELD(ICC_CR0, PID, 38, 1) =20 +FIELD(ICC_PCR, PRIORITY, 0, 5) + /* * We implement 24 bits of interrupt ID, the mandated 5 bits of priority, * and no legacy GICv3.3 vcpu interface (yet) @@ -383,6 +385,28 @@ static void gic_icc_cr0_el1_reset(CPUARMState *env, co= nst ARMCPRegInfo *ri) } } =20 +static uint64_t gic_icc_pcr_el1_read(CPUARMState *env, const ARMCPRegInfo = *ri) +{ + GICv5Domain domain =3D gicv5_logical_domain(env); + return env->gicv5_cpuif.icc_pcr[domain]; +} + +static void gic_icc_pcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + GICv5Domain domain =3D gicv5_logical_domain(env); + + value &=3D R_ICC_PCR_PRIORITY_MASK; + env->gicv5_cpuif.icc_pcr[domain] =3D value; +} + +static void gic_icc_pcr_el1_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + for (int i =3D 0; i < ARRAY_SIZE(env->gicv5_cpuif.icc_pcr); i++) { + env->gicv5_cpuif.icc_pcr[i] =3D 0; + } +} + static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { /* * Barrier: wait until the effects of a cpuif system register @@ -548,6 +572,13 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { .writefn =3D gic_icc_cr0_el1_write, .resetfn =3D gic_icc_cr0_el1_reset, }, + { .name =3D "ICC_PCR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 12, .crm =3D 0, .opc2 =3D 2, + .access =3D PL1_RW, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .readfn =3D gic_icc_pcr_el1_read, + .writefn =3D gic_icc_pcr_el1_write, + .resetfn =3D gic_icc_pcr_el1_reset, + }, { .name =3D "ICC_HAPR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 1, .crn =3D 12, .crm =3D 0, .opc2 =3D 3, .access =3D PL1_R, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, --=20 2.43.0