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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610260; x=1775215060; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zO8+icgVC1WFthhuPn3fXGZ2vtbwSvDSsbRmXizchEg=; b=K0GALIVUDmPhEb5XC8jfilPkeXQOC787b12Aufx4QcU1urwnyknIRuqU40HlPvJ4OP wM3x6A0HMSsf9heH1zTmAqLnjN5QEiRUTfvIGpTWmPSeD9bMsIcwDcWOFrHX+f8cvHP4 JGf9S0UPkjBPcBP693XaZqIom4roLBoGzT0+zBBPxAHuhDrqTfVQ1Sn+ttBpHBFgiRZh TAC28VEQ66ZCFM74Pu7J73zMZZGe0Qb2++Ka2Q0h4S7ZrljVVAKw0iLtzsjAIoLXOJUm YcAny0oRZzhUfJmQVN8BfSBr+x5mctD1jXmX0lDHEaRHv3E2mdTqrp3KEmHh8Cm0klbK 1cdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610260; x=1775215060; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=zO8+icgVC1WFthhuPn3fXGZ2vtbwSvDSsbRmXizchEg=; b=JR0Mx11R4ybtaqqijvBJEUpVUPl5zz9dvdPTpegeZaSAgf/95e6WuwfCBSGFJci6sH XG+BNZl0C20JSusyAQ1cljlpr/8b+1ODXrslbUoVuPjivscp0BQqW328yrUlgahpbHsu UXohFXgQNia0GByqhFbrwo4UB/L3Ia58Q0t1cg8LiWcD3h/DjbC+zCh4dTIivAqsWuBy oAyhdkERhdaXqpv3jom4xzaZVRgs+ThIos72DiNkbn+ngpdaeNKmiJb+LyJpTvvh5MQH CbpExp9ziWQ8logbq8LpZAvXvzKm9Zaeew83EduqDFLwWyUdvDT2+rooLCVILm8yOpVx KAqA== X-Forwarded-Encrypted: i=1; AJvYcCWcHFvWjGtpyAVnjbUyfukv96u8n6z+r1kakOyDg/uQrUHnFJbgQ/PVZtlqSU7Eh/tXPHZhhxK80OMK@nongnu.org X-Gm-Message-State: AOJu0YyGxy1Dcs/egOEtTwQYRRjA/tqlb/icCAuBdbP3FyowzmqNN1cP KfmHTbB5TT/z4bUs+n/UvN+ghBJl8sDB/DWWaDEq3GzNrS4/l0Nde5gz2PODWGAYAGo= X-Gm-Gg: ATEYQzxfl0ubSeI3upbP53ZZFuC7URzHNYzJbHY/vtYdeNI4bpWIWOxuxfwOXjH/GpR cNa1F7h2pUg3144ypv9CgvzikvQsoqOkNqCO/Sh6Wvx21CkeaRLWleZvz/BiJnKUK8OYJQ2gnJQ Lmg82CtkZU1DvzPQMu1Lh1IIdKIq/1H9TOWB481ck6EVZQ+Tja32FE7GkFgHklalG46wvbxJa8+ KypzqNUG8g3WUp2Wjmkqbh8zCgPvHJJXvsKBAFL0M6SLSMk7KloHdTZNZL9+0+2HuFNxcWSJtmB pVgC6yar1ZJ0KHEckQ0OpYMhFVfIwkIjPAIVHcbFZPBhITWycEknjUrJEzqC5bLmrjZawXyQW73 1vnScfSRch22oBXI24lxHdc68itt9RFpzJ3gHGVpOY4UWi7jdZIiBrUZM7slIPkgpm9uToUVs4s g5CpsZ+PshOVyMKavxwqaVOJETe/nxNgPDGfsy1QrFBAMkN57DoNClRLz42NQrluh70w40wgcqC vPt6+JrN8l86R8Ggm/3YedvmMtjmI0= X-Received: by 2002:a05:600c:4e55:b0:485:4533:9c47 with SMTP id 5b1f17b1804b1-48727ec77a9mr37014825e9.22.1774610260204; Fri, 27 Mar 2026 04:17:40 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 40/65] target/arm: GICv5 cpuif: Implement PPI priority registers Date: Fri, 27 Mar 2026 11:16:35 +0000 Message-ID: <20260327111700.795099-41-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_FILL_THIS_FORM_SHORT=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610613686154100 Content-Type: text/plain; charset="utf-8" Implement the GICv5 registers which hold the priority of the PPIs. Each 64-bit register has the priority fields for 8 PPIs, so there are 16 registers in total. This would be a lot of duplication if we wrote it out statically in the array, so instead create each register via a loop in define_gicv5_cpuif_regs(). Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- target/arm/cpu.h | 2 ++ target/arm/tcg/gicv5-cpuif.c | 23 +++++++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 915a225f8e..b97f659352 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -608,6 +608,8 @@ typedef struct CPUArchState { uint64_t ppi_hm[GICV5_NUM_PPIS / 64]; uint64_t ppi_pend[GICV5_NUM_PPIS / 64]; uint64_t ppi_enable[GICV5_NUM_PPIS / 64]; + /* The PRIO regs have 1 byte per PPI, so 8 PPIs to a register */ + uint64_t ppi_priority[GICV5_NUM_PPIS / 8]; } gicv5_cpuif; =20 struct { diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 09cd56cbfa..74132ca097 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -225,6 +225,12 @@ static void gic_ppi_enable_write(CPUARMState *env, con= st ARMCPRegInfo *ri, raw_write(env, ri, value); } =20 +static void gic_ppi_priority_write(CPUARMState *env, const ARMCPRegInfo *r= i, + uint64_t value) +{ + raw_write(env, ri, value); +} + static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { /* * Barrier: wait until the effects of a cpuif system register @@ -382,5 +388,22 @@ void define_gicv5_cpuif_regs(ARMCPU *cpu) { if (cpu_isar_feature(aa64_gcie, cpu)) { define_arm_cp_regs(cpu, gicv5_cpuif_reginfo); + + /* + * There are 16 ICC_PPI_PRIORITYR_EL1 regs, so define them + * programmatically rather than listing them all statically. + */ + for (int i =3D 0; i < 16; i++) { + g_autofree char *name =3D g_strdup_printf("ICC_PPI_PRIORITYR%d= _EL1", i); + ARMCPRegInfo ppi_prio =3D { + .name =3D name, .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, + .crm =3D 14 + (i >> 3), .opc2 =3D i & 7, + .access =3D PL1_RW, .type =3D ARM_CP_IO, + .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_pri= ority[i]), + .writefn =3D gic_ppi_priority_write, .raw_writefn =3D raw_= write, + }; + define_one_arm_cp_reg(cpu, &ppi_prio); + } } } --=20 2.43.0