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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610259; x=1775215059; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7oXt+HGm1k+OhZUlKvZnQCKSizbDBAvFnTtOI2ID7Ok=; b=r0fDB4E9MZUHtpkrQaJ8ue+BgUxRYyPUUAy1NJV+C2Hx5ScJAvDjk0MH0t6yEpW69f Mgrkg9o9CghD3MwsNYJab4BvFA9/672Oh6IXJFg4ud5ReFzvkUimtkA55Int8U5sERDd GYIvM6/+L+tAMTHNArACGyT6uugYwyyUyyLtNoPWCCsx6ZQAmaWTKZjq0rBiRjoMeLMV pOnEpE80b4QVtxtEg91/e6DbcRQ2ssVMZ+g8M/HrbEtHXtacApKB/lUatf/vj4i4XUnm YCRYl0vKZ1jrLa4EgRVRGOPt0OQmsH2qG20bAnpdA0P/WxziyBsNrs4J0v7zpAt4IG3f l6Mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610259; x=1775215059; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=7oXt+HGm1k+OhZUlKvZnQCKSizbDBAvFnTtOI2ID7Ok=; b=c3KSFbjqSfeSAPhjRDXAKWnH6KJgBBVYB70A0MsN4+BTNywKjJ8E5YBR4UBiDtv8vz fisqOhZvh038R/nIHWRvcU9qPgzmpAREB3uxGYc3GSfW3WTcT6HDYElQKgPS81RmM1KW McUIQp0BuTsivoZW4XI/NvRX217GQq3XkCPMxD7Nj/1zurDfN9F0olzEilwYPkwYsMNU vW4+4CQCnRCxY/0JrQxZsNmKkxZwjsI1AhEXaFNDpr9x+RCNqpvM6640GLjTWoFQcCTt Oc/LRBP4KUOtMSlsAdJxnSYAEwf2iUAkWBBz5AuTqZY4gV/9mRGjMwMCoxsIPTiFEZxL GTGA== X-Forwarded-Encrypted: i=1; AJvYcCXl4kSG4W+N+HLIa4s4ffdIzdDoHSodhffHRHAure9hn6MJQThxErs7Usa6P8k102q/Mdcs/lgaFlKh@nongnu.org X-Gm-Message-State: AOJu0YwAcCxhgUqJECHB5XpYoSVzknstjobI05FSUumMmKqVlylxqWrQ FfMq8CFv3SbUugpIjZvj1U5hu5rsDZ2ij/CocpneNY2VlBQfE3gpwhWpVDvlEZH/toA= X-Gm-Gg: ATEYQzxmbTLQgKgNVO2281iR/G0iizzjOoOOpqheOLrXjMotvVd+ulestZm35IUhrE4 3eV+SD8jWlDz2VP+dEws6+K7ZO4d0jtAiiZf4jdRfhbauYJ1g81nsQO0G0EQGfquslNOOQnIo/Q LiOPuxaqredlTCNED4bNDwTcMV1CAdIyBd7o6to9Sn+8d9+FE88RNI7W8oaf0mbIZD52hIn2+Nl RJKYu0oYE288w+6NW0IDkt7JaAnxUgb6qE3PtP/dmvUs7QOqtauJfMY9MeVV3t7BOD/TWJtSWv9 ELjuwT8xkvpA2PKOgNP+giH2/k8U00QhjmBpDPaNiwBvKb3l+ITXxF7pcJNDl0D4C+iHQA7Na9k T14Ghe7kGt91QNBubTdkAwLVhkXpXbZB2CtU28+jniSroOVpMyx8RyNVAP+abtEX2NB+qaFblGw iM97QzeWwOf0QAqCVvis+xwBJJZjc3FXAxd7BguJZro5KrR4KKn/eNCiIfOv0+1ROJzT9cZ9uyO nZhv+r+9ok+pHhPtdOeqWzx5TG9hqs= X-Received: by 2002:a05:6000:4703:b0:43b:9fee:939f with SMTP id ffacd0b85a97d-43b9fee9571mr2783082f8f.5.1774610259262; Fri, 27 Mar 2026 04:17:39 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 39/65] target/arm: GICv5 cpuif: Implement PPI enable register Date: Fri, 27 Mar 2026 11:16:34 +0000 Message-ID: <20260327111700.795099-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610689906158500 Content-Type: text/plain; charset="utf-8" Implement the GICv5 register which holds the enable state of PPIs: ICC_PPI_ENABLER_EL1. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- target/arm/cpu.h | 1 + target/arm/tcg/gicv5-cpuif.c | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 980abda3ca..915a225f8e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -607,6 +607,7 @@ typedef struct CPUArchState { uint64_t ppi_active[GICV5_NUM_PPIS / 64]; uint64_t ppi_hm[GICV5_NUM_PPIS / 64]; uint64_t ppi_pend[GICV5_NUM_PPIS / 64]; + uint64_t ppi_enable[GICV5_NUM_PPIS / 64]; } gicv5_cpuif; =20 struct { diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index ee97d98d7e..09cd56cbfa 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -219,6 +219,12 @@ static void gic_ppi_spend_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, raw_write(env, ri, old | value); } =20 +static void gic_ppi_enable_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + raw_write(env, ri, value); +} + static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { /* * Barrier: wait until the effects of a cpuif system register @@ -334,6 +340,18 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_hm[1]), .resetvalue =3D PPI_HMR1_RESET, }, + { .name =3D "ICC_PPI_ENABLER0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 10, .opc2 =3D 6, + .access =3D PL1_RW, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_enable[0]), + .writefn =3D gic_ppi_enable_write, + }, + { .name =3D "ICC_PPI_ENABLER1_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 10, .opc2 =3D 7, + .access =3D PL1_RW, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_enable[1]), + .writefn =3D gic_ppi_enable_write, + }, { .name =3D "ICC_PPI_CPENDR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 13, .opc2 =3D 4, .access =3D PL1_RW, .type =3D ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO= _RAW, --=20 2.43.0