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Iterating through this to identify the highest priority pending interrupt would be expensive; to avoid this we will use a hash table which contains an entry for each pending LPI and which caches the L2 ISTE. Typically only a few LPIs will be pending at any one time, so iterating through the hash table should be fast. We can access an L2 ISTE whenever it is valid, and can freely cache the data for as long as the IST is valid. We only need to ensure that we have written back the data at the point where IRS_IST_BASER.VALID is written to 0. We add an LPI to the cache when the pending bit is written to 1, and remove it when it is written to 0. Handling of checking the cache, and of adding and removing entries, is handled within get_l2_iste() and put_l2_iste(), which all the operations that read and write ISTE words use. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5.c | 116 ++++++++++++++++++++++++++++++++++-- include/hw/intc/arm_gicv5.h | 2 + 2 files changed, 112 insertions(+), 6 deletions(-) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 866c1333c3..989492d4b6 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -471,15 +471,22 @@ static bool write_l2_iste_mem(GICv5Common *cs, const = GICv5ISTConfig *cfg, =20 /* * This is returned by get_l2_iste() and has everything we need to do - * the writeback of the L2 ISTE word in put_l2_iste(). Currently the - * get/put functions always directly do guest memory reads and writes - * to update the L2 ISTE. In a future commit we will add support for a - * cache of some of the ISTE data in a local hashtable; the APIs are - * designed with that in mind. + * the writeback of the L2 ISTE word in put_l2_iste(). Not all these + * fields are always valid; they are private to the implementation of + * get_l2_iste() and put_l2_iste(). */ typedef struct L2_ISTE_Handle { + /* Guest memory address of the L2 ISTE; valid only if !hashed */ hwaddr l2_iste_addr; - uint32_t l2_iste; + union { + /* Actual L2_ISTE word; valid only if !hashed */ + uint32_t l2_iste; + /* Pointer to L2 ISTE word; valid only if hashed */ + uint32_t *l2_iste_p; + }; + uint32_t id; + /* True if this ISTE is currently in the cache */ + bool hashed; } L2_ISTE_Handle; =20 static uint32_t *get_l2_iste(GICv5Common *cs, const GICv5ISTConfig *cfg, @@ -499,6 +506,25 @@ static uint32_t *get_l2_iste(GICv5Common *cs, const GI= Cv5ISTConfig *cfg, * If the ISTE could not be read (typically because of a memory * error), return NULL. */ + uint32_t *hashvalue; + + if (!cfg->valid) { + /* Catch invalid config early, it has no lpi_cache */ + return NULL; + } + + hashvalue =3D g_hash_table_lookup(cfg->lpi_cache, + GINT_TO_POINTER(id)); + + h->id =3D id; + + if (hashvalue) { + h->hashed =3D true; + h->l2_iste_p =3D hashvalue; + return hashvalue; + } + + h->hashed =3D false; if (!get_l2_iste_addr(cs, cfg, id, &h->l2_iste_addr) || !read_l2_iste_mem(cs, cfg, h->l2_iste_addr, &h->l2_iste)) { return NULL; @@ -514,6 +540,34 @@ static void put_l2_iste(GICv5Common *cs, const GICv5IS= TConfig *cfg, * Once this has been called the L2_ISTE_Handle @h and the pointer * to the L2 ISTE word are no longer valid. */ + if (h->hashed) { + uint32_t l2_iste =3D *h->l2_iste_p; + if (!FIELD_EX32(l2_iste, L2_ISTE, PENDING)) { + /* + * We just made this not pending: remove from hash table + * and write back to memory. + */ + hwaddr l2_iste_addr; + + g_hash_table_remove(cfg->lpi_cache, GINT_TO_POINTER(h->id)); + if (get_l2_iste_addr(cs, cfg, h->id, &l2_iste_addr)) { + write_l2_iste_mem(cs, cfg, l2_iste_addr, l2_iste); + /* Writeback errors are ignored. */ + } + } + return; + } + + if (FIELD_EX32(h->l2_iste, L2_ISTE, PENDING)) { + /* + * We just made this pending: add it to the hash table, and + * don't bother writing it back to memory. + */ + uint32_t *hashvalue =3D g_new(uint32_t, 1); + *hashvalue =3D h->l2_iste; + g_hash_table_insert(cfg->lpi_cache, GINT_TO_POINTER(h->id), hashva= lue); + return; + } write_l2_iste_mem(cs, cfg, h->l2_iste_addr, h->l2_iste); } =20 @@ -896,6 +950,39 @@ txfail: "physical address 0x" HWADDR_FMT_plx "\n", intid, l1_add= r); } =20 +/* Data we need to pass through to irs_clean_lpi_cache_entry() */ +typedef struct CleanLPICacheUserData { + GICv5Common *cs; + GICv5ISTConfig *cfg; +} CleanLPICacheUserData; + +static gboolean irs_clean_lpi_cache_entry(gpointer key, gpointer value, + gpointer user_data) +{ + /* Drop this entry from the LPI cache, writing it back to guest memory= . */ + CleanLPICacheUserData *ud =3D user_data; + hwaddr l2_iste_addr; + uint64_t id =3D GPOINTER_TO_INT(key); + uint32_t l2_iste =3D *(uint32_t *)value; + + if (!get_l2_iste_addr(ud->cs, ud->cfg, id, &l2_iste_addr) || + !write_l2_iste_mem(ud->cs, ud->cfg, l2_iste_addr, l2_iste)) { + /* We drop the cached entry regardless of writeback errors */ + return true; + } + return true; +} + +static void irs_clean_lpi_cache(GICv5Common *cs, GICv5ISTConfig *cfg) +{ + /* Write everything in the LPI cache out to guest memory */ + CleanLPICacheUserData ud; + ud.cs =3D cs; + ud.cfg =3D cfg; + + g_hash_table_foreach_remove(cfg->lpi_cache, irs_clean_lpi_cache_entry,= &ud); +} + static void irs_ist_baser_write(GICv5 *s, GICv5Domain domain, uint64_t val= ue) { GICv5Common *cs =3D ARM_GICV5_COMMON(s); @@ -907,6 +994,7 @@ static void irs_ist_baser_write(GICv5 *s, GICv5Domain d= omain, uint64_t value) /* Ignore 1->1 transition */ return; } + irs_clean_lpi_cache(cs, &s->phys_lpi_config[domain]); cs->irs_ist_baser[domain] =3D FIELD_DP64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID, valid= ); s->phys_lpi_config[domain].valid =3D false; @@ -968,6 +1056,15 @@ static void irs_ist_baser_write(GICv5 *s, GICv5Domain= domain, uint64_t value) cfg->l2_idx_bits =3D l2_idx_bits; cfg->structure =3D FIELD_EX64(cs->irs_ist_cfgr[domain], IRS_IST_CFGR, STRUCTURE); + if (!cfg->lpi_cache) { + /* + * Keys are GINT_TO_POINTER(intid), so we want the g_direct_ha= sh + * and g_direct_equal hash and equality functions. We don't + * want to free the keys, but we do want to free the values + * (which are pointer-to-uint32_t). + */ + cfg->lpi_cache =3D g_hash_table_new_full(NULL, NULL, NULL, g_f= ree); + } cfg->valid =3D true; trace_gicv5_ist_valid(domain_name[domain], cfg->base, cfg->id_bits, cfg->l2_idx_bits, cfg->istsz, cfg->structure= ); @@ -1428,6 +1525,13 @@ static void gicv5_reset_hold(Object *obj, ResetType = type) /* IRS_IST_BASER and IRS_IST_CFGR reset to 0, clear cached info */ for (int i =3D 0; i < NUM_GICV5_DOMAINS; i++) { s->phys_lpi_config[i].valid =3D false; + /* + * If we got reset (power-cycled) with data in the cache, don't + * write it out to guest memory; just return to "empty cache". + */ + if (s->phys_lpi_config[i].lpi_cache) { + g_hash_table_remove_all(s->phys_lpi_config[i].lpi_cache); + } } } =20 diff --git a/include/hw/intc/arm_gicv5.h b/include/hw/intc/arm_gicv5.h index c631ecc3e8..fb13de0d01 100644 --- a/include/hw/intc/arm_gicv5.h +++ b/include/hw/intc/arm_gicv5.h @@ -25,6 +25,8 @@ typedef struct GICv5ISTConfig { uint8_t istsz; /* L2 ISTE size in bytes */ bool structure; /* true if using 2-level table */ bool valid; /* true if this table is valid and usable */ + /* This caches IST information about pending LPIs */ + GHashTable *lpi_cache; } GICv5ISTConfig; =20 /* --=20 2.43.0