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The IRS_CR1 register has cacheability, shareability and cache hint information to use for IRS memory accesses; since QEMU doesn't care about this we can make it simply reads-as-written. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5.c | 13 +++++++++++++ hw/intc/arm_gicv5_common.c | 2 ++ include/hw/intc/arm_gicv5_common.h | 2 ++ 3 files changed, 17 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index bc887233f5..3f397d9115 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -1080,6 +1080,13 @@ static bool config_readl(GICv5 *s, GICv5Domain domai= n, hwaddr offset, } *data =3D v; return true; + case A_IRS_CR0: + /* Enabling is instantaneous for us so IDLE is always 1 */ + *data =3D cs->irs_cr0[domain] | R_IRS_CR0_IDLE_MASK; + return true; + case A_IRS_CR1: + *data =3D cs->irs_cr1[domain]; + return true; } =20 return false; @@ -1159,6 +1166,12 @@ static bool config_writel(GICv5 *s, GICv5Domain doma= in, hwaddr offset, trace_gicv5_spi_state(id, spi->level, spi->pending, spi->active); return true; } + case A_IRS_CR0: + cs->irs_cr0[domain] =3D data & R_IRS_CR0_IRSEN_MASK; + return true; + case A_IRS_CR1: + cs->irs_cr1[domain] =3D data; + return true; } =20 return false; diff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c index 0813f0ac66..b1c8ec4521 100644 --- a/hw/intc/arm_gicv5_common.c +++ b/hw/intc/arm_gicv5_common.c @@ -66,6 +66,8 @@ static void gicv5_common_reset_hold(Object *obj, ResetTyp= e type) =20 memset(cs->irs_ist_baser, 0, sizeof(cs->irs_ist_baser)); memset(cs->irs_ist_cfgr, 0, sizeof(cs->irs_ist_cfgr)); + memset(cs->irs_cr0, 0, sizeof(cs->irs_cr0)); + memset(cs->irs_cr1, 0, sizeof(cs->irs_cr1)); =20 if (cs->spi) { GICv5Domain mp_domain; diff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5= _common.h index 61d017bf38..ac0532abe8 100644 --- a/include/hw/intc/arm_gicv5_common.h +++ b/include/hw/intc/arm_gicv5_common.h @@ -84,6 +84,8 @@ struct GICv5Common { uint64_t irs_ist_baser[NUM_GICV5_DOMAINS]; uint32_t irs_ist_cfgr[NUM_GICV5_DOMAINS]; uint32_t irs_spi_selr[NUM_GICV5_DOMAINS]; + uint32_t irs_cr0[NUM_GICV5_DOMAINS]; + uint32_t irs_cr1[NUM_GICV5_DOMAINS]; =20 /* * Pointer to an array of state information for the SPIs. Array --=20 2.43.0