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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610249; x=1775215049; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xoyJziqdU/nken6or35eJw+c9H0GsrA0zPSsjs/9kKo=; b=wfEpRQj4+ZOWYQ/QpxkjZZo21umgPIEahwTvgyCVul4CY72Y1FKsDaIHW8FCQCBfYm THzE4jrJmrcrx4XS84j0ecrmmSXPeEypgW/5LGia0sADvV1J1TFoWeLSYT3cvDXrzPkF WSIJ6lWlskUr9jqLAZ5CQQND10SXbe8CJE5hjY3R4WHftGLK8274CiURaEWmVx73p6w3 hOF3VVdxja0xF1K4cJon+39PNachpbWzwBSguvxfDxcI64P77LwHZDxaum6jGmOFahjX 6RgI6jcyUNdQzhlpUtWk7hmxzUlh34ZiDd+meEiuxq3fG+eph15quS29e30+c0ugjuwR FEww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610249; x=1775215049; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=xoyJziqdU/nken6or35eJw+c9H0GsrA0zPSsjs/9kKo=; b=KR2QEJ8mCMFznnrgIHMI1gMNRjy47q8hvfDrSrqXP1V05D/8a6rnu1Yg9K1z5cmnd4 gU4B1F0IpsRXlHgYFZpFExa9T5OiFdjH/tuOPy1g3724iQiRgmdY/vOUHEQlNUM8NMW6 5619VURjjXixP1N+GoXUZJpD4WRTeuupCUWPpo+fUKvi+BtfHjsGV/rFDQSpHQZ7fHyK zZtLeGEXPCqhgYIlQ47+x4cYmQXJ0KooKoVB+EDMvCRd3+kKK8NKDXLMcfbyhNqu3r5N oUMEkAqM6eLr073YQ+1DYPtWVsOaQPndrPfEwMudruzgtg5ejHGk8AQj3c2gJ17MmyXn g3Pg== X-Forwarded-Encrypted: i=1; AJvYcCXFhKQ9ptDNpNbUEYO9KjdMCVh7ZywmYj0tEslWp/KLNxb3Ofr90WWyVvTFWjwE0Dx/9sxqza7WliSp@nongnu.org X-Gm-Message-State: AOJu0YyhlH9YRSG5cYu+IrEYILTDH+Z+/+Ya3K9z5dDoaazIQhBO3J+y ylEzACEVInAWcUqpM9Fds2rqkb0i0e7hQ0W3u0o/1bejKZEjZnWizEYJBTJ/XKgRuKE= X-Gm-Gg: ATEYQzxlWrye7sAbSQRxy+pkZMZ3TWauGyDFPsOzBA4gArNWE/icFSZ8haHqF9Sm3R3 FI3QQN9M4/8PjGzbFglV/n71wfwqkPtYVmx7q74BROS5b+WtMUl7e0azWd7Mw3Ooqt7iveZjMip veTTvx6KOpkTj/n90DwqiCrawTpANMldbc6sMat2d2D30x2AHz3PyikqoCExh5/YvDGq1VzbsF5 CD0hpKkivc6Hqpn++2wdgbQaYiejplWhv8LLTGWPd4vZGEQONrYMJbVohcFVZxw4CVv9j30ipla NF9RXlkpqx6SDGcWroGhH4SrO4TOFU5FOrG/P/fzMOU9CXPcauPnoJ736MdLizl/x1N95hrDk8l OwHf92CF4bodH2TsdDU3duHrmM9YYoUnb4pw4gOpoKjL2ausoALOMyjMAhAnPA0IcPXpf7CBrk8 7ZNA48PAxYSgLxTkMjB31E9KTQlAuvANjQc/V/fl3nVYvKD6WtvTp8ZmhKDLQxolmhhDD20/N1P BONKW9vOromS3Ct6wTOAgRntlYIE+rzC307pFfNDw== X-Received: by 2002:a05:6000:220c:b0:439:ca7b:f4b with SMTP id ffacd0b85a97d-43b9ea77996mr3253924f8f.50.1774610248816; Fri, 27 Mar 2026 04:17:28 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 28/65] hw/intc/arm_gicv5: Update SPI state for CLEAR/SET events Date: Fri, 27 Mar 2026 11:16:23 +0000 Message-ID: <20260327111700.795099-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610284221154100 Content-Type: text/plain; charset="utf-8" When an SPI irq line changes level, this causes what the spec describes as SET_LEVEL, SET_EDGE or CLEAR events. These also happen when the trigger mode is reconfigured, or when software requests a manual resample via the IRS_SPI_RESAMPLER register. SET_LEVEL and SET_EDGE events make the interrupt pending, and update its handler mode to match its trigger mode. CLEAR events make the interrupt no longer pending. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5.c | 59 ++++++++++++++++++++++++++++++++++++++++++++ hw/intc/trace-events | 1 + 2 files changed, 60 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 6ff3a79745..bc887233f5 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -946,6 +946,28 @@ static void irs_ist_baser_write(GICv5 *s, GICv5Domain = domain, uint64_t value) } } =20 +static void spi_sample(GICv5SPIState *spi) +{ + /* + * Sample the state of the SPI input line; this generates + * SET_EDGE, SET_LEVEL or CLEAR events which update the SPI's + * pending state and handling mode per R_HHKMN. The logic is the + * same for "the input line changed" (R_QBXXV) and "software asked + * us to resample" (R_DMTFM). + */ + if (spi->level) { + /* + * SET_LEVEL or SET_EDGE: interrupt becomes pending, and the + * handling mode is updated to match the trigger mode. + */ + spi->pending =3D true; + spi->hm =3D spi->tm =3D=3D GICV5_TRIGGER_EDGE ? GICV5_EDGE : GICV5= _LEVEL; + } else if (spi->tm =3D=3D GICV5_TRIGGER_LEVEL) { + /* falling edges only trigger a CLEAR event for level-triggered */ + spi->pending =3D false; + } +} + static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset, uint64_t *data, MemTxAttrs attrs) { @@ -1096,7 +1118,24 @@ static bool config_writel(GICv5 *s, GICv5Domain doma= in, hwaddr offset, { GICv5SPIState *spi =3D spi_for_selr(cs, domain); if (spi) { + GICv5TriggerMode old_tm =3D spi->tm; spi->tm =3D FIELD_EX32(data, IRS_SPI_CFGR, TM); + if (spi->tm !=3D old_tm) { + /* + * R_KBPXL: updates to SPI trigger mode can generate CLEAR= or + * SET_LEVEL events. This is not the same logic as spi_sam= ple(). + */ + if (spi->tm =3D=3D GICV5_TRIGGER_LEVEL) { + if (spi->level) { + spi->pending =3D true; + spi->hm =3D GICV5_LEVEL; + } else { + spi->pending =3D false; + } + } else if (spi->level) { + spi->pending =3D false; + } + } } return true; } @@ -1109,6 +1148,17 @@ static bool config_writel(GICv5 *s, GICv5Domain doma= in, hwaddr offset, } } return true; + case A_IRS_SPI_RESAMPLER: + { + uint32_t id =3D FIELD_EX32(data, IRS_SPI_RESAMPLER, SPI_ID); + GICv5SPIState *spi =3D gicv5_spi_state(cs, id, domain); + + if (spi) { + spi_sample(spi); + } + trace_gicv5_spi_state(id, spi->level, spi->pending, spi->active); + return true; + } } =20 return false; @@ -1259,8 +1309,17 @@ static void gicv5_set_spi(void *opaque, int irq, int= level) /* These irqs are all SPIs; the INTID is irq + s->spi_base */ GICv5Common *cs =3D ARM_GICV5_COMMON(opaque); uint32_t spi_id =3D irq + cs->spi_base; + GICv5SPIState *spi =3D gicv5_raw_spi_state(cs, spi_id); + + if (!spi || spi->level =3D=3D level) { + return; + } =20 trace_gicv5_spi(spi_id, level); + + spi->level =3D level; + spi_sample(spi); + trace_gicv5_spi_state(spi_id, spi->level, spi->pending, spi->active); } =20 static void gicv5_reset_hold(Object *obj, ResetType type) diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 409935e15a..4c55af2780 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -241,6 +241,7 @@ gicv5_set_pending(const char *domain, const char *type,= bool virtual, uint32_t i gicv5_set_handling(const char *domain, const char *type, bool virtual, uin= t32_t id, int handling) "GICv5 IRS SetHandling %s %s virtual:%d ID %u handl= ing %d" gicv5_set_target(const char *domain, const char *type, bool virtual, uint3= 2_t id, uint32_t iaffid, int irm) "GICv5 IRS SetTarget %s %s virtual:%d ID = %u IAFFID %u routingmode %d" gicv5_request_config(const char *domain, const char *type, bool virtual, u= int32_t id, uint64_t icsr) "GICv5 IRS RequestConfig %s %s virtual:%d ID %u = ICSR 0x%" PRIx64 +gicv5_spi_state(uint32_t spi_id, bool level, bool pending, bool active) "G= ICv5 IRS SPI ID %u now level %d pending %d active %d" =20 # arm_gicv5_common.c gicv5_common_realize(uint32_t irsid, uint32_t num_cpus, uint32_t spi_base,= uint32_t spi_irs_range, uint32_t spi_range) "GICv5 IRS realized: IRS ID %u= , %u CPUs, SPI base %u, SPI IRS range %u, SPI range %u" --=20 2.43.0