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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610247; x=1775215047; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8AGUas74GiCe8W5uPOS1WFnAMWVY4ggcPmMUN6MKkgw=; b=nYZ9uouyMvABc3pPucNaB78MYSGpP6SwZAVJDO73E5C3CNiazekLX+F++116eyHm0Q wXtQzsTFcTFhEm15yCXJFFdCv6h4lYjN7sYIkgDRtQQK6RizipEQqEDRWz1e50rke89c 8fNAhW4KtdkA8UnXFKja8kg9rdOOs6bw13aoMEdatHv9/VOQDjr9Q5kqR8u5Ug4tELlO IawMPgm4snmFSPaKtnfrzyLqcXWezQsneJ7TNPSzjM3Ky5n4RKpGRg8Q/CLOYRHmJCW+ plQftz2SJLVWAcj2g6YrkKEq5rcG2VjbJk4ja9axk8YQ+irjMQsHIKB6eIUP5Ea2i7zh GiaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610247; x=1775215047; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=8AGUas74GiCe8W5uPOS1WFnAMWVY4ggcPmMUN6MKkgw=; b=F/DLSCsFFHD+O8eDh2kN0sHposhujaK+GWBPCpUB9wCgmdgKVBmmPaaTzNV805l8+0 +wPHoHwyIK9WMHphn+RyUokb3x67joLxoOsnb+MvrlF1WJFPlxLdNoCGIEmOw8zIqpFZ Mr67bcknSR4FyeCv8Q9Rd4VcpIt/lFuqFvTTfB86+vmEJNTrW7+w622DBjA1PFmfABKz gc1/53YJs+Ci+cAoWmZ9fCfVBgkIrqrX3v5CB0Ag6QvrFDcemLmbtGvUFjr2OAwmFRZu MgK0eqvDBmuxN71o4swmHIe9VSTwLFSSk7njGEMHaYM/zbeNZY+gUW0Q0htSryqTPl1Z wlRg== X-Forwarded-Encrypted: i=1; AJvYcCXBdoesLpqMCiZyI3+4guuHK+nKpCxKvrxg3R2UENel1lVCL9eDLF9qWrpeHmZIHaCE9ZEXg48e5fKs@nongnu.org X-Gm-Message-State: AOJu0YwlagyIg0YE2P68ph2Fv8WnY68d+MJvwtgtS0dzkq05gyRjEuzo JbRcNAN9vvT/WRIkbRvs+/fkxtQ/2d9WDcZisjlJNqg2dmEYRqi52qGVsXBXwevshJE= X-Gm-Gg: ATEYQzyL3bbSlN3vIWAogttD0CG0eUMUjAYjweROSAXS6IaEps46nE+hhNIvJYiJi93 /IhNhzugtMxcku1ux5ra099QGUyKH2sRbmIHLVMfvJHVqSJ1t5M4tP3Tj7Di59VgKzHCm/mAu0T Fw0P/V1MMP5IiYcsRGmdwz8Ybz3zaUsnyE9R+S9mUGBtCTL/thk/zRu2FSZmWGSqoaFUVdB9q8d D7ZTCV3GIluZ2sk7ECunjWORnxA335UMW4xQ/2yO2FwM+DHvlnhe5pCyJPiamYFzCbxcoKmxWEJ 2WmJxYh6TMUvlr0hqkSDuOjfKbiOlziqwXbEnbIZF/1gLymhzIwVcoXmJ1PCmmJ7Jsx8xI9fMWR BJOWgww3GLWjcalZlLfDowZmCl6oagLj4UeZd+w2crY9YnR8F6OYKQEAE+UPndRiVhaphawpoM2 aHNCgb7YH5NMvi0UMC9f1w3QYHSvgAtq+WEkh7NgMaFDnrWltuQg1+H6OQzge6JO16rNS9bxIyv am5w5veBhT82wZlmAowbJrWD6/aP6c= X-Received: by 2002:a05:6000:2282:b0:43b:4ef0:e17 with SMTP id ffacd0b85a97d-43b9e98139bmr3611466f8f.7.1774610246850; Fri, 27 Mar 2026 04:17:26 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 26/65] target/arm: GICv5 cpuif: Implement GIC CDRCFG and ICC_ICSR_EL1 Date: Fri, 27 Mar 2026 11:16:21 +0000 Message-ID: <20260327111700.795099-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610619565158500 Content-Type: text/plain; charset="utf-8" Implement the GIC CDRCFG system instruction, which asks the IRS for the configuration of an interrupt, and the system register ICC_ICSR_EL1 which is where the answer is placed for the guest to read it. We mark ICC_ICSR_EL1 as ARM_CP_NO_RAW, because we do not want to have this migrated as part of the generic "system register" migration arrays. Instead we will do migration via a GICv5 cpuif vmstate section. This is necessary because some of the cpuif registers are banked by interrupt domain and so need special handling to migrate the data in all the banks; it's also how we handle the gicv3 cpuif registers. (We expect that KVM also will expose the cpuif registers via GIC-specific ioctls rather than as generic sysregs.) We'll mark all the GICv5 sysregs as NO_RAW. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- target/arm/cpu.h | 5 +++++ target/arm/tcg/gicv5-cpuif.c | 27 +++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 16de0ebfa8..1fdfd91ba4 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -597,6 +597,11 @@ typedef struct CPUArchState { uint64_t vmecid_a_el2; } cp15; =20 + struct { + /* GICv5 CPU interface data */ + uint64_t icc_icsr_el1; + } gicv5_cpuif; + struct { /* M profile has up to 4 stack pointers: * a Main Stack Pointer and a Process Stack Pointer for each diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 0c4349f8a7..8cf09791c1 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -35,6 +35,9 @@ FIELD(GIC_CDHM, ID, 0, 24) FIELD(GIC_CDHM, TYPE, 29, 3) FIELD(GIC_CDHM, HM, 32, 1) =20 +FIELD(GIC_CDRCFG, ID, 0, 24) +FIELD(GIC_CDRCFG, TYPE, 29, 3) + static GICv5Common *gicv5_get_gic(CPUARMState *env) { return env->gicv5state; @@ -134,6 +137,19 @@ static void gic_cdpend_write(CPUARMState *env, const A= RMCPRegInfo *ri, gicv5_set_pending(gic, id, pending, domain, type, virtual); } =20 +static void gic_cdrcfg_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + GICv5Common *gic =3D gicv5_get_gic(env); + GICv5IntType type =3D FIELD_EX64(value, GIC_CDRCFG, TYPE); + uint32_t id =3D FIELD_EX64(value, GIC_CDRCFG, ID); + bool virtual =3D false; + GICv5Domain domain =3D gicv5_current_phys_domain(env); + + env->gicv5_cpuif.icc_icsr_el1 =3D + gicv5_request_config(gic, id, domain, type, virtual); +} + static void gic_cdhm_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -194,11 +210,22 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, .writefn =3D gic_cdpend_write, }, + { .name =3D "GIC_CDRCFG", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 5, + .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .writefn =3D gic_cdrcfg_write, + }, { .name =3D "GIC_CDHM", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 2, .opc2 =3D 1, .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, .writefn =3D gic_cdhm_write, }, + { .name =3D "ICC_ICSR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 10, .opc2 =3D 4, + .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, + .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.icc_icsr_el1), + .resetvalue =3D 0, + }, }; =20 void define_gicv5_cpuif_regs(ARMCPU *cpu) --=20 2.43.0