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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610245; x=1775215045; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZYcKb44qcAOTmabDFzYmilElxXC21N5X3c+i6UPowFQ=; b=cFUR6h7yibghqmmfZ2pV8rWCQD+uH1o+kEyrdZxu3L83JnvFJwsT9BwEnsrTjLiBUR DMosyWvux2f/IhphisJMzTvU3BNYEhLtU5HJFCTjOLks4eG/PnOYbS/bb1gIlGU90Z3x MxZyT4TyEH7X3KF2mYCSMO5X3vZoc8Auz4Ps15F09l313XmtQidbA8brHOh+AiGtdjI1 527WhV5demsxpHanP3p0QdGFhhosqa3VlmaVnjEQ2J28z1WbMiyXYVo2NdJKvKlygAjh MmolrT4JnVaBRsWpHvZM2d3P0FIChhtCihrEc3eaGsLjLE30wgR1vrPIotyuxoWfvICo rgug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610245; x=1775215045; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=ZYcKb44qcAOTmabDFzYmilElxXC21N5X3c+i6UPowFQ=; b=hbXgx70R4a8giKC0uzbpzKbbIPK0a6SgaP3xw0LwM8+0VKWUVrL4OrzXNAu3Khi9qf PTytbk4+XwBWoEhlD6L0KecrEzkA9Ow7hlRs3Ymj4r79XFdHezooi1cdm196QCDg+wtl zjljjaN1We2SHAsskXQ/RL4CWVCRKsAKylA4CORFBTvmCOVs9fSJBWOelYCxBqOY+7gw Oyv1LV/iK1SqHGiVI/DsMonDbsws9uJKM6sSLnNeH7GDVFiQ0vLQnGecSQRr355xeyaH EBzJca31ob/lVwtdYA7404n3k/7QCe1iRg/Gvx4yt0/OE8NJZXK8hrECrDTRH1TEK0RV KTbQ== X-Forwarded-Encrypted: i=1; AJvYcCVm+ynUnxBfcwjAtUXRrU431oFqX3YgH53LX0Xt6W3nFKehQGvlNjZvp52QDr1viEMsZvgcHpivDeRB@nongnu.org X-Gm-Message-State: AOJu0YwReedtTmb00xktd6iyQvCUmWEMmMzdVJH2egAMBYwoX/3/DmZw mEvscBgGJrS98nm5pUG2gxMNfNl45tSzxSzETUl+TtlmPednOBgDWrXX2ff6DyjBrhs= X-Gm-Gg: ATEYQzxRcLdgV2brasLkgzjZ1A02vulcTOerD8i/ipSgcoWfMTKnLzXpzbN+X2u2E1I VOocluSSACAqAI5p2OhoOP+xCCWyaCEo0NlVWl/Hqms4Ul3jz/zdJ0eCQxCJaxExcDa5S/VcBCj IMMOegoSPrmBCiFd1GpS+BX11ayhI/jFMIf8DWiIPG38bKxUjUh4dd2k1nolerL7LCW3KuVy8Uc ngf97mAkfypHlMtzbHPtTNMePlu2UQmpojOqEFtse3NaiwNdgJgE1OyDcqzGAwh3SWBqMim/6zC /wYVVOeWKFDAje4XZZTPeJhOSZtbUtojy1PGr5sUZnaKi+wKrmIAYbzz5SGPfvPZ+tnUY0DiK1f 5/QsNS2odwM+qlK/4bwfnardSAL2n2Qvjm7H7Eq9Gp4jfTUuc2msFqgzS7fNs/JD/vUPeZo/bVl Civ8KOZqEdMXulAvkdO87C8IaDdJdC+Iug54ZYC3nzkDK9f4vXk3w/AExksMLp79+eBtOLV1/0h 3wn+Vfdp/1T9feeOC9W63AslUt+iPE= X-Received: by 2002:a05:6000:1ac9:b0:43b:4e01:4aa9 with SMTP id ffacd0b85a97d-43b9e9d5b91mr3339888f8f.10.1774610244950; Fri, 27 Mar 2026 04:17:24 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 24/65] hw/intc/arm_gicv5: Make gicv5_set_* update SPI state Date: Fri, 27 Mar 2026 11:16:19 +0000 Message-ID: <20260327111700.795099-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610762017154100 Content-Type: text/plain; charset="utf-8" The GIC CD* insns that update interrupt state also work for SPIs. Instead of ignoring the GICV5_SPI type in gicv5_set_priority() and friends, update the state in our SPI state array. Signed-off-by: Peter Maydell --- hw/intc/arm_gicv5.c | 64 ++++++++++++++++++++++++++++++ include/hw/intc/arm_gicv5_common.h | 40 +++++++++++++++++++ 2 files changed, 104 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index d1eb96fce0..9ca1826253 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -490,6 +490,19 @@ void gicv5_set_priority(GICv5Common *cs, uint32_t id, = uint8_t priority, put_l2_iste(cs, cfg, &h); break; } + case GICV5_SPI: + { + GICv5SPIState *spi =3D gicv5_spi_state(cs, id, domain); + + if (!spi) { + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_priority: tried to s= et " + "priority of unreachable SPI %d\n", id); + return; + } + + spi->priority =3D priority; + break; + } default: qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_priority: tried to set " "priority of bad interrupt type %d\n", type); @@ -524,6 +537,19 @@ void gicv5_set_enabled(GICv5Common *cs, uint32_t id, b= ool enabled, put_l2_iste(cs, cfg, &h); break; } + case GICV5_SPI: + { + GICv5SPIState *spi =3D gicv5_spi_state(cs, id, domain); + + if (!spi) { + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_enabled: tried to se= t " + "enable state of unreachable SPI %d\n", id); + return; + } + + spi->enabled =3D true; + break; + } default: qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_enabled: tried to set " "enable state of bad interrupt type %d\n", type); @@ -558,6 +584,19 @@ void gicv5_set_pending(GICv5Common *cs, uint32_t id, b= ool pending, put_l2_iste(cs, cfg, &h); break; } + case GICV5_SPI: + { + GICv5SPIState *spi =3D gicv5_spi_state(cs, id, domain); + + if (!spi) { + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_pending: tried to se= t " + "pending state of unreachable SPI %d\n", id); + return; + } + + spi->pending =3D true; + break; + } default: qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_pending: tried to set " "pending state of bad interrupt type %d\n", type); @@ -593,6 +632,18 @@ void gicv5_set_handling(GICv5Common *cs, uint32_t id, put_l2_iste(cs, cfg, &h); break; } + case GICV5_SPI: + { + GICv5SPIState *spi =3D gicv5_spi_state(cs, id, domain); + + if (!spi) { + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_handling: tried to s= et " + "priority of unreachable SPI %d\n", id); + } + + spi->hm =3D handling; + break; + } default: qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_handling: tried to set " "handling mode of bad interrupt type %d\n", type); @@ -642,6 +693,19 @@ void gicv5_set_target(GICv5Common *cs, uint32_t id, ui= nt32_t iaffid, put_l2_iste(cs, cfg, &h); break; } + case GICV5_SPI: + { + GICv5SPIState *spi =3D gicv5_spi_state(cs, id, domain); + + if (!spi) { + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_target: tried to set= " + "target of unreachable SPI %d\n", id); + return; + } + + spi->iaffid =3D iaffid; + break; + } default: qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_target: tried to set " "target of bad interrupt type %d\n", type); diff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5= _common.h index d3f4999321..a81c941765 100644 --- a/include/hw/intc/arm_gicv5_common.h +++ b/include/hw/intc/arm_gicv5_common.h @@ -189,4 +189,44 @@ static inline bool gicv5_domain_implemented(GICv5Commo= n *cs, GICv5Domain domain) */ const char *gicv5_class_name(void); =20 +/** + * gicv5_raw_spi_state + * @cs: GIC object + * @id: INTID of SPI to look up + * + * Return pointer to the GICv5SPIState for this SPI, or NULL if the + * interrupt ID is out of range. This does not do a check that the SPI + * is assigned to the right domain: generally you should call it via + * some other wrapper that performs an appropriate further check. + */ +static inline GICv5SPIState *gicv5_raw_spi_state(GICv5Common *cs, uint32_t= id) +{ + if (id < cs->spi_base || id >=3D cs->spi_base + cs->spi_irs_range) { + return NULL; + } + + return cs->spi + (id - cs->spi_base); +} + +/** + * gicv5_spi_state: + * @cs: GIC object + * @id: INTID of SPI to look up + * @domain: domain to check + * + * Return pointer to the GICv5SPIState for this SPI, or NULL if the + * interrupt is unreachable (which can be because the INTID is out of + * range, or because the SPI is configured for a different domain). + */ +static inline GICv5SPIState *gicv5_spi_state(GICv5Common *cs, uint32_t id, + GICv5Domain domain) +{ + GICv5SPIState *spi =3D gicv5_raw_spi_state(cs, id); + + if (!spi || spi->domain !=3D domain) { + return NULL; + } + return spi; +} + #endif --=20 2.43.0