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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610243; x=1775215043; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mSHOw0ePxFClS8VZTB3TfGftr7NcOYKm+ePZhUgk940=; b=TGnF7eNsFnoe819AkskCup9UCZ+xJ0B19aHNyQj+KzhHxY5mJjErZY71/ybs461ipv 7ibyVtRlY/yoTarPcmbP7zXnxxeLSLkllt0XNTG92wQo+bbwW91dIC2wfLCTR2w9/xAl EJuMB8TXP+EypuKdDzKg61PUFPIL4F5eFsOWFZgCudgdpjwyJyl7aXIEwDueN5caROjn ZNQeEsgbxWUqynqg1O76OGuOLewsjk+OiMzmIcxIq3zfOWWXLw0MgKn3oB9J8piEdEhn PKSyN5ZWNkpg4obVMfXBlcPKr9+yGlGEQsNofQA8DB/3qAiFBi3mMngktSth094jWTUD Q39w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610243; x=1775215043; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=mSHOw0ePxFClS8VZTB3TfGftr7NcOYKm+ePZhUgk940=; b=kWaohpBB/0GlktXCkp3JNXKsBCLoMKp4zOjeyFLsm7JkYPuZRamIoEp5ZwAaZM7aQz ea4cef8DUORITjRE7TgxUvvXAlHHAIGCZRZNgifIhbtN3EQyjHqbxEvJlTXyk1N1/34C +6thBOtgXM2vM8G9qDduevGvaBTKRVXua3K/JewYvOI6VsTfgUZfmfklTKdxB/mPCHma csABsaUcZaNVRuUnggTLU+vu2tIUpA1v7PbaMCJyznFkHEA+mXjt69Dj4ynh28N2DJLr 5rRWOLOQfrc2OU7zvYAUZPLP+s67bfiSj9sDG4yEJZKQ1+AL5VLQL7WBIU7pKRRpcPNh P7WA== X-Forwarded-Encrypted: i=1; AJvYcCXEfDacbvO7ezh5if2svKNVeGULZZeTf80zYGMc5aHJXNGfSBztwCq3lNkae1Imn09bv8NwU2d6xBXT@nongnu.org X-Gm-Message-State: AOJu0YzdWv/Eq8jCytX4+leQtR7nLerMJlXqfSktITgi8zCItP8Tn1kj mbai1wxZ58+XU8thhKgjtTuQ9XpSbe3rf7DT2cJLZKpGTVEGlOOishqohgFJucCL9R0= X-Gm-Gg: ATEYQzyhpceUPs8/Pd3U/CK4PzUDF21G94Zbr53bEiilWpzTn+riCwXeAHT/7o3z+0p 88MyPnU5HSUn2HCss5peXLfivMO7qu4kREPM6drfbFkLuOkxUyHVWGd84wRFiBjz3f/rm2eekQW NPIKuv9cq8l4Y39RH9vouJQglkSCJj2bWUIBWhjamxvfVk2y2FcSXrzyqFFxFyuxObfMUg1vP4b 76j6Dj4Q4oTiZ/dw3U6nK+JESR48AtuNhed2gqGlKi8BP7cKzfsz57m0eCyQklUmCUlruOCxGQA 2xf0v6dweAsZsLP8rZF1rZwIRCRurWmdkwj4LG/5olix4Amc6M5xfi/FH6/VRwb0Xcf0vRL6ZNj eWsUTgA9KrqfgXSvgv1lL+0kcmQ78XFb2chfbjcYqhWoUVyRMJr4+DXXbrLk6OF4X7d5fQsNYTF YSNpY4RITR3HJRC6aEvpIlnNmHVuoicPn6WvLufazHjUXNx7v6lxKzQoZHwlVmk/57jOGPQt/dI oCrVyfrwoC/oEYA5Ek9ppn8m1xovL0= X-Received: by 2002:a05:6000:250d:b0:439:bf55:f5ec with SMTP id ffacd0b85a97d-43b9ea77b12mr3260198f8f.50.1774610242563; Fri, 27 Mar 2026 04:17:22 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 22/65] target/arm: GICv5 cpuif: Implement GIC CD* insns for setting config Date: Fri, 27 Mar 2026 11:16:17 +0000 Message-ID: <20260327111700.795099-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610780389158500 Content-Type: text/plain; charset="utf-8" Implement the GIC CDDIS, GIC CDEN, GIC CDAFF, GIC CDPEND and GIC CDHM system instructions. These are all simple wrappers around the equivalent gicv5_set_* functions, like GIC CDPRI. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- target/arm/tcg/gicv5-cpuif.c | 108 +++++++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 0c2bba5ce9..0c4349f8a7 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -16,6 +16,25 @@ FIELD(GIC_CDPRI, ID, 0, 24) FIELD(GIC_CDPRI, TYPE, 29, 3) FIELD(GIC_CDPRI, PRIORITY, 35, 5) =20 +FIELD(GIC_CDDIS, ID, 0, 24) +FIELD(GIC_CDDIS, TYPE, 29, 3) + +FIELD(GIC_CDEN, ID, 0, 24) +FIELD(GIC_CDEN, TYPE, 29, 3) + +FIELD(GIC_CDAFF, ID, 0, 24) +FIELD(GIC_CDAFF, IRM, 28, 1) +FIELD(GIC_CDAFF, TYPE, 29, 3) +FIELD(GIC_CDAFF, IAFFID, 32, 16) + +FIELD(GIC_CDPEND, ID, 0, 24) +FIELD(GIC_CDPEND, TYPE, 29, 3) +FIELD(GIC_CDPEND, PENDING, 32, 1) + +FIELD(GIC_CDHM, ID, 0, 24) +FIELD(GIC_CDHM, TYPE, 29, 3) +FIELD(GIC_CDHM, HM, 32, 1) + static GICv5Common *gicv5_get_gic(CPUARMState *env) { return env->gicv5state; @@ -51,6 +70,30 @@ static GICv5Domain gicv5_current_phys_domain(CPUARMState= *env) return gicv5_logical_domain(env); } =20 +static void gic_cddis_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + GICv5Common *gic =3D gicv5_get_gic(env); + GICv5IntType type =3D FIELD_EX64(value, GIC_CDDIS, TYPE); + uint32_t id =3D FIELD_EX64(value, GIC_CDDIS, ID); + bool virtual =3D false; + GICv5Domain domain =3D gicv5_current_phys_domain(env); + + gicv5_set_enabled(gic, id, false, domain, type, virtual); +} + +static void gic_cden_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + GICv5Common *gic =3D gicv5_get_gic(env); + GICv5IntType type =3D FIELD_EX64(value, GIC_CDEN, TYPE); + uint32_t id =3D FIELD_EX64(value, GIC_CDEN, ID); + bool virtual =3D false; + GICv5Domain domain =3D gicv5_current_phys_domain(env); + + gicv5_set_enabled(gic, id, true, domain, type, virtual); +} + static void gic_cdpri_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -64,6 +107,46 @@ static void gic_cdpri_write(CPUARMState *env, const ARM= CPRegInfo *ri, gicv5_set_priority(gic, id, priority, domain, type, virtual); } =20 +static void gic_cdaff_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + GICv5Common *gic =3D gicv5_get_gic(env); + uint32_t iaffid =3D FIELD_EX64(value, GIC_CDAFF, IAFFID); + GICv5RoutingMode irm =3D FIELD_EX64(value, GIC_CDAFF, IRM); + GICv5IntType type =3D FIELD_EX64(value, GIC_CDAFF, TYPE); + uint32_t id =3D FIELD_EX64(value, GIC_CDAFF, ID); + bool virtual =3D false; + GICv5Domain domain =3D gicv5_current_phys_domain(env); + + gicv5_set_target(gic, id, iaffid, irm, domain, type, virtual); +} + +static void gic_cdpend_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + GICv5Common *gic =3D gicv5_get_gic(env); + bool pending =3D FIELD_EX64(value, GIC_CDPEND, PENDING); + GICv5IntType type =3D FIELD_EX64(value, GIC_CDPEND, TYPE); + uint32_t id =3D FIELD_EX64(value, GIC_CDPEND, ID); + bool virtual =3D false; + GICv5Domain domain =3D gicv5_current_phys_domain(env); + + gicv5_set_pending(gic, id, pending, domain, type, virtual); +} + +static void gic_cdhm_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + GICv5Common *gic =3D gicv5_get_gic(env); + GICv5HandlingMode hm =3D FIELD_EX64(value, GIC_CDHM, HM); + GICv5IntType type =3D FIELD_EX64(value, GIC_CDAFF, TYPE); + uint32_t id =3D FIELD_EX64(value, GIC_CDAFF, ID); + bool virtual =3D false; + GICv5Domain domain =3D gicv5_current_phys_domain(env); + + gicv5_set_handling(gic, id, hm, domain, type, virtual); +} + static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { /* * Barrier: wait until the effects of a cpuif system register @@ -86,11 +169,36 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 0, .opc2 =3D 1, .access =3D PL1_W, .type =3D ARM_CP_NOP, }, + { .name =3D "GIC_CDDIS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .writefn =3D gic_cddis_write, + }, + { .name =3D "GIC_CDEN", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .writefn =3D gic_cden_write, + }, { .name =3D "GIC_CDPRI", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 2, .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, .writefn =3D gic_cdpri_write, }, + { .name =3D "GIC_CDAFF", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 3, + .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .writefn =3D gic_cdaff_write, + }, + { .name =3D "GIC_CDPEND", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 4, + .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .writefn =3D gic_cdpend_write, + }, + { .name =3D "GIC_CDHM", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .writefn =3D gic_cdhm_write, + }, }; =20 void define_gicv5_cpuif_regs(ARMCPU *cpu) --=20 2.43.0