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Note that neither BASER nor CFGR can be written when VALID =3D=3D 1, except to clear the VALID bit. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5.c | 74 ++++++++++++++++++++++++++++++ hw/intc/arm_gicv5_common.c | 4 ++ include/hw/intc/arm_gicv5_common.h | 3 ++ 3 files changed, 81 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 250925f004..cbb35c0270 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -265,6 +265,24 @@ REG64(IRS_SWERR_SYNDROMER0, 0x3c8) REG64(IRS_SWERR_SYNDROMER1, 0x3d0) FIELD(IRS_SWERR_SYNDROMER2, ADDR, 3, 53) =20 +static void irs_ist_baser_write(GICv5 *s, GICv5Domain domain, uint64_t val= ue) +{ + GICv5Common *cs =3D ARM_GICV5_COMMON(s); + + if (FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID)) { + /* If VALID is set, ADDR is RO and we can only update VALID */ + bool valid =3D FIELD_EX64(value, IRS_IST_BASER, VALID); + if (valid) { + /* Ignore 1->1 transition */ + return; + } + cs->irs_ist_baser[domain] =3D FIELD_DP64(cs->irs_ist_baser[domain], + IRS_IST_BASER, VALID, valid= ); + return; + } + cs->irs_ist_baser[domain] =3D value; +} + static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset, uint64_t *data, MemTxAttrs attrs) { @@ -325,6 +343,26 @@ static bool config_readl(GICv5 *s, GICv5Domain domain,= hwaddr offset, case A_IRS_AIDR: *data =3D cs->irs_aidr; return true; + + case A_IRS_IST_BASER: + *data =3D extract64(cs->irs_ist_baser[domain], 0, 32); + return true; + + case A_IRS_IST_BASER + 4: + *data =3D extract64(cs->irs_ist_baser[domain], 32, 32); + return true; + + case A_IRS_IST_STATUSR: + /* + * For QEMU writes to IRS_IST_BASER and IRS_MAP_L2_ISTR take effect + * instantaneously, and the guest can never see the IDLE bit as 0. + */ + *data =3D R_IRS_IST_STATUSR_IDLE_MASK; + return true; + + case A_IRS_IST_CFGR: + *data =3D cs->irs_ist_cfgr[domain]; + return true; } =20 return false; @@ -333,18 +371,54 @@ static bool config_readl(GICv5 *s, GICv5Domain domain= , hwaddr offset, static bool config_writel(GICv5 *s, GICv5Domain domain, hwaddr offset, uint64_t data, MemTxAttrs attrs) { + GICv5Common *cs =3D ARM_GICV5_COMMON(s); + + switch (offset) { + case A_IRS_IST_BASER: + irs_ist_baser_write(s, domain, + deposit64(cs->irs_ist_baser[domain], 0, 32, da= ta)); + return true; + case A_IRS_IST_BASER + 4: + irs_ist_baser_write(s, domain, + deposit64(cs->irs_ist_baser[domain], 32, 32, d= ata)); + return true; + case A_IRS_IST_CFGR: + if (FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID)) { + qemu_log_mask(LOG_GUEST_ERROR, + "guest tried to write IRS_IST_CFGR for %s config= frame " + "while IST_BASER.VALID set\n", domain_name[domai= n]); + } else { + cs->irs_ist_cfgr[domain] =3D data; + } + return true; + } + return false; } =20 static bool config_readll(GICv5 *s, GICv5Domain domain, hwaddr offset, uint64_t *data, MemTxAttrs attrs) { + GICv5Common *cs =3D ARM_GICV5_COMMON(s); + + switch (offset) { + case A_IRS_IST_BASER: + *data =3D cs->irs_ist_baser[domain]; + return true; + } + return false; } =20 static bool config_writell(GICv5 *s, GICv5Domain domain, hwaddr offset, uint64_t data, MemTxAttrs attrs) { + switch (offset) { + case A_IRS_IST_BASER: + irs_ist_baser_write(s, domain, data); + return true; + } + return false; } =20 diff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c index 54d75db014..44909d1b05 100644 --- a/hw/intc/arm_gicv5_common.c +++ b/hw/intc/arm_gicv5_common.c @@ -62,6 +62,10 @@ void gicv5_common_init_irqs_and_mmio(GICv5Common *cs, =20 static void gicv5_common_reset_hold(Object *obj, ResetType type) { + GICv5Common *cs =3D ARM_GICV5_COMMON(obj); + + memset(cs->irs_ist_baser, 0, sizeof(cs->irs_ist_baser)); + memset(cs->irs_ist_cfgr, 0, sizeof(cs->irs_ist_cfgr)); } =20 static void gicv5_common_init(Object *obj) diff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5= _common.h index 88e1b4d73d..9bfafcebfc 100644 --- a/include/hw/intc/arm_gicv5_common.h +++ b/include/hw/intc/arm_gicv5_common.h @@ -62,6 +62,9 @@ struct GICv5Common { =20 MemoryRegion iomem[NUM_GICV5_DOMAINS]; =20 + uint64_t irs_ist_baser[NUM_GICV5_DOMAINS]; + uint32_t irs_ist_cfgr[NUM_GICV5_DOMAINS]; + /* Bits here are set for each physical interrupt domain implemented */ uint8_t implemented_domains; =20 --=20 2.43.0