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(Notably, it stores per-interrupt configuration information like the interrupt priority and its active and pending state in an in-memory data structure.) Add a link property so that the board or SoC can wire up a MemoryRegion that we will do DMA to. We name this property "sysmem" to match the GICv3's equivalent property. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5_common.c | 8 ++++++++ include/hw/intc/arm_gicv5_common.h | 4 ++++ 2 files changed, 12 insertions(+) diff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c index b58913b970..29cc96917e 100644 --- a/hw/intc/arm_gicv5_common.c +++ b/hw/intc/arm_gicv5_common.c @@ -122,6 +122,12 @@ static void gicv5_common_realize(DeviceState *dev, Err= or **errp) cs->spi_base, cs->spi_irs_range, cs->spi_range); return; } + if (!cs->dma) { + error_setg(errp, "sysmem link property not set"); + return; + } + + address_space_init(&cs->dma_as, cs->dma, "gicv5-sysmem"); =20 trace_gicv5_common_realize(cs->irsid, cs->num_cpus, cs->spi_base, cs->spi_irs_range, cs->spi_ra= nge); @@ -137,6 +143,8 @@ static const Property arm_gicv5_common_properties[] =3D= { DEFINE_PROP_UINT32("spi-base", GICv5Common, spi_base, 0), DEFINE_PROP_UINT32("spi-irs-range", GICv5Common, spi_irs_range, GICV5_SPI_IRS_RANGE_NOT_SET), + DEFINE_PROP_LINK("sysmem", GICv5Common, dma, TYPE_MEMORY_REGION, + MemoryRegion *), }; =20 static void gicv5_common_class_init(ObjectClass *oc, const void *data) diff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5= _common.h index 906870e49f..900af53b0f 100644 --- a/include/hw/intc/arm_gicv5_common.h +++ b/include/hw/intc/arm_gicv5_common.h @@ -83,6 +83,10 @@ struct GICv5Common { uint32_t num_cpu_iaffids; uint32_t *cpu_iaffids; =20 + /* MemoryRegion and AS to DMA to/from for in-memory data structures */ + MemoryRegion *dma; + AddressSpace dma_as; + uint32_t irsid; uint32_t spi_base; uint32_t spi_irs_range; --=20 2.43.0