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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610223; x=1775215023; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lkvAUvzvhzGaBsiBxwCLpDMp2ckMfQUEme3r+CbAUuk=; b=WZxrxWOYpQEu+uJ8THGO6CmppOOIoBWnMep52Ht6VL8mLFlbXJK25b4bi7b0Q9ETrR HXoY50TK343QR8CTrhgEAHOFBFsegAsl+r8ksmPEAl4oBkGxA/OJOL2OmJ8n7Ra241go wnWrY0fKvtQQdpMPLX065DUZfpJMPOxcf2ayFf2txMYNeYLVHlzXof2jN8eIv0TzCCOv 12iOPp0skx17l+zD4jGleYv3/m1lRiuc7jL/UCiAWpqC2A0sinT81GNwi+WXBKKIRCc1 c9fAZu4eB9+yyWcova5zpQQQz0bAemYpxXJ3yT1dTRWj5Bis0icNqpo6LsX+8iAih+tF u/gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610223; x=1775215023; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=lkvAUvzvhzGaBsiBxwCLpDMp2ckMfQUEme3r+CbAUuk=; b=cODAEmjMkO2QGOwcguDgaYPxrOOI76ud1bP/E4dzyO7xrQUTE9NyvbwaMMwTOMlogO mXkuzV6qEPqe6NP8o1tcUxJOQr0teZEfqK041+9pZTnzfcAAeLFZE2jVgA1HLwP3eh36 /+Dk2lDqDKm3aPzyBQKdqhFrw468elAT4AqBJpyf9H6AT59d+TUO4o8mcwRh0z2Nfbf6 tqH0ojrMcwW0JJoJ6BvyMmaX0PxNyYsH3z59WlmnOAqa91ItStb3/Yiwm8NZIxE9/ZRj LXzASWoIcgTc90OLt2pg69Kw9niY6nSaXHkRxl2WByC8n1U6DholXNva8osAi66JqB/y Q2zQ== X-Forwarded-Encrypted: i=1; AJvYcCWmVJTErIyZswpbZ1LE88c49WvbHRyo1uniEjHJxfctX6QV0Z5Zcnup6yUcKpGCLxhkyO7hZ8/Y9Kdx@nongnu.org X-Gm-Message-State: AOJu0YxoyrvdDSpDZOscjWJYj/+SHViFjNkw721p+ppW4KPst5gp5pnI Mbxq3x8857yf4BLxIh0OWi2ljT02ZQcVt2iZmjyWZyWbp1ypXf3siPSUJ1aZBuK/j2Q= X-Gm-Gg: ATEYQzwF4PFJFqtQS2Kt7ijuyTe2uDTMI+Qb0h71CPLOaHfwY3XtfPrBV9Gprj3Kl/c WO9apJ8h9OyW8EttBNdsSnLvmG+kdVz9Dfzo9RTZtoL4qlj7zOykP2Li+H/vULBJqpjj1TdBsoc vMWpPGP4n7Ns4ciUdolr3QkON/9eSKT82TWgLvw8GRyBzQBFcnj1DVx1wAYSu9BmvuWTU0o+Sv5 hliVD2/luR2BgiYb83HsXXmYSZpB3kcWHdjowyNA8VMadMqeVMu1E6M+9M8gMWRP5xqwU8FYhxE piOG9WYgpQVlCz+nG5f+X1HOIM0bVUXFjFn3X9NjeMNkr/+oPYEJ3qeUxIuMTCGngq4lHLItDWX CtZ0hZHMYFlx7nONFTjciZGLKRxm/3hTu+sW2gOMrZqJgmCfJcAa17q90aLwt+gt1ZMeKBlX0yU EmHT9wIiJGDblhI/858lMiFw134gq+ikW/AfLTJVMjQssz7IcyzXNZWbv8dlJ5XN5RArl3yjJyW DXMBUd81zOJ5PV+pvDmUUbQeXd/Dnc= X-Received: by 2002:a05:600c:524f:b0:485:4eaf:eb14 with SMTP id 5b1f17b1804b1-48727ec7894mr34098055e9.21.1774610222821; Fri, 27 Mar 2026 04:17:02 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 01/65] qom/object: Add object_resolve_and_typecheck() Date: Fri, 27 Mar 2026 11:15:56 +0000 Message-ID: <20260327111700.795099-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610367560154100 Add a new function object_resolve_and_typecheck(), whose purpose is to look up the object at a given QOM path, confirm that it is the expected type, and return it. This is similar to the existing object_resolve_path_type(), but it insists on a non-ambiguous path. We were already using this functionality internally to object.c as part of the object_resolve_link() function, so this patch implements the new function by pulling the link-property specific parts out of the more generic resolve-and-typecheck part. The motivation for this function is that we want to allow devices to provide an array of link properties; for that we will need to be able to provide the expected type of the linked object in a different way to the single-item link properties. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- include/qom/object.h | 17 +++++++++++++++++ qom/object.c | 41 +++++++++++++++++++++++------------------ 2 files changed, 40 insertions(+), 18 deletions(-) diff --git a/include/qom/object.h b/include/qom/object.h index 26df6137b9..797688f25e 100644 --- a/include/qom/object.h +++ b/include/qom/object.h @@ -1750,6 +1750,23 @@ ObjectProperty *object_class_property_add_link(Objec= tClass *oc, Object *val, Error **errp), ObjectPropertyLinkFlags flags); =20 +/** + * object_resolve_and_typecheck: + * @path: path to look up + * @name: name of property we are resolving for (used only in error messag= es) + * @target_type: QOM type we expect @path to resolve to + * @errp: error + * + * Look up the object at @path and return it. If it does not have the + * correct type @target_type, return NULL and set @errp. + * + * This is similar to object_resolve_path_type(), but it insists on a + * non-ambiguous path and it produces error messages that are + * specialised to the use case of setting a link property on an object. + */ +Object *object_resolve_and_typecheck(const char *path, const char *name, + const char *target_type, Error **errp= ); + /** * object_property_add_str: * @obj: the object to add a property to diff --git a/qom/object.c b/qom/object.c index ff8ede8a32..046b15c7f4 100644 --- a/qom/object.c +++ b/qom/object.c @@ -1895,26 +1895,12 @@ static void object_get_link_property(Object *obj, V= isitor *v, } } =20 -/* - * object_resolve_link: - * - * Lookup an object and ensure its type matches the link property type. T= his - * is similar to object_resolve_path() except type verification against the - * link property is performed. - * - * Returns: The matched object or NULL on path lookup failures. - */ -static Object *object_resolve_link(Object *obj, const char *name, - const char *path, Error **errp) +Object *object_resolve_and_typecheck(const char *path, const char *name, + const char *target_type, Error **errp) { - const char *type; - char *target_type; bool ambiguous =3D false; Object *target; =20 - /* Go from link to FOO. */ - type =3D object_property_get_type(obj, name, NULL); - target_type =3D g_strndup(&type[5], strlen(type) - 6); target =3D object_resolve_path_type(path, target_type, &ambiguous); =20 if (ambiguous) { @@ -1931,11 +1917,30 @@ static Object *object_resolve_link(Object *obj, con= st char *name, } target =3D NULL; } - g_free(target_type); - return target; } =20 +/* + * object_resolve_link: + * + * Lookup an object and ensure its type matches the link property type. T= his + * is similar to object_resolve_path() except type verification against the + * link property is performed. + * + * Returns: The matched object or NULL on path lookup failures. + */ +static Object *object_resolve_link(Object *obj, const char *name, + const char *path, Error **errp) +{ + const char *type; + g_autofree char *target_type =3D NULL; + + /* Go from link to FOO. */ + type =3D object_property_get_type(obj, name, NULL); + target_type =3D g_strndup(&type[5], strlen(type) - 6); + return object_resolve_and_typecheck(path, name, target_type, errp); +} + static void object_set_link_property(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610613; cv=none; d=zohomail.com; s=zohoarc; b=OrBQJyhyRmWjNWMttk1P9wK/f54ow7QTdmx+PRSxgWTS+rkQHacrencTQvmMHkTm1JfKnDWzJfG8qXdd0PUh0G7m6dzd7tuMdQV+uUmL1Bl1ohgHKPtTTX703O4iFtw13kzZY8TOY/9xZXyPeBsRKq34QXqNMdbRfM8a5ZvnqYI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610613; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=4YrZovDto6t0FqJWMN8zdd2dG3ackVIujvm5OvxbxII=; b=nczR3YE9wBdN69j+iIXMwaGxiPickZ5XjZ9Xk1gXYAhcrnAX5015hO/q6/EnmKlsHUafr4KO5CNDiXkt5pnUtrmrndVBgu3IYuLhPRUVykneZGVtLmXPtPPW5XJyf/CYtL1Q3jOHPYuBshNXDZ6cTb4UPmwm5g7CZdrNSWvZOEQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610613057769.0758315637876; Fri, 27 Mar 2026 04:23:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65Be-0006Md-8S; Fri, 27 Mar 2026 07:17:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65Bc-0006LI-DU for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:08 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65BZ-0007WQ-K1 for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:08 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-43b5bded412so1432102f8f.0 for ; Fri, 27 Mar 2026 04:17:05 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610224; x=1775215024; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4YrZovDto6t0FqJWMN8zdd2dG3ackVIujvm5OvxbxII=; b=w+4rZU36cxBSdOuKiyZPG6BP273oRmume/ZPlRiGRLvwJWtEHoOpOv7g/BxdierTbk bpMFji5hO6xdXFDtYrcqeMm27SyfnnSec8UfDLW87sFnmY8sBsXkGxwz7beaRU19PJVh ISbvki48l3wFm34ADYII8HyAx/W7+0GgNkhIoRbMkJoaCIwoPAenH9gloECf6zPifIii p0ouKPjz7Klcpkw9UvCQFWIY3y9QcxAKc+mRdnxIlv/G96zL0+XAmjZIXOMHcxYQ3PVX Tuvt+P5ijrFwtRNCPSEnPjCGAzgCugucE1wtSzUh4SGxpr5Q7cwwL4LKfmQ59ySZLRoo YmJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610224; x=1775215024; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=4YrZovDto6t0FqJWMN8zdd2dG3ackVIujvm5OvxbxII=; b=gFGQkQaiiwYXBOb9nVX9TH519i/OHmerECcle/HkRPqwsQNBsXcMpOCMrusGGpS/LI ddeI0YuUCMSnbzPBHgXx8kB49htmpwxz34ZiWA2TDBXASo9Hk7QD+jEy8eE5dmxAExDp /zqCwbGRPyAwQhU6ctMXuCY91tFUK+tEk1bf/I35zbS5jHp/DQKhecukyr5H8xdY06aY TZkuJ53KwNnY4cROWtFv95EfEa2uGfo/zUmbhjSbWAaLStv7oEm6hown063V9G+FcIaP LUArrJmux1DwyRmD5iNEPKerkZgMBJoc3Le/+yHnSvBIM3hlHIx/A5vPeS6PjAoWQ/O+ qW0w== X-Forwarded-Encrypted: i=1; AJvYcCUxt5kzZpDGEXwAD3ce+j1ExdCsBb1kaSuTCZpd3CbAU2Hw4H/Bd+wLjuFmoUGP5WeojO6kdqLX+SvQ@nongnu.org X-Gm-Message-State: AOJu0YzmrB6Hg3ahhUplg7+ETpOegzuJBpeGAyPYKSntWYO9a6HNNG+P KGHQO+CKZmNHQvbv5bz1ywDtem8vidbRtPnA8k1gtK6Au8mWAgDulJJhpO4dDg65oNg= X-Gm-Gg: ATEYQzwDSlcRJfbN2k3UkQR7/cCNmLV5hDy/jdrSW7ctyhMPzMABSd6XxLnVqHGD4r/ RSkGS7iwjsIgmEsYwjeUoc5S2zJq4Yt2iSoMFbjwZU0M5ki55BAPowxcP7D32h6EkUA1HzCh0Qd LCCngTndugVVK30f6ria1KQcHmgSXFUXcGnVjCLNZ8MqWo7asGM13vYVKcf+SJZ9J+W/lMeZMiK bnxqPNgQZUefU1pnjDkJyTqvN3iT27i1cmdvdZxH/1TToIFJksYSWqNgJkqO7yuL+Ij6765LG9Q Vt5aOaJB4Ehjep+OsksTLdf5XbYo0b6RRlXAHGwxeumtH/4TQMDqTS0UavO9Ib96SKjK1ORn2TF j4WTdR4yJFhy++ZYa+zjCjILYpGoP11GEQ24nvkd84d0CL7NsmltSeRgAPiecrbGvlX2Qyb4hX0 UW7L9dZoewoomUcptd5VhxnLsqUsfQHsbX1UsFvizAB726RXJJf/wx3Ur/RheYXBm+Ytf1ZAHE0 j48ETcFNvmoReYC77i6of8RDDVpNi0= X-Received: by 2002:a05:6000:22c2:b0:439:b3bb:2777 with SMTP id ffacd0b85a97d-43b9e9eb148mr3219353f8f.22.1774610223787; Fri, 27 Mar 2026 04:17:03 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 02/65] hw/core: Permit devices to define an array of link properties Date: Fri, 27 Mar 2026 11:15:57 +0000 Message-ID: <20260327111700.795099-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610613898154100 Currently we allow devices to define "link properties" with DEFINE_PROP_LINK(): these are a way to give a device a pointer to another QOM object. (Under the hood this is done by handing it the canonical QOM path for the object.) We also allow devices to define "array properties" with DEFINE_PROP_ARRAY(): these are a way to give a device a variable-length array of properties. However, there is no way to define an array of link properties. If you try to do it by passing qdev_prop_link as the arrayprop argument to DEFINE_PROP_ARRAY() you will get a crash because qdev_prop_link does not provide the .set and .get methods in its PropertyInfo struct. This patch implements a new DEFINE_PROP_LINK_ARRAY(). In a device you can use it like this: struct MyDevice { ... uint32_t num_cpus; ARMCPU **cpus; } and in your Property array: DEFINE_PROP_LINK_ARRAY("cpus", MyDevice, num_cpus, cpus, TYPE_ARM_CPU, ARMCPU *), The array property code will fill in s->num_cpus, allocate memory in s->cpus, and populate it with pointers. On the device-creation side you set the property in the same way as the existing array properties, using the new qlist_append_link() function to append to the QList: QList *cpulist =3D qlist_new(); for (int i =3D 0; i < cpus; i++) { qlist_append_link(cpulist, OBJECT(cpu[i])); } qdev_prop_set_array(mydev, "cpus", cpulist); The implementation is mostly in the provision of the .set and .get methods to the qdev_prop_link PropertyInfo struct. The code of these methods parallels the code in object_set_link_property() and object_get_link_property(). We can't completely share the code with those functions because of differences in where we get the information like the target QOM type, but I have pulled out a new function object_resolve_and_typecheck() for the shared "given a QOM path and a type, give me the object or an error" code. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/core/qdev-properties.c | 78 +++++++++++++++++++++++++++++++ include/hw/core/qdev-properties.h | 41 ++++++++++++++++ 2 files changed, 119 insertions(+) diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c index ba8461e9a4..f8181b0d91 100644 --- a/hw/core/qdev-properties.c +++ b/hw/core/qdev-properties.c @@ -669,6 +669,7 @@ static Property array_elem_prop(Object *obj, const Prop= erty *parent_prop, * being inside the device struct. */ .offset =3D (uintptr_t)elem - (uintptr_t)obj, + .link_type =3D parent_prop->link_type, }; } =20 @@ -950,6 +951,12 @@ void qdev_prop_set_array(DeviceState *dev, const char = *name, QList *values) qobject_unref(values); } =20 +void qlist_append_link(QList *qlist, Object *obj) +{ + g_autofree char *path =3D object_get_canonical_path(obj); + qlist_append_str(qlist, path); +} + static GPtrArray *global_props(void) { static GPtrArray *gp; @@ -1059,9 +1066,80 @@ static ObjectProperty *create_link_property(ObjectCl= ass *oc, const char *name, OBJ_PROP_LINK_STRONG); } =20 +/* + * The logic in these get_link() and set_link() functions is similar + * to that used for single-element link properties in the + * object_get_link_property() and object_set_link_property() functions. + * The difference is largely in how we get the expected type of the + * link: for us it is in the Property struct, and for a single link + * property it is part of the property name on the object. + */ +static void get_link(Object *obj, Visitor *v, const char *name, void *opaq= ue, + Error **errp) +{ + const Property *prop =3D opaque; + Object **targetp =3D object_field_prop_ptr(obj, prop); + g_autofree char *path =3D NULL; + + if (*targetp) { + path =3D object_get_canonical_path(*targetp); + visit_type_str(v, name, &path, errp); + } else { + path =3D g_strdup(""); + visit_type_str(v, name, &path, errp); + } +} + +static void set_link(Object *obj, Visitor *v, const char *name, void *opaq= ue, + Error **errp) +{ + const Property *prop =3D opaque; + Object **targetp =3D object_field_prop_ptr(obj, prop); + g_autofree char *path =3D NULL; + Object *new_target, *old_target =3D *targetp; + + ERRP_GUARD(); + + /* Get the path to the object we want to set the link to */ + if (!visit_type_str(v, name, &path, errp)) { + return; + } + + /* Now get the pointer to the actual object */ + if (*path) { + new_target =3D object_resolve_and_typecheck(path, prop->name, + prop->link_type, errp); + if (!new_target) { + return; + } + } else { + new_target =3D NULL; + } + + /* + * Our link properties are always OBJ_PROP_LINK_STRONG and + * have the allow_set_link_before_realize check. + */ + qdev_prop_allow_set_link_before_realize(obj, prop->name, new_target, e= rrp); + if (*errp) { + return; + } + + *targetp =3D new_target; + object_ref(new_target); + object_unref(old_target); +} + const PropertyInfo qdev_prop_link =3D { .type =3D "link", .create =3D create_link_property, + /* + * Since we have a create method, the get and set are used + * only in get_prop_array() and set_prop_array() for the case + * where we have an array of link properties. + */ + .get =3D get_link, + .set =3D set_link, }; =20 void qdev_property_add_static(DeviceState *dev, const Property *prop) diff --git a/include/hw/core/qdev-properties.h b/include/hw/core/qdev-prope= rties.h index d8745d4c65..58527e62d5 100644 --- a/include/hw/core/qdev-properties.h +++ b/include/hw/core/qdev-properties.h @@ -168,6 +168,32 @@ extern const PropertyInfo qdev_prop_link; DEFINE_PROP(_name, _state, _field, qdev_prop_link, _ptr_type, \ .link_type =3D _type) =20 +/** + * DEFINE_PROP_LINK_ARRAY: + * @_name: name of the array + * @_state: name of the device state structure type + * @_field: uint32_t field in @_state to hold the array length + * @_arrayfield: field in @_state (of type '@_arraytype *') which + * will point to the array + * @_linktype: QOM type name of the link type + * @_arraytype: C type of the array elements + * + * Define device properties for a variable-length array _name of links + * (i.e. this is the array version of DEFINE_PROP_LINK). + * + * The array is represented as a list of QStrings in the visitor interface, + * where each string is the QOM path of the object to be linked. + */ +#define DEFINE_PROP_LINK_ARRAY(_name, _state, _field, _arrayfield, \ + _linktype, _arraytype) \ + DEFINE_PROP(_name, _state, _field, qdev_prop_array, uint32_t, \ + .set_default =3D true, \ + .defval.u =3D 0, \ + .arrayinfo =3D &qdev_prop_link, \ + .arrayfieldsize =3D sizeof(_arraytype), \ + .arrayoffset =3D offsetof(_state, _arrayfield), \ + .link_type =3D _linktype) + #define DEFINE_PROP_UINT8(_n, _s, _f, _d) \ DEFINE_PROP_UNSIGNED(_n, _s, _f, _d, qdev_prop_uint8, uint8_t) #define DEFINE_PROP_UINT16(_n, _s, _f, _d) \ @@ -219,6 +245,21 @@ void qdev_prop_set_enum(DeviceState *dev, const char *= name, int value); /* Takes ownership of @values */ void qdev_prop_set_array(DeviceState *dev, const char *name, QList *values= ); =20 +/** + * qlist_append_link: Add a QOM object to a QList of link properties + * @qlist: list to append to + * @obj: object to append + * + * This is a helper function for constructing a QList to pass to + * qdev_prop_set_array() when the qdev property array is an array of + * link properties (i.e. one defined with DEFINE_PROP_LINK_ARRAY). + * + * The object is encoded into the list as a QString which is the + * canonical path of the object; this is the same encoding that + * object_set_link_property() and object_get_link_property() use. + */ +void qlist_append_link(QList *qlist, Object *obj); + void *object_field_prop_ptr(Object *obj, const Property *prop); =20 void qdev_prop_register_global(GlobalProperty *prop); --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Since the IRS is the main (and only non-optional) part of the GICv5 outside the CPU, we call it simply "GICv5", in line with how we've handled the GICv3. Since we're definitely going to need to have support for KVM VMs where we present the guest with a GICv5, we use the same split between an abstract "common" and a concrete specific-to-TCG child class that we have for the various GICv3 components. This avoids having to refactor out the base class later. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/Kconfig | 4 +++ hw/intc/arm_gicv5.c | 39 ++++++++++++++++++++++++++++++ hw/intc/arm_gicv5_common.c | 31 ++++++++++++++++++++++++ hw/intc/meson.build | 4 +++ include/hw/intc/arm_gicv5.h | 32 ++++++++++++++++++++++++ include/hw/intc/arm_gicv5_common.h | 31 ++++++++++++++++++++++++ 6 files changed, 141 insertions(+) create mode 100644 hw/intc/arm_gicv5.c create mode 100644 hw/intc/arm_gicv5_common.c create mode 100644 include/hw/intc/arm_gicv5.h create mode 100644 include/hw/intc/arm_gicv5_common.h diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index 9f456d7e43..a3241fc1eb 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -35,6 +35,10 @@ config ARM_GIC_KVM bool depends on ARM_GIC && KVM =20 +config ARM_GICV5 + bool + select MSI_NONBROKEN + config XICS bool =20 diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c new file mode 100644 index 0000000000..f9dab710d3 --- /dev/null +++ b/hw/intc/arm_gicv5.c @@ -0,0 +1,39 @@ +/* + * ARM GICv5 emulation: Interrupt Routing Service (IRS) + * + * Copyright (c) 2025 Linaro Limited + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/intc/arm_gicv5.h" + +OBJECT_DEFINE_TYPE(GICv5, gicv5, ARM_GICV5, ARM_GICV5_COMMON) + +static void gicv5_reset_hold(Object *obj, ResetType type) +{ + GICv5 *s =3D ARM_GICV5(obj); + GICv5Class *c =3D ARM_GICV5_GET_CLASS(s); + + if (c->parent_phases.hold) { + c->parent_phases.hold(obj, type); + } +} + +static void gicv5_init(Object *obj) +{ +} + +static void gicv5_finalize(Object *obj) +{ +} + +static void gicv5_class_init(ObjectClass *oc, const void *data) +{ + ResettableClass *rc =3D RESETTABLE_CLASS(oc); + GICv5Class *gc =3D ARM_GICV5_CLASS(oc); + + resettable_class_set_parent_phases(rc, NULL, gicv5_reset_hold, NULL, + &gc->parent_phases); +} diff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c new file mode 100644 index 0000000000..b0194f7f26 --- /dev/null +++ b/hw/intc/arm_gicv5_common.c @@ -0,0 +1,31 @@ +/* + * Common base class for GICv5 IRS + * + * Copyright (c) 2025 Linaro Limited + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/intc/arm_gicv5_common.h" + +OBJECT_DEFINE_ABSTRACT_TYPE(GICv5Common, gicv5_common, ARM_GICV5_COMMON, S= YS_BUS_DEVICE) + +static void gicv5_common_reset_hold(Object *obj, ResetType type) +{ +} + +static void gicv5_common_init(Object *obj) +{ +} + +static void gicv5_common_finalize(Object *obj) +{ +} + +static void gicv5_common_class_init(ObjectClass *oc, const void *data) +{ + ResettableClass *rc =3D RESETTABLE_CLASS(oc); + + rc->phases.hold =3D gicv5_common_reset_hold; +} diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 96742df090..e4ddc5107f 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -12,6 +12,10 @@ system_ss.add(when: 'CONFIG_ARM_GICV3', if_true: files( 'arm_gicv3_its.c', 'arm_gicv3_redist.c', )) +system_ss.add(when: 'CONFIG_ARM_GICV5', if_true: files( + 'arm_gicv5_common.c', + 'arm_gicv5.c', +)) system_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-= a10-pic.c')) system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_vic.c')) system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_intc.c')) diff --git a/include/hw/intc/arm_gicv5.h b/include/hw/intc/arm_gicv5.h new file mode 100644 index 0000000000..3cd9652f6f --- /dev/null +++ b/include/hw/intc/arm_gicv5.h @@ -0,0 +1,32 @@ +/* + * ARM GICv5 emulation: Interrupt Routing Service (IRS) + * + * Copyright (c) 2025 Linaro Limited + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_INTC_ARM_GICV5_H +#define HW_INTC_ARM_GICV5_H + +#include "qom/object.h" +#include "hw/core/sysbus.h" +#include "hw/intc/arm_gicv5_common.h" + +#define TYPE_ARM_GICV5 "arm-gicv5" + +OBJECT_DECLARE_TYPE(GICv5, GICv5Class, ARM_GICV5) + +/* + * This class is for TCG-specific state for the GICv5. + */ +struct GICv5 { + GICv5Common parent_obj; +}; + +struct GICv5Class { + GICv5CommonClass parent_class; + ResettablePhases parent_phases; +}; + +#endif diff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5= _common.h new file mode 100644 index 0000000000..d2243c7660 --- /dev/null +++ b/include/hw/intc/arm_gicv5_common.h @@ -0,0 +1,31 @@ +/* + * Common base class for GICv5 IRS + * + * Copyright (c) 2025 Linaro Limited + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_INTC_ARM_GICV5_COMMON_H +#define HW_INTC_ARM_GICV5_COMMON_H + +#include "qom/object.h" +#include "hw/core/sysbus.h" + +#define TYPE_ARM_GICV5_COMMON "arm-gicv5-common" + +OBJECT_DECLARE_TYPE(GICv5Common, GICv5CommonClass, ARM_GICV5_COMMON) + +/* + * This class is for common state that will eventually be shared + * between TCG and KVM implementations of the GICv5. + */ +struct GICv5Common { + SysBusDevice parent_obj; +}; + +struct GICv5CommonClass { + SysBusDeviceClass parent_class; +}; + +#endif --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610226; x=1775215026; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MgRWJYLqD7uzJGEY2M5NKnbTbzCDI5DLqfNZPVYqGzg=; b=CQWade08Yl5A2Qs+lhYaVnE0Z0OTY8q00geaHqKYHTDfGJDsQ6c2JDt7ljCLHEa4P5 3QpTDhW7+sh8g2t9dkBnn467NKp6c6VcH0oKkSqyBZeL+mcFdC2Ope62R3iDOuKpU7jD KTo9P3ZHsprNqzEn7pH9N2BX/IL7u837TIZFWYocodJmNBhdogXN9QGonqV7qd0cP4Y1 W3KZggowZqwfFnIEnTRrFqJKlaJdl8U6arpGjo9dt66VQm9vIjhpNKdsd/lW9dojL0Re Xdvy2wwwq6chyzLrcC/vhfQ6vT8LrfPeJvqq2ff/SevdhtD0Ed2m9YAQd6By33n/Zruw 74Og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610226; x=1775215026; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=MgRWJYLqD7uzJGEY2M5NKnbTbzCDI5DLqfNZPVYqGzg=; b=kqPJ7OJ5RR7hZYVPHmF6ztwC2V5MN6ZwT9bPF1owwwkEXiCU4NvxrX46r9cRBqSx5P 1Sy15Qj1S75BHa9RC/ItwITiJjh91gNovslcBjsZ3Awy8Im5D6Cg30NjJ4wXa/n6mSFg Pr7EX/CIRUrfV+E8y3iWGAMqg4kl9HqakO/DU/6+Smc6IYntzTrMphRAeoAwYiRf13bw u+4SSt9m15saSscOwMmkRuHIrRs/X2DYVaMcpEanXPFBkVJQW+Cv8pjP8xoGRGFsTXlx 36mvPjCmPEsPJbt/ZdSvMlAVDShFrAHaMOiKHyuT26E6ZJX9/r9TiP0vTA4mBjIaIfgB R7PA== X-Forwarded-Encrypted: i=1; AJvYcCW3DOXhfxxZWh7wJDKMIoo5OatW+pyanWbAshIEf5WaA7q/t+Q0JFe0r7fdwJ6lriGsvrqlOTVDDfRu@nongnu.org X-Gm-Message-State: AOJu0YzWou6bR5xD3AeIJpX2/Yybi/vyXrDZN/dh99UzPW2ufi3B5nd/ N1ds6whGbwh1BdgFEOs5R96PDbO0OkpMx5A87Ubc87g/g8GwSOf06XYq/5GgRpF+6LFgdgHjXdA 8uJ6fsbU= X-Gm-Gg: ATEYQzxiErjcx/MZJRJLoEqyq4fl7wVMdEKRftUZ+JJkRBWkGswSizXRU5kTZ2gp7hT PcJi8dzVkJmVmdUw5wdG73a1F9X4DxTvvJ9/PsMWeMLufIW92ofsuK0NJL6T++xRx3qqmSyGWbF dd5PsUvuvQQ9aOvt4H3+L7tfTwsYVJcVc8/0L2cbEKQE/bg1Bbs9ILmAdTn0dHgxLplKIc5JmKp 15DQHJuW5XOS7CYF6drpacFoYQO+Jh02Md0SWHtgcONYXBPMEWG/P4bVT4y7+UpPUNYpMyWSIPG 5pXZj6AwgrdkHbriyqscX0Ej+K8diy+1nC/0Vj6nBDP3qjsX34XenC4a8s5Q0QmUaTrSnXG5iny EhCoMjFlXqtqDbTd/M1p/YHVCxDOx7qj5qf2xxPWboGivmIDTOMk7itQrtbI5y5ypllCYHI3Hv4 3zfpwYjtTJZBOFAhs3mueq3OIR9A5jYHlzx6Lq5bIqF8wu2IVPDNltqg0CdiVnnKSVXmn1JH2jW wv6hFCFyW77q7osa5FMYEKlkrXLbDc= X-Received: by 2002:a05:6000:40cd:b0:436:3707:2bf0 with SMTP id ffacd0b85a97d-43b9ea465e0mr3098628f8f.35.1774610225672; Fri, 27 Mar 2026 04:17:05 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 04/65] hw/arm/Kconfig: select ARM_GICV5 for ARM_VIRT board Date: Fri, 27 Mar 2026 11:15:59 +0000 Message-ID: <20260327111700.795099-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610613687154100 Content-Type: text/plain; charset="utf-8" When building the Arm "virt" board, pull in the GICv5. We haven't added support for creating or wiring up the GICv5 in that board yet, but adding it to the Kconfig early means that the GICv5 code will be compiled and so we can have more confidence that the individual commits building it up are correct (or at least compile). Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 4e50fb1111..e1a6dba1e9 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -10,6 +10,7 @@ config ARM_VIRT imply NVDIMM imply IOMMUFD select ARM_GIC + select ARM_GICV5 select ACPI select ARM_SMMUV3 select GPIO_KEY --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610685; cv=none; d=zohomail.com; s=zohoarc; b=OXn2M5D+THC3XX/57Na5+VdXauBxkt7FmlBM2USdYr7aavFQ3ht/wKbEqm5rqiYraYqzhv2zYMin/EZIRR9jkFOYAeAIl/ybQ/GKfvO4/UctwadF8eWWCcuneCVOx1TshBHGVBaAvOdePDNGAESJFFaTd6EvVMYBzExEqXc+rdk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610685; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=AYuqw3HFZoF9226pvAWhjUsB9lC+vN3nYVgH2xmrsaQ=; b=N8N8JgzqtZ0Cbv0pHgHB6GX/zYSD8QJGU5wFaHEzWjyY3CKdySsAqytkmxNoRA7mKXhAgbEsHPnYqrFFgC8VI2M34DmaByB7VYPZXnOcGNrbBu6fEWuyR65CSrQIIebk11CKASnKVcdKWNXh8Ekj0v8hxaKkwWiDFIuDQh2akFU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610685966589.2404078810886; Fri, 27 Mar 2026 04:24:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65Bi-0006OL-8m; Fri, 27 Mar 2026 07:17:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65Bf-0006Mj-4l for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:12 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65Bc-0007cz-Cl for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:10 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-439af7d77f0so1576599f8f.0 for ; Fri, 27 Mar 2026 04:17:07 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610227; x=1775215027; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AYuqw3HFZoF9226pvAWhjUsB9lC+vN3nYVgH2xmrsaQ=; b=ZgqDApvphhAFANZ/oUZGcy44/Xo/d7Ge5YApUy9OEPXgd46vUmuLUqPHf2dPt9WZug Az+vJCbvKPClEjvk7OuS1rNsAx6e8OfCJGJzILSaTDzzPvBmEaxxfbQSTM2PxXR/FaHq RT8XY+GwCiqSVvAMqxkVZFx0OCr4K3wPmLznd3YqGrIEWDTlWdIuWMWhmXTlaLtoIngX YP9pY8cZwjBFLEr8M1j2Udodn2VKilmFgW+GYmicf+guGR9hm7GvOKXF/arG35Au4nJn d8eGqb3Ck0OLPl4n/esNEmuxhUhGLIHpWSmXSpfaJitDCfsWAaWSM9CAzx+IdEy9/K+b jaFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610227; x=1775215027; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=AYuqw3HFZoF9226pvAWhjUsB9lC+vN3nYVgH2xmrsaQ=; b=fxsxiP2AD+ppdW3K6P1yrIDLugt2j7qndWkD3jYDUy7VBpCq4ssdgPlgww+6W8UyCl B25nVcZ7Pr6t9dd5p2OC3/Ca0PqB809d2MyDL3ub6cTVzb/7N6Rlj9Gr+tj/3HUJq1KN w88Zf6Vyvj3M0eD3gukFhitO1KVCeCN4WFsQwdwjdcMZoSHL/C32/aRHAghdGaRl/a3K FgaXtWUlyUzL2CUj2ajrJSoMRqsJ++aBmXUzg+EeX57Y7n6xeq3rsHUNV/9qM7mFL5Zj nyIn8Gvl6ssKn8W6sp3uq00SFZCXbxytEbbvQvPaL9pQibsVDaS3UOciWguI9AKpYHJg mv9g== X-Forwarded-Encrypted: i=1; AJvYcCU/KngusHe+3LZSbDtbe8F+zpcWiiba50fWC1SAc/Y45Fepw2FqkM0AdwpfUb/nvVMc+HNUR2kKirid@nongnu.org X-Gm-Message-State: AOJu0Yy2pQoNW3m0FejwIiSo8r4mh0YjKC/GGzvonekOoyZCzdkeGnwY GkvLeK8B9w0+r5Ygl6jc/eqL5hwa4+seiJkDwR7jCelTOTdR1K+iH6xTNMHO+soP5J4= X-Gm-Gg: ATEYQzyVWVv4U6hpHwnKRTf8Xp80qeaMlfwM/qdXLAYapk3XMjQV87MgRMEGXdnpug7 3Ih15Wbwm2c6/GPvu0Y6Q5EM6f+j/ulOik1z7uFuynAUBxHmMPkBQk4qXjz+QdGyRUQViY87GIa objWS/g1GcXDensuphmn7fzI2ZbMwa9PXyYb7jy/hRq9KRW1kyhDrgW9V2E+LaiR5zbVhrDR3rO 0xUDwBVXSO0ZEJXXzuDqKEfHfeoUB/FyWs4+mvyRRMvponGXY5aO/lZZJN7LeKiaqzBOZt67yhV +PpWxKlvGK7aLETjJf15K0a8xg6ZfACXU5LfTx0Oju99SfcdWuDMInPxyNoi2ekS6lXvItdrx3B WbY3MZgokcCoHiYsvK14afDlwIr/U8/0k671zSuCPaRsPKC715J25ySWSDMeYPqaNqCJ69qX+/4 VQwWMXDvxTsnxQ3F5DyUwjh4jTPvqeIXpjP48gtr7t4u/5V5HPGP+Z3ZD8FrPZXxCEqok7g2rpR 6FC3BaiR8Fk1bDEwEol2IYI5YAZYNQ= X-Received: by 2002:a05:6000:310c:b0:43b:4f7d:e085 with SMTP id ffacd0b85a97d-43b9e9ee634mr3531010f8f.35.1774610226582; Fri, 27 Mar 2026 04:17:06 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 05/65] hw/intc/arm_gicv5: Implement skeleton code for IRS register frames Date: Fri, 27 Mar 2026 11:16:00 +0000 Message-ID: <20260327111700.795099-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610688946154100 Content-Type: text/plain; charset="utf-8" The GICv5 IRS has one mandatory register frame (the config frame) for each of up to four supported physical interrupt domains. Implement the skeleton of the code needed to create these as sysbus MMIO regions. The config frame has a mix of 32-bit and 64-bit registers, and it is valid to access the 64-bit registers with 32-bit accesses. In a similar way to the various GICv3 devices, we turn the MemoryRegionOps read_with_attrs and write_with_attrs calls into calls on functions specifically to read 32 or 64 bit values. (We can't trivially implement one in terms of the other because various registers have side effects on write which must only trigger when the "correct" half of the 64-bit register is written to.) Unlike the GICv3, we choose to expose a sysbus MMIO region for each interrupt domain even if the config of the GICv5 means that it doesn't implement that domain. This avoids having the config frame for a domain ending up at a different MMIO region index depending on the config of the GICv5. (This matters more for GICv5 because it supports Realm, and so there are more possible valid configurations.) gicv5_common_init_irqs_and_mmio() does not yet create any IRQs, but we name it this way to parallel the equivalent GICv3 function and to avoid having to rename it when we add the IRQ line creation in a subsequent commit. The arm_gicv5_types.h header is a little undermotivated at this point, but the aim is to have somewhere to put definitions that we want in both the GIC proper and the CPU interface. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5.c | 172 +++++++++++++++++++++++++++++ hw/intc/arm_gicv5_common.c | 35 ++++++ hw/intc/trace-events | 6 + include/hw/intc/arm_gicv5.h | 1 + include/hw/intc/arm_gicv5_common.h | 50 +++++++++ include/hw/intc/arm_gicv5_types.h | 28 +++++ 6 files changed, 292 insertions(+) create mode 100644 include/hw/intc/arm_gicv5_types.h diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index f9dab710d3..3a9d566924 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -8,9 +8,157 @@ =20 #include "qemu/osdep.h" #include "hw/intc/arm_gicv5.h" +#include "qapi/error.h" +#include "qemu/log.h" +#include "trace.h" =20 OBJECT_DEFINE_TYPE(GICv5, gicv5, ARM_GICV5, ARM_GICV5_COMMON) =20 +static const char *domain_name[] =3D { + [GICV5_ID_S] =3D "Secure", + [GICV5_ID_NS] =3D "NonSecure", + [GICV5_ID_EL3] =3D "EL3", + [GICV5_ID_REALM] =3D "Realm", +}; + +static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset, + uint64_t *data, MemTxAttrs attrs) +{ + return false; +} + +static bool config_writel(GICv5 *s, GICv5Domain domain, hwaddr offset, + uint64_t data, MemTxAttrs attrs) +{ + return false; +} + +static bool config_readll(GICv5 *s, GICv5Domain domain, hwaddr offset, + uint64_t *data, MemTxAttrs attrs) +{ + return false; +} + +static bool config_writell(GICv5 *s, GICv5Domain domain, hwaddr offset, + uint64_t data, MemTxAttrs attrs) +{ + return false; +} + +static MemTxResult config_read(void *opaque, GICv5Domain domain, hwaddr of= fset, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + GICv5 *s =3D ARM_GICV5(opaque); + bool result; + + switch (size) { + case 4: + result =3D config_readl(s, domain, offset, data, attrs); + break; + case 8: + result =3D config_readll(s, domain, offset, data, attrs); + break; + default: + result =3D false; + break; + } + + if (!result) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid guest read for IRS %s config frame " + "at offset " HWADDR_FMT_plx + " size %u\n", __func__, domain_name[domain], + offset, size); + trace_gicv5_badread(domain_name[domain], offset, size); + /* + * The spec requires that reserved registers are RAZ/WI; so we + * log the error but return MEMTX_OK so we don't cause a + * spurious data abort. + */ + *data =3D 0; + } else { + trace_gicv5_read(domain_name[domain], offset, *data, size); + } + + return MEMTX_OK; +} + +static MemTxResult config_write(void *opaque, GICv5Domain domain, + hwaddr offset, uint64_t data, unsigned siz= e, + MemTxAttrs attrs) +{ + GICv5 *s =3D ARM_GICV5(opaque); + bool result; + + switch (size) { + case 4: + result =3D config_writel(s, domain, offset, data, attrs); + break; + case 8: + result =3D config_writell(s, domain, offset, data, attrs); + break; + default: + result =3D false; + break; + } + + if (!result) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid guest write for IRS %s config frame " + "at offset " HWADDR_FMT_plx + " size %u\n", __func__, domain_name[domain], + offset, size); + trace_gicv5_badwrite(domain_name[domain], offset, data, size); + /* + * The spec requires that reserved registers are RAZ/WI; so we + * log the error but return MEMTX_OK so we don't cause a + * spurious data abort. + */ + } else { + trace_gicv5_write(domain_name[domain], offset, data, size); + } + + return MEMTX_OK; +} + +#define DEFINE_READ_WRITE_WRAPPERS(NAME, DOMAIN) = \ + static MemTxResult config_##NAME##_read(void *opaque, hwaddr offset, = \ + uint64_t *data, unsigned size,= \ + MemTxAttrs attrs) = \ + { = \ + return config_read(opaque, DOMAIN, offset, data, size, attrs); = \ + } = \ + static MemTxResult config_##NAME##_write(void *opaque, hwaddr offset, = \ + uint64_t data, unsigned size,= \ + MemTxAttrs attrs) = \ + { = \ + return config_write(opaque, DOMAIN, offset, data, size, attrs); = \ + } + +DEFINE_READ_WRITE_WRAPPERS(ns, GICV5_ID_NS) +DEFINE_READ_WRITE_WRAPPERS(realm, GICV5_ID_REALM) +DEFINE_READ_WRITE_WRAPPERS(secure, GICV5_ID_S) +DEFINE_READ_WRITE_WRAPPERS(el3, GICV5_ID_EL3) + +#define FRAME_OP_ENTRY(NAME, DOMAIN) \ + [DOMAIN] =3D { \ + .read_with_attrs =3D config_##NAME##_read, \ + .write_with_attrs =3D config_##NAME##_write, \ + .endianness =3D DEVICE_LITTLE_ENDIAN, \ + .valid.min_access_size =3D 4, \ + .valid.max_access_size =3D 8, \ + .impl.min_access_size =3D 4, \ + .impl.max_access_size =3D 8, \ + } + +static const MemoryRegionOps config_frame_ops[NUM_GICV5_DOMAINS] =3D { + FRAME_OP_ENTRY(ns, GICV5_ID_NS), + FRAME_OP_ENTRY(realm, GICV5_ID_REALM), + FRAME_OP_ENTRY(secure, GICV5_ID_S), + FRAME_OP_ENTRY(el3, GICV5_ID_EL3), +}; + static void gicv5_reset_hold(Object *obj, ResetType type) { GICv5 *s =3D ARM_GICV5(obj); @@ -21,6 +169,28 @@ static void gicv5_reset_hold(Object *obj, ResetType typ= e) } } =20 +static void gicv5_realize(DeviceState *dev, Error **errp) +{ + GICv5Common *cs =3D ARM_GICV5_COMMON(dev); + GICv5Class *gc =3D ARM_GICV5_GET_CLASS(dev); + + ERRP_GUARD(); + + gc->parent_realize(dev, errp); + if (*errp) { + return; + } + + /* + * When we implement support for more than one interrupt domain, + * we will provide some QOM properties so the board can configure + * which domains are implemented. For now, we only implement the + * NS domain. + */ + cs->implemented_domains =3D (1 << GICV5_ID_NS); + gicv5_common_init_irqs_and_mmio(cs, config_frame_ops); +} + static void gicv5_init(Object *obj) { } @@ -32,8 +202,10 @@ static void gicv5_finalize(Object *obj) static void gicv5_class_init(ObjectClass *oc, const void *data) { ResettableClass *rc =3D RESETTABLE_CLASS(oc); + DeviceClass *dc =3D DEVICE_CLASS(oc); GICv5Class *gc =3D ARM_GICV5_CLASS(oc); =20 + device_class_set_parent_realize(dc, gicv5_realize, &gc->parent_realize= ); resettable_class_set_parent_phases(rc, NULL, gicv5_reset_hold, NULL, &gc->parent_phases); } diff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c index b0194f7f26..bf990bfa54 100644 --- a/hw/intc/arm_gicv5_common.c +++ b/hw/intc/arm_gicv5_common.c @@ -11,6 +11,41 @@ =20 OBJECT_DEFINE_ABSTRACT_TYPE(GICv5Common, gicv5_common, ARM_GICV5_COMMON, S= YS_BUS_DEVICE) =20 +static bool bad_frame_accepts(void *opaque, hwaddr addr, unsigned size, + bool is_write, MemTxAttrs attrs) +{ + return false; +} + +/* + * Used for the sysbus MMIO regions corresponding to IRS frames where + * this IRS does not implement the interrupt domain. It's probably a + * board/SoC error to create an IRS and try to wire up this MMIO + * region, but if it does then the region will behave as unassigned + * memory (generating a decode error). These frames are just here so + * that changing which domains are implemented doesn't reorder which + * sysbus MMIO region is which. + */ +static const MemoryRegionOps bad_frame_ops =3D { + .valid.accepts =3D bad_frame_accepts, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +void gicv5_common_init_irqs_and_mmio(GICv5Common *cs, + const MemoryRegionOps config_ops[NUM_= GICV5_DOMAINS]) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(cs); + + for (int i =3D 0; i < NUM_GICV5_DOMAINS; i++) { + g_autofree char *memname =3D g_strdup_printf("gicv5-irs-%d", i); + const MemoryRegionOps *ops =3D gicv5_domain_implemented(cs, i) ? + &config_ops[i] : &bad_frame_ops; + memory_region_init_io(&cs->iomem[i], OBJECT(cs), ops, cs, + memname, IRS_CONFIG_FRAME_SIZE); + sysbus_init_mmio(sbd, &cs->iomem[i]); + } +} + static void gicv5_common_reset_hold(Object *obj, ResetType type) { } diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 018c609ca5..edd3c49c5f 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -227,6 +227,12 @@ gicv3_its_vte_read(uint32_t vpeid, int valid, uint32_t= vptsize, uint64_t vptaddr gicv3_its_vte_read_fault(uint32_t vpeid) "GICv3 ITS: vPE Table read for vP= EID 0x%x: faulted" gicv3_its_vte_write(uint32_t vpeid, int valid, uint32_t vptsize, uint64_t = vptaddr, uint32_t rdbase) "GICv3 ITS: vPE Table write for vPEID 0x%x: valid= %d VPTsize 0x%x VPTaddr 0x%" PRIx64 " RDbase 0x%x" =20 +# arm_gicv5.c +gicv5_read(const char *domain, uint64_t offset, uint64_t data, unsigned si= ze) "GICv5 IRS %s config frame read: offset 0x%" PRIx64 " data 0x%" PRIx64 = " size %u" +gicv5_badread(const char *domain, uint64_t offset, unsigned size) "GICv5 I= RS %s config frame read: offset 0x%" PRIx64 " size %u: error" +gicv5_write(const char *domain, uint64_t offset, uint64_t data, unsigned s= ize) "GICv5 IRS %s config frame write: offset 0x%" PRIx64 " data 0x%" PRIx6= 4 " size %u" +gicv5_badwrite(const char *domain, uint64_t offset, uint64_t data, unsigne= d size) "GICv5 IRS %s config frame write: offset 0x%" PRIx64 " data 0x%" PR= Ix64 " size %u: error" + # armv7m_nvic.c nvic_recompute_state(int vectpending, int vectpending_prio, int exception_= prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_= prio %d" nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked,= int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpend= ing %d is_s_banked %d vectpending_prio %d exception_prio %d" diff --git a/include/hw/intc/arm_gicv5.h b/include/hw/intc/arm_gicv5.h index 3cd9652f6f..42ccef8474 100644 --- a/include/hw/intc/arm_gicv5.h +++ b/include/hw/intc/arm_gicv5.h @@ -26,6 +26,7 @@ struct GICv5 { =20 struct GICv5Class { GICv5CommonClass parent_class; + DeviceRealize parent_realize; ResettablePhases parent_phases; }; =20 diff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5= _common.h index d2243c7660..b7a17aac31 100644 --- a/include/hw/intc/arm_gicv5_common.h +++ b/include/hw/intc/arm_gicv5_common.h @@ -11,6 +11,26 @@ =20 #include "qom/object.h" #include "hw/core/sysbus.h" +#include "hw/intc/arm_gicv5_types.h" + +/* + * QEMU interface: + * + * sysbus MMIO regions (in order matching IRS_IDR0.INT_DOM encoding): + * - IRS config frame for the Secure Interrupt Domain + * - IRS config frame for the Non-secure Interrupt Domain + * - IRS config frame for the EL3 Interrupt Domain + * - IRS config frame for the Realm Interrupt Domain + * + * Note that even if this particular IRS does not implement all four + * interrupt domains it will still expose four sysbus MMIO regions. + * The regions corresponding to unimplemented domains will always fail + * accesses with a decode error. Generally the SoC/board should + * probably not map a region for a domain that it configured the IRS + * to not implement; the regions are only exposed so that changing + * which domains are implemented doesn't reorder which sysbus MMIO + * region is which (e.g. NS will always be 1 and EL3 will always be 2). + */ =20 #define TYPE_ARM_GICV5_COMMON "arm-gicv5-common" =20 @@ -22,10 +42,40 @@ OBJECT_DECLARE_TYPE(GICv5Common, GICv5CommonClass, ARM_= GICV5_COMMON) */ struct GICv5Common { SysBusDevice parent_obj; + + MemoryRegion iomem[NUM_GICV5_DOMAINS]; + + /* Bits here are set for each physical interrupt domain implemented */ + uint8_t implemented_domains; }; =20 struct GICv5CommonClass { SysBusDeviceClass parent_class; }; =20 + +#define IRS_CONFIG_FRAME_SIZE 0x10000 + +/** + * gicv5_common_init_irqs_and_mmio: Create IRQs and MMIO regions for the G= ICv5 + * @s: GIC object + * @ops: array of MemoryRegionOps that implement the config frames behavio= ur + * + * Subclasses of ARM_GICV5_COMMON should call this to create the sysbus + * MemoryRegions for the IRS config frames, passing in a four element array + * of MemoryRegionOps structs. + */ +void gicv5_common_init_irqs_and_mmio(GICv5Common *cs, + const MemoryRegionOps ops[NUM_GICV5_D= OMAINS]); + +/** + * gicv5_domain_implemented: Return true if this IRS implements this domain + * @s: GIC object + * @domain: domain to check + */ +static inline bool gicv5_domain_implemented(GICv5Common *cs, GICv5Domain d= omain) +{ + return cs->implemented_domains & (1 << domain); +} + #endif diff --git a/include/hw/intc/arm_gicv5_types.h b/include/hw/intc/arm_gicv5_= types.h new file mode 100644 index 0000000000..49dc1d6e95 --- /dev/null +++ b/include/hw/intc/arm_gicv5_types.h @@ -0,0 +1,28 @@ +/* + * Type definitions for GICv5 + * + * This file is for type definitions that we want to share between + * the GIC proper and the CPU interface. + * + * Copyright (c) 2025 Linaro Limited + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_INTC_ARM_GICv5_TYPES_H +#define HW_INTC_ARM_GICv5_TYPES_H + +/* + * The GICv5 has four physical Interrupt Domains. This numbering must + * match the encoding used in IRS_IDR0.INT_DOM. + */ +typedef enum GICv5Domain { + GICV5_ID_S =3D 0, + GICV5_ID_NS =3D 1, + GICV5_ID_EL3 =3D 2, + GICV5_ID_REALM =3D 3, +} GICv5Domain; + +#define NUM_GICV5_DOMAINS 4 + +#endif --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610274; cv=none; d=zohomail.com; s=zohoarc; b=D6L/WZsIs8qze9BzklOPAHE620rv/kJpwNVW6fOv2KGOV4evw15Iik6xBcD1phYYkum+TYIwsSD4cYJFySdKkiokUDo9suXhYDxhmkQS8RyjNbdYO+1hUjl70OfOc4lQtRpYhN/CvmW0ynjy4d+fSRkPs2gVzsxUsCY7XD6MWAs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610274; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=amX7qN1Oe+nF222PYlnbVwaAHtsoUnvlRllsmPM1bzc=; b=PlyfrdmtQIxYXwWBCNK7pEMz5nTJTF+82l+dVyI50hKDpy4Mpifw+etSNvS6mXnjRuod1gOJaqlMFq2igu1rqkAtiBfIRSAqca1RVt/AV6iR+akan0pNqV8ewmjM+CwfgXbgVUiYMyJw5RGky2X/IYe8tHNfBFQhotm/FAk+Ios= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610274009628.3789333646378; Fri, 27 Mar 2026 04:17:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65Bk-0006PV-IR; Fri, 27 Mar 2026 07:17:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65Bf-0006Mg-2x for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:11 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65Bd-0007ez-Ad for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:10 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-486fba7ce4cso20562965e9.3 for ; Fri, 27 Mar 2026 04:17:08 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610228; x=1775215028; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=amX7qN1Oe+nF222PYlnbVwaAHtsoUnvlRllsmPM1bzc=; b=o+CcN3n3r7uF5mB/W1o5vP6DRlP+E0jdPUBSYX6JwiztFPj0MODTitCOsNVEPqrs2g GUbTdAe1ADSta6g0T57hqd6fcZGW2xLMQsfvszZ9raT/36YfRJxUA1Kvq7H4/2cclMnw WRibOg/AgagdlD+lY0kCPbfA1E7O/UypBp5LzrQIhyabUumKX+RZJ4ITxeysAt4sFwZH OwFkNNO/sKszGtZsFGD46iriRrxpZLF9k7epEmoI+YPvDasEkxK2DJl43dLygOy8gOxT mtDrlQD5HVO7r1M21ROOyzWCirNkxZ6tFjplrVZR+1WnuXylQ+dhAB8P51BCJE3Cyf5e OVdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610228; x=1775215028; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=amX7qN1Oe+nF222PYlnbVwaAHtsoUnvlRllsmPM1bzc=; b=BWrOrA2SfEn/T0y10eVwyriCRz1AvHGrh02bpbb8h1ewgWX8Rf293nWmexx38Uy6sz XPxSu/vf+au6DgoDTTT/JITe44Zzwz8Y8ylIlIVl81psfr2Gvn+tFHuEy8FI5VhEY1UB o//G0gmLQkWA3WLBfB+8L1VHS58rNfYd/ReW0C4DHV1uSfhAm+9ra7b563rNNWQHysqY dfINyQM32ICT6gHo/tE0YRe2O9gJRxTjqSmVBmSoAqVDECkG+UgUD8CukVn30bPt+v2z XeiSghrQxKoKGmAZOAC80UzQ1mYMqZjcUFoflLNX7D2ICwbTcdz+JA/3ou0UssAEihQp RChA== X-Forwarded-Encrypted: i=1; AJvYcCX0AJCaqJeGTSqgUbMMf9Df1wZOrYnyCKwpW3i9cl/V4cYo80H7SYEz9ParV+diqAUen+ZLtCnQmZhk@nongnu.org X-Gm-Message-State: AOJu0YzBNpABRrqsC9vqbR43EGBvcVovSBdqrNW5WPnMA2oaKSRBsqgO CfdaWiODATPLM7Af4+wBx8GBmiLAW8Te87CgUQyYGEutoAyC4CMYHDA5KOeZGrLjrGp5cH5k7gC KEwu0Fx0= X-Gm-Gg: ATEYQzzkpSICzaOMIQmZtee91wTl1citU8Aq1LuWWK6R6dJ52M+RAfu52+9MzT9FZnm KYdqpUu2JdVDY5N8/N6g+hI18H5fWKVXKMCrsGe0m26Vp/GuZ65mKWBmWO2PYCavXvxXW0LXXU1 qnng84+dTJHOna3WTuV+01qOA0Kaf9b58ocIUn8AwYMyiDoMncoUz3k/aaWCvbEg+wL+UlWF2Kh UjJyIGQzMRMO2+LbBUl9TakHSMPpIdUse5U5zvWiFM8FzNzzbVYNgm6prr67WrUk/Fn950TE1q0 8eoibs4g6RTLAokPb1jou0A7m6lypkD96carLhKO9SnvqVOmpNVY8MPWHNQcozKIzwXBQK/li7r Hn5OI3GgIDn7ONYuvTGjsio+VFjgSjL6/wVlxI4ZucUYfRf5E5Uj95w1syA36ub5QNDjorRUm50 lhssBdR/Y2ZELzu+2+tciPDlA06nHDWetUkMzukdVAGKWQjLLP7+0iBcoZ+oOBZRB7CdGExhDiI srvjS905fdS6tuR4iidltNtSxp6LBY= X-Received: by 2002:a05:600c:4f91:b0:486:f634:ef1 with SMTP id 5b1f17b1804b1-48727eda549mr35026215e9.17.1774610227580; Fri, 27 Mar 2026 04:17:07 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 06/65] hw/intc/arm_gicv5: Add migration blocker Date: Fri, 27 Mar 2026 11:16:01 +0000 Message-ID: <20260327111700.795099-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610276309158500 Content-Type: text/plain; charset="utf-8" This initial version of the GICv5 will not support migration: * the spec is still only at EAC level, so the data to be migrated might in theory change before it is finalised * when we add support for missing features like EL2/EL3/Realm we might find we want to refactor the data structures we use * I still need to check against the proposed KVM GICv5 handling to see if there are any awkward mismatches that might affect how we want to store the data * it's experimental, so for pragmatic reasons I'm skipping it to get the initial version done faster Install a migration blocker to enforce this. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 3a9d566924..64bec16bdd 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -11,6 +11,7 @@ #include "qapi/error.h" #include "qemu/log.h" #include "trace.h" +#include "migration/blocker.h" =20 OBJECT_DEFINE_TYPE(GICv5, gicv5, ARM_GICV5, ARM_GICV5_COMMON) =20 @@ -173,6 +174,7 @@ static void gicv5_realize(DeviceState *dev, Error **err= p) { GICv5Common *cs =3D ARM_GICV5_COMMON(dev); GICv5Class *gc =3D ARM_GICV5_GET_CLASS(dev); + Error *migration_blocker =3D NULL; =20 ERRP_GUARD(); =20 @@ -181,6 +183,12 @@ static void gicv5_realize(DeviceState *dev, Error **er= rp) return; } =20 + error_setg(&migration_blocker, + "Live migration disabled: not yet supported by GICv5"); + if (migrate_add_blocker(&migration_blocker, errp)) { + return; + } + /* * When we implement support for more than one interrupt domain, * we will provide some QOM properties so the board can configure --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610800; cv=none; d=zohomail.com; s=zohoarc; b=drfKMaQ2NW+EElkqiaSwmwtgUkR5OW7ItQM4KYuZQ3UhYjwKkiL54VbMJjihwYSEPDVUO1gbVFPt1BLB6huSZcscCVHGGeBjB68CYkkIaEZ/cehs75oYzW6EXYH1EjdhTj62jXN0PL8Xhg4ULttzC6E2FwtIICHsvHv7wYGrjnA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610800; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=q+a1vwfitmUycYoLhCWK2VU83xMZoXvp5UmVsl5NDqE=; b=fUc6i9mNnMYigXd3aFKVqhGOW0hGPyly5+P+J5M1ZLfhoM7VFgap2pX+NCI+YTLvxoCdWuxVS53Zr2ofZ2c3tFcMXJ1lJcRNUC15/cC3Prna3cLz6KEaci4Cv6oJZRZrq3weadqdBWzkcojIgVsCd6U8f8k3BjYUeAni+9pW0FU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610800895694.1026024226545; Fri, 27 Mar 2026 04:26:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65Br-0006Vv-7s; Fri, 27 Mar 2026 07:17:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65Bg-0006NT-RB for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:13 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65Be-0007iO-5o for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:12 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-43b9144790dso1094565f8f.1 for ; Fri, 27 Mar 2026 04:17:09 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610229; x=1775215029; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=q+a1vwfitmUycYoLhCWK2VU83xMZoXvp5UmVsl5NDqE=; b=lEylRPecf3ETM0SZpitVH3iRx5+8a0lGeOD2Esb82yb6HuBZZ1l+QYe7JBN91hULEI 3HBLmtm/jAHLkxv+ytquagJkohv5z5CSghE0YT7U/prR13ImUxEa70F434OI1wHFjbNI jtifb5Dmc5O6B0T8e7rtHH7bDrY7NYTIrTcW7No6mWPCGsZv+PmGzNNUrJGenF7yz8/5 mE8/kYdxDdNWEwHmt2iU7rXNhaHRchxppViNmZ1pxbFhhtzrWNycOCMwfbx1+IGi5Lom jnznG5sCMXNMQKdAHg3TglbVyVDu543At6hCbkMYnHJIZCypnmqerxzszCbGJqVfutYN EOdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610229; x=1775215029; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=q+a1vwfitmUycYoLhCWK2VU83xMZoXvp5UmVsl5NDqE=; b=rDYFyV+IqJhQ1IPR+bMfsE5T7AFBEPKWVw1VafUQj00T3mAz3b0LW5TG9dwHu561Cr Riy7Ygkky3MyKPyUaJts2DHWZlAkXem+ASLfVTX1gW5EEQMWUeuckLwsHUXf3+a8Dds2 JUfobkFTMzoHNBfo826iqdaBj7HqFF/VLlZGy2oGO2t1ijFGK33942l3ZYzEz2yh9VFj OMEZZ0vuj4HW4tVcnzovKfBwkiU50ipW0Bo1niH1UH0qvmK3VEN3IIBQwUZWPEcQHhFl J2JdSPlECfkai+NkksUrNbqsJoIGMHD+LVMBkFzJMLvyyKEiqMe1NeH7AE1CRduEHS6F hyvA== X-Forwarded-Encrypted: i=1; AJvYcCWdW2qX3BAREO9k39cjVTqGXqoQsUn/alQdRs1ig3QegOpsldpoK3RZvEgVy+lbvdnKCFirHU9Nmnck@nongnu.org X-Gm-Message-State: AOJu0YxfEOvApBrmG+J5KVxeksDR+ZRPOEGafkkl95i4lQXt/BcW8BD9 k6YlAVW0SYMns6gkoUEe8n+Sg7XXeCUx8lWRyuhnm/Dxmd1O43i5RytgYgqy70h0iEEt8Szih3k HVGCFyno= X-Gm-Gg: ATEYQzxREGyK6hzzppVt2fdMMzBBlc4bBd6fjOMJtX3jkpX8+ymD62OGc4KyS1DJAeS c921VoF70LnP3z8D46r9iDZQeXBbdjMXr1r7jHNQUslnVb59FC+vpFCyQj7+KPF+l+KpP2yLnI7 7PshchhwBgWCxHMa2BDmR/YFb1HmXGUtWwGWIFk18zcmORny3qIL0mNuCORNeKEZmkOX3It6d4I zL23G4Xql1x0QhpUewROjvtIzOwJkHhvDdMqZBpM6wDBWbaZ/WM3b1Jd53XXm1DXEFLjyVzSVDj 7SuUJVRF7Bkn30YKDzA/OhVgJfM0u7YMzeqvxmquey2acmaziWXrMN2UEUtAtC38M0bmJUJYorf J26gLBsSM/L/Il3IN4ppIq8tpWMlfgU/peGv+uEsrZsVnPUtbj519TcM+4mIWuMJ3MrgRg4SLmA YLfO6gNFTvNthcE6Xy6CUdJ9ZToJYp3WmVu67TUCHGRERjZZoqfDwkqUyBVunR2SvZbgB+DZ6Zz NCWjcB9p/FDcicnpLZv/9rdi7a9dj0= X-Received: by 2002:a05:6000:613:b0:43b:8766:600b with SMTP id ffacd0b85a97d-43b9ea11981mr3393090f8f.49.1774610228476; Fri, 27 Mar 2026 04:17:08 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 07/65] hw/intc/arm_gicv5: Create and validate QOM properties Date: Fri, 27 Mar 2026 11:16:02 +0000 Message-ID: <20260327111700.795099-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610802685154100 Content-Type: text/plain; charset="utf-8" Add code to the GICv5 skeleton which creates the QOM properties which the board or SoC can use to configure the GIC, and the validation code to check they are in range. Generally these correspond to fields in the IRS ID registers, and the properties are named correspondingly. Notable here is that unlike the GICv3 (which assumes its connected CPUs are the system's CPUs starting from 0), we define a QOM array property which is an array of pointers to the CPUs, and a QOM array property which is an array of integers telling the GIC what the IAFFID (interrupt affinity ID) for each CPU is; so a board or SoC which wants to connect multiple CPUs to this GICv5 would do something like: QList *cpulist =3D qlist_new(), *iaffidlist =3D qlist_new(); for (int i =3D 0; i < ms->smp.cpus; i++) { qlist_append_link(cpulist, OBJECT(qemu_get_cpu(i))); qlist_append_int(iaffidlist, i); } qdev_prop_set_array(vms->gic, "cpus", cpulist); qdev_prop_set_array(vms->gic, "cpu-iaffids", iaffidlist); Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5_common.c | 80 ++++++++++++++++++++++++++++++ hw/intc/trace-events | 3 ++ include/hw/intc/arm_gicv5_common.h | 25 ++++++++++ 3 files changed, 108 insertions(+) diff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c index bf990bfa54..3448734686 100644 --- a/hw/intc/arm_gicv5_common.c +++ b/hw/intc/arm_gicv5_common.c @@ -8,9 +8,15 @@ =20 #include "qemu/osdep.h" #include "hw/intc/arm_gicv5_common.h" +#include "hw/core/qdev-properties.h" +#include "qapi/error.h" +#include "trace.h" =20 OBJECT_DEFINE_ABSTRACT_TYPE(GICv5Common, gicv5_common, ARM_GICV5_COMMON, S= YS_BUS_DEVICE) =20 +/* Any value > 2^24 is out of the valid range for this property */ +#define GICV5_SPI_IRS_RANGE_NOT_SET 0xffffffff + static bool bad_frame_accepts(void *opaque, hwaddr addr, unsigned size, bool is_write, MemTxAttrs attrs) { @@ -58,9 +64,83 @@ static void gicv5_common_finalize(Object *obj) { } =20 +static void gicv5_common_realize(DeviceState *dev, Error **errp) +{ + GICv5Common *cs =3D ARM_GICV5_COMMON(dev); + + if (cs->num_cpus =3D=3D 0) { + error_setg(errp, "The cpus array property must have at least one C= PU"); + return; + } + if (cs->num_cpus >=3D (1 << 16)) { + /* We'll hit other QEMU limits long before this one :-) */ + error_setg(errp, "Number of CPUs exceeds GICv5 architectural maxim= um"); + return; + } + if (cs->num_cpus !=3D cs->num_cpu_iaffids) { + error_setg(errp, "The cpu-iaffids array property must be the same = size " + "as the cpus array property"); + return; + } + if (cs->irsid >=3D (1 << 16)) { + error_setg(errp, "irsid (%u) is more than 2^16-1", cs->irsid); + return; + } + if (cs->spi_range > (1 << 24)) { + /* + * Note that IRS_IDR5.SPI_RANGE is a 25 bit field but the largest + * architecturally permitted value is 2^24 (not 2^25-1), hence + * use of > in the range check. + */ + error_setg(errp, "spi-range (%u) is more than 2^24", cs->spi_range= ); + return; + } + if (cs->spi_irs_range =3D=3D GICV5_SPI_IRS_RANGE_NOT_SET) { + /* spi-irs-range defaults to same as spi-range */ + cs->spi_irs_range =3D cs->spi_range; + } + if (cs->spi_irs_range > (1 << 24)) { + /* Similarly IRS_IDR6.SPI_IRS_RANGE */ + error_setg(errp, "spi-irs-range (%u) is more than 2^24", + cs->spi_irs_range); + return; + } + if (cs->spi_base >=3D (1 << 24)) { + /* IRS_IDR7.SPI_BASE is a 24-bit field, so range check is >=3D */ + error_setg(errp, "spi-base (%u) is more than 2^24-1", cs->spi_base= ); + return; + } + /* range checks above mean we know this addition won't overflow */ + if (cs->spi_base + cs->spi_irs_range > cs->spi_range) { + error_setg(errp, "spi-base (%u) + spi-irs-range (%u) is " + "more than spi-range (%u)", + cs->spi_base, cs->spi_irs_range, cs->spi_range); + return; + } + + trace_gicv5_common_realize(cs->irsid, cs->num_cpus, + cs->spi_base, cs->spi_irs_range, cs->spi_ra= nge); +} + +static const Property arm_gicv5_common_properties[] =3D { + DEFINE_PROP_LINK_ARRAY("cpus", GICv5Common, num_cpus, + cpus, TYPE_ARM_CPU, ARMCPU *), + DEFINE_PROP_ARRAY("cpu-iaffids", GICv5Common, num_cpu_iaffids, + cpu_iaffids, qdev_prop_uint32, uint32_t), + DEFINE_PROP_UINT32("irsid", GICv5Common, irsid, 0), + DEFINE_PROP_UINT32("spi-range", GICv5Common, spi_range, 0), + DEFINE_PROP_UINT32("spi-base", GICv5Common, spi_base, 0), + DEFINE_PROP_UINT32("spi-irs-range", GICv5Common, spi_irs_range, + GICV5_SPI_IRS_RANGE_NOT_SET), +}; + static void gicv5_common_class_init(ObjectClass *oc, const void *data) { ResettableClass *rc =3D RESETTABLE_CLASS(oc); + DeviceClass *dc =3D DEVICE_CLASS(oc); =20 rc->phases.hold =3D gicv5_common_reset_hold; + + dc->realize =3D gicv5_common_realize; + device_class_set_props(dc, arm_gicv5_common_properties); } diff --git a/hw/intc/trace-events b/hw/intc/trace-events index edd3c49c5f..54777f6da3 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -233,6 +233,9 @@ gicv5_badread(const char *domain, uint64_t offset, unsi= gned size) "GICv5 IRS %s gicv5_write(const char *domain, uint64_t offset, uint64_t data, unsigned s= ize) "GICv5 IRS %s config frame write: offset 0x%" PRIx64 " data 0x%" PRIx6= 4 " size %u" gicv5_badwrite(const char *domain, uint64_t offset, uint64_t data, unsigne= d size) "GICv5 IRS %s config frame write: offset 0x%" PRIx64 " data 0x%" PR= Ix64 " size %u: error" =20 +# arm_gicv5_common.c +gicv5_common_realize(uint32_t irsid, uint32_t num_cpus, uint32_t spi_base,= uint32_t spi_irs_range, uint32_t spi_range) "GICv5 IRS realized: IRS ID %u= , %u CPUs, SPI base %u, SPI IRS range %u, SPI range %u" + # armv7m_nvic.c nvic_recompute_state(int vectpending, int vectpending_prio, int exception_= prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_= prio %d" nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked,= int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpend= ing %d is_s_banked %d vectpending_prio %d exception_prio %d" diff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5= _common.h index b7a17aac31..ea01b2a1db 100644 --- a/include/hw/intc/arm_gicv5_common.h +++ b/include/hw/intc/arm_gicv5_common.h @@ -12,10 +12,24 @@ #include "qom/object.h" #include "hw/core/sysbus.h" #include "hw/intc/arm_gicv5_types.h" +#include "target/arm/cpu-qom.h" =20 /* * QEMU interface: * + * + QOM array property "cpus": CPUState pointers to each CPU + * connected to this IRS. + * + QOM array property "cpu-iaffids": array of uint32_t giving the + * IAFFID for each CPU in the "cpus" property array + * + QOM property "irsid": unique identifier for this IRS in the system + * (this is IRS_IDR0.IRSID); default is 0 + * + QOM property "spi-range": total number of SPIs in the system + * IRS (this is IRS_IDR5.SPI_RANGE); must be set + * + QOM property "spi-base": minimum SPI INTID.ID implemented on this + * IRS (this is IRS_IDR7.SPI_BASE); default is 0 + * + QOM property "spi-irs-range": number of SPI INTID.ID managed on this + * IRS (this is IRS_IDR6.SPI_IRS_RANGE); defaults to value of spi-range + * * sysbus MMIO regions (in order matching IRS_IDR0.INT_DOM encoding): * - IRS config frame for the Secure Interrupt Domain * - IRS config frame for the Non-secure Interrupt Domain @@ -47,6 +61,17 @@ struct GICv5Common { =20 /* Bits here are set for each physical interrupt domain implemented */ uint8_t implemented_domains; + + /* Properties */ + uint32_t num_cpus; + ARMCPU **cpus; + uint32_t num_cpu_iaffids; + uint32_t *cpu_iaffids; + + uint32_t irsid; + uint32_t spi_base; + uint32_t spi_irs_range; + uint32_t spi_range; }; =20 struct GICv5CommonClass { --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Unlike the GICv3, it does not deal with PPIs (private peripheral interrupts, i.e. per-CPU interrupts): in a GICv5 system those are handled entirely within the CPU interface. The inbound GPIO array is therefore a simple sequence of one GPIO per SPI that this IRS handles. Create the GPIO input array in gicv5_common_init_irqs_and_mmio(). Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5.c | 11 ++++++++++- hw/intc/arm_gicv5_common.c | 5 +++++ hw/intc/trace-events | 1 + include/hw/intc/arm_gicv5_common.h | 4 ++++ 4 files changed, 20 insertions(+), 1 deletion(-) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 64bec16bdd..cb1234b022 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -160,6 +160,15 @@ static const MemoryRegionOps config_frame_ops[NUM_GICV= 5_DOMAINS] =3D { FRAME_OP_ENTRY(el3, GICV5_ID_EL3), }; =20 +static void gicv5_set_spi(void *opaque, int irq, int level) +{ + /* These irqs are all SPIs; the INTID is irq + s->spi_base */ + GICv5Common *cs =3D ARM_GICV5_COMMON(opaque); + uint32_t spi_id =3D irq + cs->spi_base; + + trace_gicv5_spi(spi_id, level); +} + static void gicv5_reset_hold(Object *obj, ResetType type) { GICv5 *s =3D ARM_GICV5(obj); @@ -196,7 +205,7 @@ static void gicv5_realize(DeviceState *dev, Error **err= p) * NS domain. */ cs->implemented_domains =3D (1 << GICV5_ID_NS); - gicv5_common_init_irqs_and_mmio(cs, config_frame_ops); + gicv5_common_init_irqs_and_mmio(cs, gicv5_set_spi, config_frame_ops); } =20 static void gicv5_init(Object *obj) diff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c index 3448734686..b58913b970 100644 --- a/hw/intc/arm_gicv5_common.c +++ b/hw/intc/arm_gicv5_common.c @@ -38,10 +38,15 @@ static const MemoryRegionOps bad_frame_ops =3D { }; =20 void gicv5_common_init_irqs_and_mmio(GICv5Common *cs, + qemu_irq_handler handler, const MemoryRegionOps config_ops[NUM_= GICV5_DOMAINS]) { SysBusDevice *sbd =3D SYS_BUS_DEVICE(cs); =20 + if (cs->spi_irs_range) { + qdev_init_gpio_in(DEVICE(cs), handler, cs->spi_irs_range); + } + for (int i =3D 0; i < NUM_GICV5_DOMAINS; i++) { g_autofree char *memname =3D g_strdup_printf("gicv5-irs-%d", i); const MemoryRegionOps *ops =3D gicv5_domain_implemented(cs, i) ? diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 54777f6da3..0797a23c1a 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -232,6 +232,7 @@ gicv5_read(const char *domain, uint64_t offset, uint64_= t data, unsigned size) "G gicv5_badread(const char *domain, uint64_t offset, unsigned size) "GICv5 I= RS %s config frame read: offset 0x%" PRIx64 " size %u: error" gicv5_write(const char *domain, uint64_t offset, uint64_t data, unsigned s= ize) "GICv5 IRS %s config frame write: offset 0x%" PRIx64 " data 0x%" PRIx6= 4 " size %u" gicv5_badwrite(const char *domain, uint64_t offset, uint64_t data, unsigne= d size) "GICv5 IRS %s config frame write: offset 0x%" PRIx64 " data 0x%" PR= Ix64 " size %u: error" +gicv5_spi(uint32_t id, int level) "GICv5 SPI ID %u asserted at level %d" =20 # arm_gicv5_common.c gicv5_common_realize(uint32_t irsid, uint32_t num_cpus, uint32_t spi_base,= uint32_t spi_irs_range, uint32_t spi_range) "GICv5 IRS realized: IRS ID %u= , %u CPUs, SPI base %u, SPI IRS range %u, SPI range %u" diff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5= _common.h index ea01b2a1db..10276d652f 100644 --- a/include/hw/intc/arm_gicv5_common.h +++ b/include/hw/intc/arm_gicv5_common.h @@ -29,6 +29,9 @@ * IRS (this is IRS_IDR7.SPI_BASE); default is 0 * + QOM property "spi-irs-range": number of SPI INTID.ID managed on this * IRS (this is IRS_IDR6.SPI_IRS_RANGE); defaults to value of spi-range + * + unnamed GPIO inputs: the SPIs handled by this IRS + * (so GPIO input 0 is the SPI with INTID SPI_BASE, input 1 is + * SPI_BASE + 1, and so on up to SPI_BASE + SPI_IRS_RANGE - 1) * * sysbus MMIO regions (in order matching IRS_IDR0.INT_DOM encoding): * - IRS config frame for the Secure Interrupt Domain @@ -91,6 +94,7 @@ struct GICv5CommonClass { * of MemoryRegionOps structs. */ void gicv5_common_init_irqs_and_mmio(GICv5Common *cs, + qemu_irq_handler handler, const MemoryRegionOps ops[NUM_GICV5_D= OMAINS]); =20 /** --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610697; cv=none; d=zohomail.com; s=zohoarc; b=A78783E7tIjgM/PVkIcf83sPisMXi0DR2Bd9pO5UDIeswwX4EzEbJQH4Mjz8lFbb2g53tvRx8GHafp1Lg09fd4N+hByvzipmnm6+gnq0MXupZvir2XMWpfSBS/aigIS4fXYTSXfJgsaBw6P0R1ZyOMG/gTZ6UeNwEnQJZxJNNpM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610697; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=L2i2X+U/t9okZTf4XS2NhEngJ3FvRUCSx/JHhx+JgBY=; b=D1woB/7bZ0Xhu06sfx8vTmqf8f6LRAuPhLowjpp6MVESu2j3X3j1zwuHA+22gYpSSXY5Ozd3ghviaxyzyBpO0E9MuXuIrXbYFlnjnYv3PoQN15+1sKevpTreDTmyORhe/GlaqCMH5LhybRA7GS6sB+DanH5QWoLzW8A0zKzp2QA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610697523213.6744207683721; Fri, 27 Mar 2026 04:24:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65Bq-0006UR-5V; Fri, 27 Mar 2026 07:17:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65Bj-0006Pd-Cj for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:15 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65Bh-0007m3-2q for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:14 -0400 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-439b9b190easo1387289f8f.2 for ; Fri, 27 Mar 2026 04:17:12 -0700 (PDT) Received: from lanath.. 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Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5.c | 243 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 243 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index cb1234b022..4c1ec8f30a 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -7,6 +7,7 @@ */ =20 #include "qemu/osdep.h" +#include "hw/core/registerfields.h" #include "hw/intc/arm_gicv5.h" #include "qapi/error.h" #include "qemu/log.h" @@ -22,6 +23,248 @@ static const char *domain_name[] =3D { [GICV5_ID_REALM] =3D "Realm", }; =20 +REG32(IRS_IDR0, 0x0) + FIELD(IRS_IDR0, INT_DOM, 0, 2) + FIELD(IRS_IDR0, PA_RANGE, 2, 4) + FIELD(IRS_IDR0, VIRT, 6, 1) + FIELD(IRS_IDR0, ONE_N, 7, 1) + FIELD(IRS_IDR0, VIRT_ONE_N, 8, 1) + FIELD(IRS_IDR0, SETLPI, 9, 1) + FIELD(IRS_IDR0, MEC, 10, 1) + FIELD(IRS_IDR0, MPAM, 11, 1) + FIELD(IRS_IDR0, SWE, 12, 1) + FIELD(IRS_IDR0, IRSID, 16, 16) + +REG32(IRS_IDR1, 0x4) + FIELD(IRS_IDR1, PE_CNT, 0, 16) + FIELD(IRS_IDR1, IAFFID_BITS, 16, 4) + FIELD(IRS_IDR1, PRI_BITS, 20, 3) + +REG32(IRS_IDR2, 0x8) + FIELD(IRS_IDR2, ID_BITS, 0, 5) + FIELD(IRS_IDR2, LPI, 5, 1) + FIELD(IRS_IDR2, MIN_LPI_ID_BITS, 6, 4) + FIELD(IRS_IDR2, IST_LEVELS, 10, 1) + FIELD(IRS_IDR2, IST_L2SZ, 11, 3) + FIELD(IRS_IDR2, IST_MD, 14, 1) + FIELD(IRS_IDR2, ISTMD_SZ, 15, 5) + +REG32(IRS_IDR3, 0xc) + FIELD(IRS_IDR3, VMD, 0, 1) + FIELD(IRS_IDR3, VMD_SZ, 1, 4) + FIELD(IRS_IDR3, VM_ID_BITS, 5, 5) + FIELD(IRS_IDR3, VMT_LEVELS, 10, 1) + +REG32(IRS_IDR4, 0x10) + FIELD(IRS_IDR4, VPED_SZ, 0, 6) + FIELD(IRS_IDR4, VPE_ID_BITS, 6, 4) + +REG32(IRS_IDR5, 0x14) + FIELD(IRS_IDR5, SPI_RANGE, 0, 25) + +REG32(IRS_IDR6, 0x18) + FIELD(IRS_IDR6, SPI_IRS_RANGE, 0, 25) + +REG32(IRS_IDR7, 0x1c) + FIELD(IRS_IDR7, SPI_BASE, 0, 24) + +REG32(IRS_IIDR, 0x40) + FIELD(IRS_IIDR, IMPLEMENTER, 0, 12) + FIELD(IRS_IIDR, REVISION, 12, 4) + FIELD(IRS_IIDR, VARIANT, 16, 4) + FIELD(IRS_IIDR, PRODUCTID, 20, 12) + +REG32(IRS_AIDR, 0x44) + FIELD(IRS_AIDR, ARCHMINORREV, 0, 4) + FIELD(IRS_AIDR, ARCHMAJORREV, 4, 4) + FIELD(IRS_AIDR, COMPONENT, 8, 4) + +REG32(IRS_CR0, 0x80) + FIELD(IRS_CR0, IRSEN, 0, 1) + FIELD(IRS_CR0, IDLE, 1, 1) + +REG32(IRS_CR1, 0x84) + FIELD(IRS_CR1, SH, 0, 2) + FIELD(IRS_CR1, OC, 2, 2) + FIELD(IRS_CR1, IC, 4, 2) + FIELD(IRS_CR1, IST_RA, 6, 1) + FIELD(IRS_CR1, IST_WA, 7, 1) + FIELD(IRS_CR1, VMT_RA, 8, 1) + FIELD(IRS_CR1, VMT_WA, 9, 1) + FIELD(IRS_CR1, VPET_RA, 10, 1) + FIELD(IRS_CR1, VPET_WA, 11, 1) + FIELD(IRS_CR1, VMD_RA, 12, 1) + FIELD(IRS_CR1, VMD_WA, 13, 1) + FIELD(IRS_CR1, VPED_RA, 14, 1) + FIELD(IRS_CR1, VPED_WA, 15, 1) + +REG32(IRS_SYNCR, 0xc0) + FIELD(IRS_SYNCR, SYNC, 31, 1) + +REG32(IRS_SYNC_STATUSR, 0xc4) + FIELD(IRS_SYNC_STATUSR, IDLE, 0, 1) + +REG64(IRS_SPI_VMR, 0x100) + FIELD(IRS_SPI_VMR, VM_ID, 0, 16) + FIELD(IRS_SPI_VMR, VIRT, 63, 1) + +REG32(IRS_SPI_SELR, 0x108) + FIELD(IRS_SPI_SELR, ID, 0, 24) + +REG32(IRS_SPI_DOMAINR, 0x10c) + FIELD(IRS_SPI_DOMAINR, DOMAIN, 0, 2) + +REG32(IRS_SPI_RESAMPLER, 0x110) + FIELD(IRS_SPI_RESAMPLER, SPI_ID, 0, 24) + +REG32(IRS_SPI_CFGR, 0x114) + FIELD(IRS_SPI_CFGR, TM, 0, 1) + +REG32(IRS_SPI_STATUSR, 0x118) + FIELD(IRS_SPI_STATUSR, IDLE, 0, 1) + FIELD(IRS_SPI_STATUSR, V, 1, 1) + +REG32(IRS_PE_SELR, 0x140) + FIELD(IRS_PE_SELR, IAFFID, 0, 16) + +REG32(IRS_PE_STATUSR, 0x144) + FIELD(IRS_PE_STATUSR, IDLE, 0, 1) + FIELD(IRS_PE_STATUSR, V, 1, 1) + FIELD(IRS_PE_STATUSR, ONLINE, 2, 1) + +REG32(IRS_PE_CR0, 0x148) + FIELD(IRS_PE_CR0, DPS, 0, 1) + +REG64(IRS_IST_BASER, 0x180) + FIELD(IRS_IST_BASER, VALID, 0, 1) + FIELD(IRS_IST_BASER, ADDR, 6, 50) + +REG32(IRS_IST_CFGR, 0x190) + FIELD(IRS_IST_CFGR, LPI_ID_BITS, 0, 5) + FIELD(IRS_IST_CFGR, L2SZ, 5, 2) + FIELD(IRS_IST_CFGR, ISTSZ, 7, 2) + FIELD(IRS_IST_CFGR, STRUCTURE, 16, 1) + +REG32(IRS_IST_STATUSR, 0x194) + FIELD(IRS_IST_STATUSR, IDLE, 0, 1) + +REG32(IRS_MAP_L2_ISTR, 0x1c0) + FIELD(IRS_MAP_L2_ISTR, ID, 0, 24) + +REG64(IRS_VMT_BASER, 0x200) + FIELD(IRS_VMT_BASER, VALID, 0, 1) + FIELD(IRS_VMT_BASER, ADDR, 3, 53) + +REG32(IRS_VMT_CFGR, 0x210) + FIELD(IRS_VMT_CFGR, VM_ID_BITS, 0, 5) + FIELD(IRS_VMT_CFGR, STRUCTURE, 16, 1) + +REG32(IRS_VMT_STATUSR, 0x124) + FIELD(IRS_VMT_STATUSR, IDLE, 0, 1) + +REG64(IRS_VPE_SELR, 0x240) + FIELD(IRS_VPE_SELR, VM_ID, 0, 16) + FIELD(IRS_VPE_SELR, VPE_ID, 32, 16) + FIELD(IRS_VPE_SELR, S, 63, 1) + +REG64(IRS_VPE_DBR, 0x248) + FIELD(IRS_VPE_DBR, INTID, 0, 24) + FIELD(IRS_VPE_DBR, DBPM, 32, 5) + FIELD(IRS_VPE_DBR, REQ_DB, 62, 1) + FIELD(IRS_VPE_DBR, DBV, 63, 1) + +REG32(IRS_VPE_HPPIR, 0x250) + FIELD(IRS_VPE_HPPIR, ID, 0, 24) + FIELD(IRS_VPE_HPPIR, TYPE, 29, 3) + FIELD(IRS_VPE_HPPIR, HPPIV, 32, 1) + +REG32(IRS_VPE_CR0, 0x258) + FIELD(IRS_VPE_CR0, DPS, 0, 1) + +REG32(IRS_VPE_STATUSR, 0x25c) + FIELD(IRS_VPE_STATUSR, IDLE, 0, 1) + FIELD(IRS_VPE_STATUSR, V, 1, 1) + +REG64(IRS_VM_DBR, 0x280) + FIELD(IRS_VM_DBR, VPE_ID, 0, 16) + FIELD(IRS_VM_DBR, EN, 63, 1) + +REG32(IRS_VM_SELR, 0x288) + FIELD(IRS_VM_SELR, VM_ID, 0, 16) + +REG32(IRS_VM_STATUSR, 0x28c) + FIELD(IRS_VM_STATUSR, IDLE, 0, 1) + FIELD(IRS_VM_STATUSR, V, 1, 1) + +REG64(IRS_VMAP_L2_VMTR, 0x2c0) + FIELD(IRS_VMAP_L2_VMTR, VM_ID, 0, 16) + FIELD(IRS_VMAP_L2_VMTR, M, 63, 1) + +REG64(IRS_VMAP_VMR, 0x2c8) + FIELD(IRS_VMAP_VMR, VM_ID, 0, 16) + FIELD(IRS_VMAP_VMR, U, 62, 1) + FIELD(IRS_VMAP_VMR, M, 63, 1) + +REG64(IRS_VMAP_VISTR, 0x2d0) + FIELD(IRS_VMAP_VISTR, TYPE, 29, 3) + FIELD(IRS_VMAP_VISTR, VM_ID, 32, 16) + FIELD(IRS_VMAP_VISTR, U, 62, 1) + FIELD(IRS_VMAP_VISTR, M, 63, 1) + +REG64(IRS_VMAP_L2_VISTR, 0x2d8) + FIELD(IRS_VMAP_L2_VISTR, ID, 0, 24) + FIELD(IRS_VMAP_L2_VISTR, TYPE, 29, 3) + FIELD(IRS_VMAP_L2_VISTR, VM_ID, 32, 16) + FIELD(IRS_VMAP_L2_VISTR, M, 63, 1) + +REG64(IRS_VMAP_VPER, 0x2e0) + FIELD(IRS_VMAP_VPER, VPE_ID, 0, 16) + FIELD(IRS_VMAP_VPER, VM_ID, 32, 16) + FIELD(IRS_VMAP_VPER, M, 63, 1) + +REG64(IRS_SAVE_VMR, 0x300) + FIELD(IRS_SAVE_VMR, VM_ID, 0, 16) + FIELD(IRS_SAVE_VMR, Q, 62, 1) + FIELD(IRS_SAVE_VMR, S, 63, 1) + +REG32(IRS_SAVE_VM_STATUSR, 0x308) + FIELD(IRS_SAVE_VM_STATUSR, IDLE, 0, 1) + FIELD(IRS_SAVE_VM_STATUSR, Q, 1, 1) + +REG32(IRS_MEC_IDR, 0x340) + FIELD(IRS_MEC_IDR, MECIDSIZE, 0, 4) + +REG32(IRS_MEC_MECID_R, 0x344) + FIELD(IRS_MEC_MICID_R, MECID, 0, 16) + +REG32(IRS_MPAM_IDR, 0x380) + FIELD(IRS_MPAM_IDR, PARTID_MAX, 0, 16) + FIELD(IRS_MPAM_IDR, PMG_MAX, 16, 8) + FIELD(IRS_MPAM_IDR, HAS_MPAM_SP, 24, 1) + +REG32(IRS_MPAM_PARTID_R, 0x384) + FIELD(IRS_MPAM_IDR, PARTID, 0, 16) + FIELD(IRS_MPAM_IDR, PMG, 16, 8) + FIELD(IRS_MPAM_IDR, MPAM_SP, 24, 2) + FIELD(IRS_MPAM_IDR, IDLE, 31, 1) + +REG64(IRS_SWERR_STATUSR, 0x3c0) + FIELD(IRS_SWERR_STATUSR, V, 0, 1) + FIELD(IRS_SWERR_STATUSR, S0V, 1, 1) + FIELD(IRS_SWERR_STATUSR, S1V, 2, 1) + FIELD(IRS_SWERR_STATUSR, OF, 3, 1) + FIELD(IRS_SWERR_STATUSR, EC, 16, 8) + FIELD(IRS_SWERR_STATUSR, IMP_EC, 24, 8) + +REG64(IRS_SWERR_SYNDROMER0, 0x3c8) + FIELD(IRS_SWERR_SYNDROMER0, VM_ID, 0, 16) + FIELD(IRS_SWERR_SYNDROMER0, ID, 32, 24) + FIELD(IRS_SWERR_SYNDROMER0, TYPE, 60, 3) + FIELD(IRS_SWERR_SYNDROMER0, VIRTUAL, 63, 1) + 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These are all 32-bit registers. We make these fields in the GIC state struct rather than just hardcoding them in the register read function so that we can later code "do this only if X is implemented" as a test on the ID register value. Signed-off-by: Peter Maydell --- hw/intc/arm_gicv5.c | 115 +++++++++++++++++++++++++++++ include/hw/intc/arm_gicv5_common.h | 38 ++++++++++ 2 files changed, 153 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 4c1ec8f30a..250925f004 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -268,6 +268,65 @@ REG64(IRS_SWERR_SYNDROMER1, 0x3d0) static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset, uint64_t *data, MemTxAttrs attrs) { + GICv5Common *cs =3D ARM_GICV5_COMMON(s); + uint32_t v =3D 0; + + switch (offset) { + case A_IRS_IDR0: + v =3D cs->irs_idr0; + /* INT_DOM reports the domain this register is for */ + v =3D FIELD_DP32(v, IRS_IDR0, INT_DOM, domain); + if (domain !=3D GICV5_ID_REALM) { + /* MEC field RES0 except for the Realm domain */ + v &=3D ~R_IRS_IDR0_MEC_MASK; + } + if (domain =3D=3D GICV5_ID_EL3) { + /* VIRT is RES0 for EL3 domain */ + v &=3D ~R_IRS_IDR0_VIRT_MASK; + /* ...which means VIRT_ONE_N is also RES0 */ + v &=3D ~R_IRS_IDR0_VIRT_ONE_N_MASK; + } + return true; + + case A_IRS_IDR1: + *data =3D cs->irs_idr1; + return true; + + case A_IRS_IDR2: + *data =3D cs->irs_idr2; + return true; + + case A_IRS_IDR3: + /* In EL3 IDR0.VIRT is 0 so this is RES0 */ + *data =3D domain =3D=3D GICV5_ID_EL3 ? 0 : cs->irs_idr3; + return true; + + case A_IRS_IDR4: + /* In EL3 IDR0.VIRT is 0 so this is RES0 */ + *data =3D domain =3D=3D GICV5_ID_EL3 ? 0 : cs->irs_idr4; + return true; + + case A_IRS_IDR5: + *data =3D cs->irs_idr5; + return true; + + case A_IRS_IDR6: + *data =3D cs->irs_idr6; + return true; + + case A_IRS_IDR7: + *data =3D cs->irs_idr7; + return true; + + case A_IRS_IIDR: + *data =3D cs->irs_iidr; + return true; + + case A_IRS_AIDR: + *data =3D cs->irs_aidr; + return true; + } + return false; } =20 @@ -422,6 +481,60 @@ static void gicv5_reset_hold(Object *obj, ResetType ty= pe) } } =20 +static void gicv5_set_idregs(GICv5Common *cs) +{ + /* Set the ID register value fields */ + uint32_t v; + + /* + * Fields in IDR0 for optional parts of the spec that we don't + * implement are 0. + */ + v =3D 0; + /* + * We can handle physical addresses of any size, so report support + * for 56 bits of physical address space. + */ + v =3D FIELD_DP32(v, IRS_IDR0, PA_RANGE, 7); + v =3D FIELD_DP32(v, IRS_IDR0, IRSID, cs->irsid); + cs->irs_idr0 =3D v; + + v =3D 0; + v =3D FIELD_DP32(v, IRS_IDR1, PE_CNT, cs->num_cpus); + v =3D FIELD_DP32(v, IRS_IDR1, IAFFID_BITS, QEMU_GICV5_IAFFID_BITS - 1); + v =3D FIELD_DP32(v, IRS_IDR1, PRI_BITS, QEMU_GICV5_PRI_BITS - 1); + cs->irs_idr1 =3D v; + + v =3D 0; + /* We always support physical LPIs with 2-level ISTs of all sizes */ + v =3D FIELD_DP32(v, IRS_IDR2, ID_BITS, QEMU_GICV5_ID_BITS); + v =3D FIELD_DP32(v, IRS_IDR2, LPI, 1); + v =3D FIELD_DP32(v, IRS_IDR2, MIN_LPI_ID_BITS, QEMU_GICV5_MIN_LPI_ID_B= ITS); + v =3D FIELD_DP32(v, IRS_IDR2, IST_LEVELS, 1); + v =3D FIELD_DP32(v, IRS_IDR2, IST_L2SZ, 7); + /* Our impl does not need IST metadata, so ISTMD and ISTMD_SZ are 0 */ + cs->irs_idr2 =3D v; + + /* We don't implement virtualization yet, so these are zero */ + cs->irs_idr3 =3D 0; + cs->irs_idr4 =3D 0; + + /* These three have just one field each */ + cs->irs_idr5 =3D FIELD_DP32(0, IRS_IDR5, SPI_RANGE, cs->spi_range); + cs->irs_idr6 =3D FIELD_DP32(0, IRS_IDR6, SPI_IRS_RANGE, cs->spi_irs_ra= nge); + cs->irs_idr7 =3D FIELD_DP32(0, IRS_IDR7, SPI_BASE, cs->spi_base); + + v =3D 0; + v =3D FIELD_DP32(v, IRS_IIDR, IMPLEMENTER, QEMU_GICV5_IMPLEMENTER); + v =3D FIELD_DP32(v, IRS_IIDR, REVISION, QEMU_GICV5_REVISION); + v =3D FIELD_DP32(v, IRS_IIDR, VARIANT, QEMU_GICV5_VARIANT); + v =3D FIELD_DP32(v, IRS_IIDR, PRODUCTID, QEMU_GICV5_PRODUCTID); + cs->irs_iidr =3D v; + + /* This is a GICv5.0 IRS, so all fields are zero */ + cs->irs_aidr =3D 0; +} + static void gicv5_realize(DeviceState *dev, Error **errp) { GICv5Common *cs =3D ARM_GICV5_COMMON(dev); @@ -448,6 +561,8 @@ static void gicv5_realize(DeviceState *dev, Error **err= p) * NS domain. */ cs->implemented_domains =3D (1 << GICV5_ID_NS); + + gicv5_set_idregs(cs); gicv5_common_init_irqs_and_mmio(cs, gicv5_set_spi, config_frame_ops); } =20 diff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5= _common.h index 10276d652f..906870e49f 100644 --- a/include/hw/intc/arm_gicv5_common.h +++ b/include/hw/intc/arm_gicv5_common.h @@ -65,6 +65,18 @@ struct GICv5Common { /* Bits here are set for each physical interrupt domain implemented */ uint8_t implemented_domains; =20 + /* ID register values: set at realize, constant thereafter */ + uint32_t irs_idr0; + uint32_t irs_idr1; + uint32_t irs_idr2; + uint32_t irs_idr3; + uint32_t irs_idr4; + uint32_t irs_idr5; + uint32_t irs_idr6; + uint32_t irs_idr7; + uint32_t irs_iidr; + uint32_t irs_aidr; + /* Properties */ uint32_t num_cpus; ARMCPU **cpus; @@ -84,6 +96,32 @@ struct GICv5CommonClass { =20 #define IRS_CONFIG_FRAME_SIZE 0x10000 =20 +/* + * The architecture allows a GICv5 to implement less than the full + * width for various ID fields. QEMU's implementation always supports + * the full width of these fields. These constants define our + * implementation's limits. + */ + +/* Number of INTID.ID bits we support */ +#define QEMU_GICV5_ID_BITS 24 +/* Min LPI_ID_BITS supported */ +#define QEMU_GICV5_MIN_LPI_ID_BITS 14 +/* IAFFID bits supported */ +#define QEMU_GICV5_IAFFID_BITS 16 +/* Number of priority bits supported in the IRS */ +#define QEMU_GICV5_PRI_BITS 5 + +/* + * There are no TRMs currently published for hardware implementations + * of GICv5 that we might identify ourselves as. Instead, we borrow + * the Arm Implementer code and pick an arbitrary product ID (ASCII "Q") + */ +#define QEMU_GICV5_IMPLEMENTER 0x43b +#define QEMU_GICV5_PRODUCTID 0x51 +#define QEMU_GICV5_REVISION 0 +#define QEMU_GICV5_VARIANT 0 + /** * gicv5_common_init_irqs_and_mmio: Create IRQs and MMIO regions for the G= ICv5 * @s: GIC object --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610548; cv=none; d=zohomail.com; s=zohoarc; b=OtJpuRrfBGXnlY3WlTH4I0GKKC6Mk8DpJmXgMVKYBTnP9yTedCqzszLMVKentXKSoTiNIDSZW8uK+IfD6t2/iBJAPEkP/RhFsKh66aTvyGnq4gmAx/GnBkiqagIxpDEM+h+1QjuIjTjSA/yHgn1vxYtTr3MwiJ5wnpRZAYzhSWo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610548; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=sPzosEGuwhk6i6RHzymnZDkK3KDFX6eGqZn4vO6SwyY=; b=D9nn+pvXqtIPXkCmxvxDny9/Hp7/3qNCgZgbgneeduTmnZEIvtHWW8c0uZa4GidagElV9ACIIdIKqFg7ccZ/dPKMKN7AdcB8vcJ1W/CsqjLo294+Q+K1yK4R//+f4/pdt0+pcpG4nmlrh2/a+OJXz6Q1VAL5rlpaTLCqnCX9WJw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610548267461.43959291297665; Fri, 27 Mar 2026 04:22:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65Bp-0006Te-9o; Fri, 27 Mar 2026 07:17:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65Bk-0006Q6-Ml for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:17 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65Bi-0007qB-Eh for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:15 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-48700b1ba53so18914975e9.1 for ; Fri, 27 Mar 2026 04:17:13 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610233; x=1775215033; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sPzosEGuwhk6i6RHzymnZDkK3KDFX6eGqZn4vO6SwyY=; b=mz0jMaK6KG6dpc+eABj71fbBfcWDfmkura4CKURzdMKBr7TiWcV/ROxzuTlzOLiGQw fslSCafzNIFoCJbEQ6o80jI1g557Isn6WL/8Lg/ZMDXFWPtlGS83nk9NSSSRmak6e+5F BCwnxLzBh+ZmMVaZdQrKexEKiFeF7VLRbllLegKR64JQ0fNS6r9mDhhotrHxgijyNPvz UXl2VhgiOqfD78L1q88e4ubf0i2NJfrt4E/ldsJkgtbiHhN+/CwOW0rwA+XHKX5tfJgR 9RfgPGe1TmbDfT/bq8rkG4iMZkzuRh4GBzx251aYecaPLqG7mcnWrCON2q4CwCVDdljd qiFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610233; x=1775215033; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=sPzosEGuwhk6i6RHzymnZDkK3KDFX6eGqZn4vO6SwyY=; b=NS9dX7wVyBYr4QbY7AkyVEml11N+PMbH7+roEHE8hjQHdlKLdzquZG6nlvjGNZgDky li/17MDau/Gn+cmFeEsj3ARSDe6mjHUQv6rML3FsNxzqQT++8oqUiXGqhQtqYlkWmyGo fd7BSPh+a9/dqSSocfkiL78fvXYnf/zXNZT8Z/4a2wwHf458MpUUT/an/Oftnko8hJjm /vblrBPrF5zCVKPF+XfO63jdbR8FdcMqMVDDS6TfZY6Y6OSEhkNSJQ8t2CrdvLIcaxwW RXnBmabFZOklIscq2pOAcE/uxadLxTsFO4Chi27pdpi8CTvGIyn/fADwM6iB9pfKc5G6 H4Ag== X-Forwarded-Encrypted: i=1; AJvYcCW3/7pTd0JpxvUtkN+by4gVFZoRioIlKvxFYRp56DrNxj7Dg/gqYIRpDYTP1cvqqhhZt/CqZCr+YPxE@nongnu.org X-Gm-Message-State: AOJu0Yx8reol19LDJW44rnF6EWqAHjsV06vgdUFcIH5zYVrOXcvNXiHN PcFFQ+4w9GfRKnuia71gKfQ1q9ZH36aCjbvDsuKy5zNXFswLPQQLHjpPQXEFz+7lJBvQkgXmF3B PBJMjH8o= X-Gm-Gg: ATEYQzybrDpE2iG5DF9d6ckGsxUNHs5xlE8CLd7iMCfb4k6noeqVEpwW7mMqw5hkYz2 DPkdialqG2ugP8qIL7Ks548i4N+jcHto+bK47cxrc3v0s0plp8kAaRhZMvAb4IgYCuTb6Nv2qQz 0o54OPTzDH3pe50EBD1O0LJsQaUUCLQUi1WYa3yF5JkP42166tDnbNuy07+fEVoQc+6G2rSExRD pyGl+2Cmv6Rbfj3zx4ZCJ/1YOEHPxLMRmP2dh1rb1ryS9mg4FCKPmL/efmmTc+dDMBluDLJDPmI OfMziWQAx3NOT2FUGLV/k3dtj5sJeQ8RYfJA1n0K30T2HDvucUoGAx5Y+vTdcrncAqKK6bCd0qm 4C8dP7rdNW0rgSTMI1o7ZCqmmkUx7b2RVpWLjGeqbQZtsBlqzIcOz8y4gCTbySAAwHjB+ycQVTt f+kvokH+2Bhfgc2nTzC2oEc90IbrAN9NYM+6VynZMHRH1DkRhgXjQzyMiGj0d6XhEzNd0NZhOSe gE3S2K6supe1zh3LxsLt/rHvA5xhok= X-Received: by 2002:a05:600c:8b4b:b0:485:3fe6:21f5 with SMTP id 5b1f17b1804b1-48727f0e5f8mr31326645e9.10.1774610232749; Fri, 27 Mar 2026 04:17:12 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 11/65] hw/intc/arm_gicv5: Add link property for MemoryRegion for DMA Date: Fri, 27 Mar 2026 11:16:06 +0000 Message-ID: <20260327111700.795099-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610550662154100 Content-Type: text/plain; charset="utf-8" The GICv5 IRS keeps data structures in system memory. (Notably, it stores per-interrupt configuration information like the interrupt priority and its active and pending state in an in-memory data structure.) Add a link property so that the board or SoC can wire up a MemoryRegion that we will do DMA to. We name this property "sysmem" to match the GICv3's equivalent property. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5_common.c | 8 ++++++++ include/hw/intc/arm_gicv5_common.h | 4 ++++ 2 files changed, 12 insertions(+) diff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c index b58913b970..29cc96917e 100644 --- a/hw/intc/arm_gicv5_common.c +++ b/hw/intc/arm_gicv5_common.c @@ -122,6 +122,12 @@ static void gicv5_common_realize(DeviceState *dev, Err= or **errp) cs->spi_base, cs->spi_irs_range, cs->spi_range); return; } + if (!cs->dma) { + error_setg(errp, "sysmem link property not set"); + return; + } + + address_space_init(&cs->dma_as, cs->dma, "gicv5-sysmem"); =20 trace_gicv5_common_realize(cs->irsid, cs->num_cpus, cs->spi_base, cs->spi_irs_range, cs->spi_ra= nge); @@ -137,6 +143,8 @@ static const Property arm_gicv5_common_properties[] =3D= { DEFINE_PROP_UINT32("spi-base", GICv5Common, spi_base, 0), DEFINE_PROP_UINT32("spi-irs-range", GICv5Common, spi_irs_range, GICV5_SPI_IRS_RANGE_NOT_SET), + DEFINE_PROP_LINK("sysmem", GICv5Common, dma, TYPE_MEMORY_REGION, + MemoryRegion *), }; =20 static void gicv5_common_class_init(ObjectClass *oc, const void *data) diff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5= _common.h index 906870e49f..900af53b0f 100644 --- a/include/hw/intc/arm_gicv5_common.h +++ b/include/hw/intc/arm_gicv5_common.h @@ -83,6 +83,10 @@ struct GICv5Common { uint32_t num_cpu_iaffids; uint32_t *cpu_iaffids; =20 + /* MemoryRegion and AS to DMA to/from for in-memory data structures */ + MemoryRegion *dma; + AddressSpace dma_as; + uint32_t irsid; uint32_t spi_base; uint32_t spi_irs_range; --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610375; cv=none; d=zohomail.com; s=zohoarc; b=ao6jpLfx2BZjJSezVLD7QTYxFrJUCgtH+588z7Ahq2xrmIHQgAl5e+YmHKHVjK/Pmk5K1XFv92oEuosMMS25U5SC2aDTXmomMh33QlaDH+0Al0bN4Btk0kK1+hcTsBzWiXKJm0Dv4/Qp7bHjCmb0V9ON+BWdNh3S3LmKlfvlRms= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610375; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=eAtjWu5Nao9N8oE0IDX5NSQrIVlRkYa+wCz3k4lXaJM=; b=cgk9jLdUCJbSsEm1UQNIcNi/U5VQfrV/BWITm2FXjcTg2e3HNZ1yZ58h3lGpzpp9y+UMWAmCz6Mp/6aCONJQphDxZceiVoDl5A6vYAxAGrw1q4zbNx6AeNYs8W4arhx7TdW3EdVTXxNgTQYJEqrbV5ClcKBn0JLzIDSa93NPJG0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610375629117.24405131370497; Fri, 27 Mar 2026 04:19:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65Bw-0006eF-Q1; Fri, 27 Mar 2026 07:17:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65Bn-0006RX-46 for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:19 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65Bj-0007r6-M9 for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:17 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-43b527ac5d0so1082577f8f.2 for ; Fri, 27 Mar 2026 04:17:15 -0700 (PDT) Received: from lanath.. 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For the GICv5, we don't yet implement KVM support, so the KVM-enabled codepath is always an error. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5_common.c | 12 ++++++++++++ include/hw/intc/arm_gicv5_common.h | 10 ++++++++++ 2 files changed, 22 insertions(+) diff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c index 29cc96917e..7f15e3c7c8 100644 --- a/hw/intc/arm_gicv5_common.c +++ b/hw/intc/arm_gicv5_common.c @@ -11,6 +11,8 @@ #include "hw/core/qdev-properties.h" #include "qapi/error.h" #include "trace.h" +#include "qemu/error-report.h" +#include "system/kvm.h" =20 OBJECT_DEFINE_ABSTRACT_TYPE(GICv5Common, gicv5_common, ARM_GICV5_COMMON, S= YS_BUS_DEVICE) =20 @@ -157,3 +159,13 @@ static void gicv5_common_class_init(ObjectClass *oc, c= onst void *data) dc->realize =3D gicv5_common_realize; device_class_set_props(dc, arm_gicv5_common_properties); } + +const char *gicv5_class_name(void) +{ + /* When we implement KVM GICv5 we might return "kvm-arm-gicv5" here. */ + if (kvm_enabled()) { + error_report("Userspace GICv5 is not supported with KVM"); + exit(1); + } + return "arm-gicv5"; +} diff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5= _common.h index 900af53b0f..88e1b4d73d 100644 --- a/include/hw/intc/arm_gicv5_common.h +++ b/include/hw/intc/arm_gicv5_common.h @@ -149,4 +149,14 @@ static inline bool gicv5_domain_implemented(GICv5Commo= n *cs, GICv5Domain domain) return cs->implemented_domains & (1 << domain); } =20 +/** + * gicv5_class_name + * + * Return name of GICv5 class to use depending on whether KVM acceleration= is + * in use. May throw an error if the chosen implementation is not availabl= e. + * + * Returns: class name to use + */ +const char *gicv5_class_name(void); + #endif --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610397; cv=none; d=zohomail.com; s=zohoarc; b=dP71SCssktpiYTQTmSlUjThx1rWQWS3IdJVcD0gLtgoTJUMapZagJL7gf2Xue04K9KBEkzLUqE7Z+okGojbyD1c9IYKWQLDB25VfdEeRoH+5Dr60t15aJdWRrHJBEJzAgtPzkMyh5vRpIMnjxo8y52HD3n8TnoT2zK7SuQfhI7Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610397; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=0hk6a1v8L3spC6OyBMcpBGHvcslrItUrS5/6IvS68Vw=; b=afaM950NcGdSTmWquFa4qSYB7J7izG4RGV2WJMJfQEh8mHL8q4JwtFvPB2lHlUuO0+P0/V33+03LaKuBw5DHOg2nrRByJenRH1yZC+ut3A8R4Bo8bZtxFvgUPW+0a5PqJ7ExfPjxOi6wQHr91J7QB2c3h/wMn8SdA5VpAnBeqlM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610397858810.472305479074; Fri, 27 Mar 2026 04:19:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65Bw-0006eN-QM; Fri, 27 Mar 2026 07:17:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65Bn-0006Rb-5J for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:19 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65Bk-0007rw-6E for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:17 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-486ff3a0fc1so19560845e9.2 for ; Fri, 27 Mar 2026 04:17:15 -0700 (PDT) Received: from lanath.. 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Add defines for them. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- include/hw/intc/arm_gicv5_types.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/include/hw/intc/arm_gicv5_types.h b/include/hw/intc/arm_gicv5_= types.h index 49dc1d6e95..7d23752ece 100644 --- a/include/hw/intc/arm_gicv5_types.h +++ b/include/hw/intc/arm_gicv5_types.h @@ -25,4 +25,24 @@ typedef enum GICv5Domain { =20 #define NUM_GICV5_DOMAINS 4 =20 +/* Architected GICv5 PPIs (as listed in R_XDVCM) */ +#define GICV5_PPI_S_DB_PPI 0 +#define GICV5_PPI_RL_DB_PPI 1 +#define GICV5_PPI_NS_DB_PPI 2 +#define GICV5_PPI_SW_PPI 3 +#define GICV5_PPI_HACDBSIRQ 15 +#define GICV5_PPI_CNTHVS 19 +#define GICV5_PPI_CNTHPS 20 +#define GICV5_PPI_PMBIRQ 21 +#define GICV5_PPI_COMMIRQ 22 +#define GICV5_PPI_PMUIRQ 23 +#define GICV5_PPI_CTIIRQ 24 +#define GICV5_PPI_GICMNT 25 +#define GICV5_PPI_CNTHP 26 +#define GICV5_PPI_CNTV 27 +#define GICV5_PPI_CNTHV 28 +#define GICV5_PPI_CNTPS 29 +#define GICV5_PPI_CNTP 30 +#define GICV5_PPI_TRBIRQ 31 + #endif --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610837; cv=none; d=zohomail.com; s=zohoarc; b=EZg5CqhK4BGuvWlr4a1ay5hAZ90vA31k3NgJlg8iTx5Q1+fu++IINft2nTJO4UeNGDtW4tlugYbVMZ9J7Q6yBqXmbCjCc0obO2B/X1kcossAAPCTVHmaOBUAB+WSoPGW3SOoBp/8HJRzTDBCgILCBcPJdvfhLHqqcuerUx6MvM8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610837; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=je7B5zDvIcs1KYXJyPR11CmwTDqna8zeEJTkuZaNBM8=; b=BHxGXwktJ2qOf7jWObdFJIKydn7yETA/8ppPFmO1wsX8DJ4arQvjDMTn1qTFPrkd74WXr9U1GKPpjg/I3dxrQGLaEoJaasXPsv/yPuCerbsOKicw1ZVVOaX/skq0CCBuBcwU9iMpfwFg89FDpAAvYLIK9PyNZbSIbbCW3GC2zSE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610836997156.48479410015477; Fri, 27 Mar 2026 04:27:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65Bs-0006XM-5p; Fri, 27 Mar 2026 07:17:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65Bo-0006SS-Bi for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:20 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65Bl-0007sK-Bj for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:19 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-439bc14dcf4so2271077f8f.1 for ; Fri, 27 Mar 2026 04:17:16 -0700 (PDT) Received: from lanath.. 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Add the initial source files for the GICv5 CPU interface, with initial content implementing just the two GSB GIC barrier instructions, which are no-ops for QEMU. Since we will not initially implement virtualization or the "legacy GICv3" interface that can be provided to a VM guest, we don't have the ICH_VCTLR_EL2 register and do not need to implement an accessfn for the "trap if at EL1 and EL2 enabled and legacy GICv3 is enabled" handling. We will come back and add this later as part of the legacy-GICv3 code. (The GICv3 has a similar architecture with part of the GIC being in the CPU and part external; for QEMU we implemented the CPU interface in hw/intc/, but in retrospect I think this was something of a design mistake, and for GICv5 I am going to stick a bit closer to how the hardware architecture splits things up; hence this code is in target/arm.) Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- target/arm/cpu-features.h | 6 +++++ target/arm/helper.c | 1 + target/arm/internals.h | 3 +++ target/arm/tcg/gicv5-cpuif.c | 43 ++++++++++++++++++++++++++++++++++++ target/arm/tcg/meson.build | 1 + 5 files changed, 54 insertions(+) create mode 100644 target/arm/tcg/gicv5-cpuif.c diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index b683c9551a..e391b394ba 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -280,6 +280,7 @@ FIELD(ID_AA64PFR1, PFAR, 60, 4) FIELD(ID_AA64PFR2, MTEPERM, 0, 4) FIELD(ID_AA64PFR2, MTESTOREONLY, 4, 4) FIELD(ID_AA64PFR2, MTEFAR, 8, 4) +FIELD(ID_AA64PFR2, GCIE, 12, 4) FIELD(ID_AA64PFR2, FPMR, 32, 4) =20 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) @@ -1159,6 +1160,11 @@ static inline bool isar_feature_aa64_gcs(const ARMIS= ARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64PFR1, GCS) !=3D 0; } =20 +static inline bool isar_feature_aa64_gcie(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64PFR2, GCIE) !=3D 0; +} + static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) { return FIELD_SEX64_IDREG(id, ID_AA64MMFR0, TGRAN4) >=3D 1; diff --git a/target/arm/helper.c b/target/arm/helper.c index 7389f2988c..8faca360fc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6310,6 +6310,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (tcg_enabled()) { define_tlb_insn_regs(cpu); define_at_insn_regs(cpu); + define_gicv5_cpuif_regs(cpu); } #endif =20 diff --git a/target/arm/internals.h b/target/arm/internals.h index 8ec2750847..9bde58cf00 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1797,6 +1797,9 @@ void define_pm_cpregs(ARMCPU *cpu); /* Add the cpreg definitions for GCS cpregs */ void define_gcs_cpregs(ARMCPU *cpu); =20 +/* Add the cpreg definitions for the GICv5 CPU interface */ +void define_gicv5_cpuif_regs(ARMCPU *cpu); + /* Effective value of MDCR_EL2 */ static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env) { diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c new file mode 100644 index 0000000000..7392a98c49 --- /dev/null +++ b/target/arm/tcg/gicv5-cpuif.c @@ -0,0 +1,43 @@ +/* + * GICv5 CPU interface + * + * Copyright (c) 2025 Linaro Limited + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "cpregs.h" + +static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { + /* + * Barrier: wait until the effects of a cpuif system register + * write have definitely made it to the IRS (and will thus show up + * in cpuif reads from the IRS by this or other CPUs and in the + * status of IRQ, FIQ etc). For QEMU we do all interaction with + * the IRS synchronously, so we can make this a nop. + */ + { .name =3D "GSB_SYS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NOP, + }, + /* + * Barrier: wait until the effects of acknowledging an interrupt + * (via GICR CDIA or GICR CDNMIA) are visible, including the + * effect on the {IRQ,FIQ,vIRQ,vFIQ} pending state. This is a + * weaker version of GSB SYS. Again, for QEMU this is a nop. + */ + { .name =3D "GSB_ACK", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 0, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NOP, + }, +}; + +void define_gicv5_cpuif_regs(ARMCPU *cpu) +{ + if (cpu_isar_feature(aa64_gcie, cpu)) { + define_arm_cp_regs(cpu, gicv5_cpuif_reginfo); + } +} diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 5f59156055..a67911f8dc 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -62,6 +62,7 @@ arm_common_ss.add(files( arm_common_system_ss.add(files( 'cpregs-at.c', 'debug.c', + 'gicv5-cpuif.c', 'hflags.c', 'neon_helper.c', 'psci.c', --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610509; cv=none; d=zohomail.com; s=zohoarc; b=I9V4786XyD/4nti9XTgJq/O/bFfLmO7bKJULPvn5qYuPaRjd1SIIFimW1i3L8SktvKEpkwiPYNPmzwl5mgwiX3MR4EmU0bAkaK75Z5nDIP0NkaFYTgOxcJgngI6C+PR4e5v7JP+ZU4PnoPa4Dp4gxdE3IODNK1u2utXSJHi1aL8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610509; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=GBC/rL6SP5hiYwiIrNz8t3Gc0wlQxRngYUrU09KceNM=; b=keFn/0H3IGqUU39TbqyeWw0egSR09/PIKfnoayapQHmHz/iObMVW1dBS4UBl6uhWntYSAESHJwjpgiiz0TnZtmlMg2h3CH3HVx4AA0NaI7Qyl33vT1hmLGRytfY6f8IaCh/1mkEBi55PvlAxZUhXQo/Hixu9ghl2BLeLH1DgxPc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610509774208.20860874655807; Fri, 27 Mar 2026 04:21:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65Bq-0006Uj-Cs; Fri, 27 Mar 2026 07:17:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65Bo-0006T1-Mv for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:20 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65Bm-0007tW-9N for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:20 -0400 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-43b87970468so1944320f8f.3 for ; Fri, 27 Mar 2026 04:17:17 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610236; x=1775215036; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GBC/rL6SP5hiYwiIrNz8t3Gc0wlQxRngYUrU09KceNM=; b=AdgUgXPYMvoY+y+GmKrcLV+kumWGQBQkXPdnSkgtFw8RoIJ3e1yYN0sckLCYQ4LCEI k5neLOl2Y0QTV6E17DINdwYz/DPyAyfNmmGViIH81wKc+Bvg1uNXWRveS6YYMrZ6TSGb ITqBNU5N5lgx3IiUxhq+bqWd/RfvmVZei+mM0is1SFqTMEJeMMcc9P984jMe71VMkZna DXKvSnuq/Ir+aeMV0IaJGHGgmMwyn1N2eW2tQJOjYYAd8GyX81MZFKQJ+YZTHKX+IGlE vfZtziPsQeveG6ZYR9xDMPgz1Nh/LdL8ZDu2M/xGH5DsLnTBcGCGEX/WQkDAOL7JJSlv T9/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610236; x=1775215036; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=GBC/rL6SP5hiYwiIrNz8t3Gc0wlQxRngYUrU09KceNM=; b=E1zvgP1/bEf+UHIasMN5KoAnHD1qrXCIDggOyOrX8aiuYHiJxxTlUdlyYp433MSxbD SqZwW19TPjsz5fE02hb8T8p+SSNax9KjeSm86qr/nGR5iT7sxmH1uQEjR3fZkzJUk4ka 2QMF96avOkGBkx69u/sydhFle6RPLN1JtoQQPt98E3xQXxGhSGVh+86H5PNQjWC8+RUo njlsaujadL1/OvdO4YY5TRGj1B87sHQk+taboAbEhZ3jUTvYSqFL7ioPIICQytm3mptH jbjlbNnkp+iL+0PLJGR6YAYPwURQqr96GZpzqjkv9oXteLFphvOJfU3K0LwFY+9GC/fA j53g== X-Forwarded-Encrypted: i=1; AJvYcCVLQ6c24kABqULpuJP8yrW6IybMpQRrlG1o3e18uyuNN7A2bTd3xLBgI2+V6vOGXiqMbQeAqBfVY6qf@nongnu.org X-Gm-Message-State: AOJu0Yzzx155KQmQKdWXf4QMjt1IdMC8PFiqKMQ0KRRSdtKDTAIDfJq7 9duo+PMPsd9iC60HowJBEb56/3Xc9mKQHc2zdzCRD4YEIE3C5UR+gMY++R3uMvt3Ko0= X-Gm-Gg: ATEYQzxGyNTzk6vFMyq8cpxYqiebbgDsVTsD7JAsh+URQhKgUa9bL34BDHfm12/uL/F Q0Tvwf38lfNkOIkDp+IkM7ndiLV4WNyehO0KYa7BarvNq2VW/SEBa9lvyZVMXVYKe1OwcO21Q6E Do4t3b7k807BKVyIOMluB6VRRdgyrptWY7A4dAG6eZrgBXd9pjDxbRHQiHIk1G9Hjn/wAHXzaYv bNZW23dSiceR1ixLaBh/8NgoC1RUI3UmBHUAIJt2QVqaOcuxEn9Q+gXOTfOEGfHR/Ls/cQJqDrT qmoQjYJ9KYirl1NBTjcVl+HQlaI+S6yS5nTvulPh8nhcsySjwwx6j5eieccueOj9Hm0WRI4A5UB BRWtjGdoSWVcb5TPKTuErlvhg13WF01r/rQjgK+pE8IEukDcD3T5fxlcegIgXj1TmWmu2Y+anfj rC7WcerE7rDdWbkyI0ameZhoy/mkNqBCUc60H/gAJ8YNAT54hzx8/TzcgZ34P+/14qJVFeZP7us 6CDgljDzDlQUi93d03x3qFpRWEk/Yk= X-Received: by 2002:a05:6000:144f:b0:43b:998c:d82b with SMTP id ffacd0b85a97d-43b9ea34871mr3246050f8f.19.1774610236192; Fri, 27 Mar 2026 04:17:16 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 15/65] target/arm: Set up pointer to GICv5 in each CPU Date: Fri, 27 Mar 2026 11:16:10 +0000 Message-ID: <20260327111700.795099-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610511041158500 Content-Type: text/plain; charset="utf-8" The qdev link property array gives the IRS a pointer to each CPU that is connected to it, but the CPU also needs a pointer to the IRS so that it can issue commands. Set this up in a similar way to how we do it for the GICv3: have the GIC's realize function call gicv5_set_gicv5state() to set a pointer in the CPUARMState. The CPU will only allow this link to be made if it actually implements the GICv5 CPU interface; it will be the responsibility of the board code to configure the CPU to have a GICv5 cpuif if it wants to connect a GICv5 to it. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5_common.c | 9 +++++++++ include/hw/intc/arm_gicv5_stream.h | 32 ++++++++++++++++++++++++++++++ target/arm/cpu.c | 16 +++++++++++++++ target/arm/cpu.h | 2 ++ 4 files changed, 59 insertions(+) create mode 100644 include/hw/intc/arm_gicv5_stream.h diff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c index 7f15e3c7c8..54d75db014 100644 --- a/hw/intc/arm_gicv5_common.c +++ b/hw/intc/arm_gicv5_common.c @@ -8,6 +8,7 @@ =20 #include "qemu/osdep.h" #include "hw/intc/arm_gicv5_common.h" +#include "hw/intc/arm_gicv5_stream.h" #include "hw/core/qdev-properties.h" #include "qapi/error.h" #include "trace.h" @@ -129,6 +130,14 @@ static void gicv5_common_realize(DeviceState *dev, Err= or **errp) return; } =20 + for (int i =3D 0; i < cs->num_cpus; i++) { + if (!gicv5_set_gicv5state(cs->cpus[i], cs)) { + error_setg(errp, + "CPU %d does not implement GICv5 CPU interface", i); + return; + } + } + address_space_init(&cs->dma_as, cs->dma, "gicv5-sysmem"); =20 trace_gicv5_common_realize(cs->irsid, cs->num_cpus, diff --git a/include/hw/intc/arm_gicv5_stream.h b/include/hw/intc/arm_gicv5= _stream.h new file mode 100644 index 0000000000..7257ddde90 --- /dev/null +++ b/include/hw/intc/arm_gicv5_stream.h @@ -0,0 +1,32 @@ +/* + * Interface between GICv5 CPU interface and GICv5 IRS + * Loosely modelled on the GICv5 Stream Protocol interface documented + * in the GICv5 specification. + * + * Copyright (c) 2025 Linaro Limited + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_INTC_ARM_GICV5_STREAM_H +#define HW_INTC_ARM_GICV5_STREAM_H + +#include "target/arm/cpu-qom.h" + +typedef struct GICv5Common GICv5Common; + +/** + * gicv5_set_gicv5state + * @cpu: CPU object to tell about its IRS + * @cs: the GIC IRS it is connected to + * + * Set the CPU object's GICv5 pointer to point to this GIC IRS. The + * IRS must call this when it is realized, for each CPU it is + * connected to. + * + * Returns true on success, false if the CPU doesn't implement the + * GICv5 CPU interface. + */ +bool gicv5_set_gicv5state(ARMCPU *cpu, GICv5Common *cs); + +#endif diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ccc47c8a9a..4044bce5b6 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -41,6 +41,7 @@ #include "hw/core/boards.h" #ifdef CONFIG_TCG #include "hw/intc/armv7m_nvic.h" +#include "hw/intc/arm_gicv5_stream.h" #endif /* CONFIG_TCG */ #endif /* !CONFIG_USER_ONLY */ #include "system/tcg.h" @@ -1085,6 +1086,21 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f= , int flags) } } =20 +#ifndef CONFIG_USER_ONLY +bool gicv5_set_gicv5state(ARMCPU *cpu, GICv5Common *cs) +{ + /* + * Set this CPU's gicv5state pointer to point to the GIC that we are + * connected to. + */ + if (!cpu_isar_feature(aa64_gcie, cpu)) { + return false; + } + cpu->env.gicv5state =3D cs; + return true; +} +#endif + uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz) { uint32_t Aff1 =3D idx / clustersz; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 657ff4ab20..16de0ebfa8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -812,6 +812,8 @@ typedef struct CPUArchState { const struct arm_boot_info *boot_info; /* Store GICv3CPUState to access from this struct */ void *gicv3state; + /* Similarly, for a GICv5Common */ + void *gicv5state; #else /* CONFIG_USER_ONLY */ /* For usermode syscall translation. */ bool eabi; --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610759; cv=none; d=zohomail.com; s=zohoarc; b=PTdTCfZcE8NxegOc7rMFofKyRuImfecyYh7GRRCzMMJJBkX/+yCx2X7yFRPQszntBl9Y4e7ti+uzAjgjLFSv3838io1kFPJEV96khXMwKyHQPNFLcQWOQ0IH2m62TVf8JTngl6L1FBA3METeOVQhYgF43/JXr64KbNrB52sUDpg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610759; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Bo1tMGJjf8413y4VWnCIE2KG4+bnE/ZHqBVrYM1R3f8=; b=kxy6AE2SUkj77uwO+i0To6FCkHyCyZQECE3s6PGKjm4fLe9kzD7pgYffODogt0ds49oqHUbAxPKR/QR+FHOyp5pzKqA+gcyJOZtryrNiUVKletsoSoxpJQDhIPloxKnCU1mSsEe4dgEJ//BBMPc591tXd7C59ZbXyWnWyatibqA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610759922451.1628584070693; Fri, 27 Mar 2026 04:25:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65Bs-0006Y9-La; Fri, 27 Mar 2026 07:17:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65Bp-0006Th-BG for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:21 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65Bm-0007tz-TG for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:21 -0400 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-43b41b545d9so2036496f8f.2 for ; Fri, 27 Mar 2026 04:17:18 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610237; x=1775215037; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Bo1tMGJjf8413y4VWnCIE2KG4+bnE/ZHqBVrYM1R3f8=; b=MDXy222SaSW1Cb3UqWQ5rcghnYh5QMkTGQn79/3WxAtmUt01K6HILkXsY4ht6pw7GC f04m6ulQisNGczXB7/EulGqGCjUtuzu3YKJMmac/nYBfsNA6KfrH4o4KTnh2pG9Xpen2 LwecPOVzQOFM16W9Vy6U1uMd0ILFAD/SngoKVPhsGNFViiORU8Ny+PGlQD5X1Ep/QwAf YQlX4Zt2L93emM6+MkxbdTZMAWhwDe4S8thFX9NnuIqLieeujkD8vGOIPTdD+atXo+5f Qmhs0hTMDOxwTnV4n9ETKyMF+7a/9I2L2iHU/qL/WzdrqNdsLOxrJgogCr5IQF3lOO6O s2nQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610237; x=1775215037; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Bo1tMGJjf8413y4VWnCIE2KG4+bnE/ZHqBVrYM1R3f8=; b=WxF9PEvBpYyeK7xwZXdN8Qp3ScsyjVshKIvFGJSXVE6+ZkoPThdc9RTCHGO3QdP+Cw 0yErmAmlmryeUeKYLlWNX1Xo/71jgk1f3MfoWkoyCgMRGhrk7qm795bbm0VCQ7k1bEtQ C09S7q7+Klq6hYJjs/P1EF1TH5QeCjMEjLQ520VXRcBD69NbDCWAUU+FOqPvuvpidUYV G025t2/jKY3k1DHu3PDbTKaGCr/0PFUqRX9pgw7A46bZVCA2HU6ZoXR6F5YU51fd8t/S k+7DJ9M3LuI1QDgDoJSYTkHFBy1W/79gSY/9DnCuLCKaggloMm9qiyBu2Gg9Xg2BZE3u 7/4A== X-Forwarded-Encrypted: i=1; AJvYcCWJVn5No8L/6E9c+tLmZj+LoVXXWSl+KZLJbRPdro/ZtJdFu/aDRjNyZqfafLFpVvytFiv11wIenSqU@nongnu.org X-Gm-Message-State: AOJu0Yx4nBBV87zdHPW5qblEMW+15sDPYdV4JqfNno1C2F+Q4ANTrdHR cbatUxWvhcHYkDOptNQzi8Upmb8MqCQ7sxaCw8PCJvLGFgWLNkeMb/DxGLS0MEnvu9JPgh2BmNL HasteibU= X-Gm-Gg: ATEYQzz3lgpIT/kfuuMlRbnJ910/1TIMpKEIwLlaCZuelOVFnwfWu8eQ09OMKvtAlmG sXbXM2e9XKEfdC4UQMI5NXj5jXPTDNjKn4QgDnlt3+BtLDxGiRIgSvqs+DrhjAhqkZK0cFZR0yn Ja9OEqpnghVyq+g7h0zs18F3wOxr1HFeuTQ0hXzKkkCM/ekg2+OckwfeURDIyGnpC5vg6lxb8gq NUjTyEylQCqKJMlAaGqPDUhzusnrXvg/1H6700DXt09by2ZyB4CyJ0PifdKIcYUs180xaOsYwO6 lrFlPMQoGbUhlPQ0+NK1Et12j68Ph/y1rg6pjAQOMht3TcjXho0kqsgBgqNQtU7zQRaBviQtVEr vogPgxLs2fngQaZ9gBA5cC4blfBbn86lOQdkMzdVsRRMtq7+Tu16sPSkyk2wkrsnk4LEgd2ArZL vvmVJ4bAyqjArKQq4tWns+vs0E5/3BeWAJLi9pW6xLFRww3a0Y2hznBvgoHOttKIavyXY9r7m80 NfW8wxWCMQe7XlvYkxI2bwqbkRiH48= X-Received: by 2002:a05:6000:2207:b0:439:b7c9:2ef1 with SMTP id ffacd0b85a97d-43b9e9ea728mr3197231f8f.20.1774610237142; Fri, 27 Mar 2026 04:17:17 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 16/65] hw/intc/arm_gicv5: Implement IRS_IST_{BASER, STATUSR, CFGR} Date: Fri, 27 Mar 2026 11:16:11 +0000 Message-ID: <20260327111700.795099-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610760295158500 Content-Type: text/plain; charset="utf-8" Implement the three registers that handle configuration of the interrupt status table for physical LPIs: * IRS_IST_BASER holds the base address of the table, and has the VALID bit that tells the IRS to start using the config * IRS_IST_CFGR has all the other config data for the table * IRS_IST_STATUSR has the IDLE bit that tells software when updates to IRS_IST_BASER have taken effect Implement these registers. Note that neither BASER nor CFGR can be written when VALID =3D=3D 1, except to clear the VALID bit. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5.c | 74 ++++++++++++++++++++++++++++++ hw/intc/arm_gicv5_common.c | 4 ++ include/hw/intc/arm_gicv5_common.h | 3 ++ 3 files changed, 81 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 250925f004..cbb35c0270 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -265,6 +265,24 @@ REG64(IRS_SWERR_SYNDROMER0, 0x3c8) REG64(IRS_SWERR_SYNDROMER1, 0x3d0) FIELD(IRS_SWERR_SYNDROMER2, ADDR, 3, 53) =20 +static void irs_ist_baser_write(GICv5 *s, GICv5Domain domain, uint64_t val= ue) +{ + GICv5Common *cs =3D ARM_GICV5_COMMON(s); + + if (FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID)) { + /* If VALID is set, ADDR is RO and we can only update VALID */ + bool valid =3D FIELD_EX64(value, IRS_IST_BASER, VALID); + if (valid) { + /* Ignore 1->1 transition */ + return; + } + cs->irs_ist_baser[domain] =3D FIELD_DP64(cs->irs_ist_baser[domain], + IRS_IST_BASER, VALID, valid= ); + return; + } + cs->irs_ist_baser[domain] =3D value; +} + static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset, uint64_t *data, MemTxAttrs attrs) { @@ -325,6 +343,26 @@ static bool config_readl(GICv5 *s, GICv5Domain domain,= hwaddr offset, case A_IRS_AIDR: *data =3D cs->irs_aidr; return true; + + case A_IRS_IST_BASER: + *data =3D extract64(cs->irs_ist_baser[domain], 0, 32); + return true; + + case A_IRS_IST_BASER + 4: + *data =3D extract64(cs->irs_ist_baser[domain], 32, 32); + return true; + + case A_IRS_IST_STATUSR: + /* + * For QEMU writes to IRS_IST_BASER and IRS_MAP_L2_ISTR take effect + * instantaneously, and the guest can never see the IDLE bit as 0. + */ + *data =3D R_IRS_IST_STATUSR_IDLE_MASK; + return true; + + case A_IRS_IST_CFGR: + *data =3D cs->irs_ist_cfgr[domain]; + return true; } =20 return false; @@ -333,18 +371,54 @@ static bool config_readl(GICv5 *s, GICv5Domain domain= , hwaddr offset, static bool config_writel(GICv5 *s, GICv5Domain domain, hwaddr offset, uint64_t data, MemTxAttrs attrs) { + GICv5Common *cs =3D ARM_GICV5_COMMON(s); + + switch (offset) { + case A_IRS_IST_BASER: + irs_ist_baser_write(s, domain, + deposit64(cs->irs_ist_baser[domain], 0, 32, da= ta)); + return true; + case A_IRS_IST_BASER + 4: + irs_ist_baser_write(s, domain, + deposit64(cs->irs_ist_baser[domain], 32, 32, d= ata)); + return true; + case A_IRS_IST_CFGR: + if (FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID)) { + qemu_log_mask(LOG_GUEST_ERROR, + "guest tried to write IRS_IST_CFGR for %s config= frame " + "while IST_BASER.VALID set\n", domain_name[domai= n]); + } else { + cs->irs_ist_cfgr[domain] =3D data; + } + return true; + } + return false; } =20 static bool config_readll(GICv5 *s, GICv5Domain domain, hwaddr offset, uint64_t *data, MemTxAttrs attrs) { + GICv5Common *cs =3D ARM_GICV5_COMMON(s); + + switch (offset) { + case A_IRS_IST_BASER: + *data =3D cs->irs_ist_baser[domain]; + return true; + } + return false; } =20 static bool config_writell(GICv5 *s, GICv5Domain domain, hwaddr offset, uint64_t data, MemTxAttrs attrs) { + switch (offset) { + case A_IRS_IST_BASER: + irs_ist_baser_write(s, domain, data); + return true; + } + return false; } =20 diff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c index 54d75db014..44909d1b05 100644 --- a/hw/intc/arm_gicv5_common.c +++ b/hw/intc/arm_gicv5_common.c @@ -62,6 +62,10 @@ void gicv5_common_init_irqs_and_mmio(GICv5Common *cs, =20 static void gicv5_common_reset_hold(Object *obj, ResetType type) { + GICv5Common *cs =3D ARM_GICV5_COMMON(obj); + + memset(cs->irs_ist_baser, 0, sizeof(cs->irs_ist_baser)); + memset(cs->irs_ist_cfgr, 0, sizeof(cs->irs_ist_cfgr)); } =20 static void gicv5_common_init(Object *obj) diff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5= _common.h index 88e1b4d73d..9bfafcebfc 100644 --- a/include/hw/intc/arm_gicv5_common.h +++ b/include/hw/intc/arm_gicv5_common.h @@ -62,6 +62,9 @@ struct GICv5Common { =20 MemoryRegion iomem[NUM_GICV5_DOMAINS]; =20 + uint64_t irs_ist_baser[NUM_GICV5_DOMAINS]; + uint32_t irs_ist_cfgr[NUM_GICV5_DOMAINS]; + /* Bits here are set for each physical interrupt domain implemented */ uint8_t implemented_domains; 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We would like to be able to write generic code that can manipulate any of these ISTs. Define a struct which captures the config information for an IST, and cache the IRS_IST_CFGR/IRS_IST_BASER data into this format when the guest sets the VALID bit. This also allows us to enforce the correct handling of reserved and out-of-range values, and expand the encodings of sizes into a more convenient format for later use. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5.c | 64 +++++++++++++++++++++++++++++++++++++ hw/intc/trace-events | 2 ++ include/hw/intc/arm_gicv5.h | 12 +++++++ 3 files changed, 78 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index cbb35c0270..172c5be0d4 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -278,9 +278,68 @@ static void irs_ist_baser_write(GICv5 *s, GICv5Domain = domain, uint64_t value) } cs->irs_ist_baser[domain] =3D FIELD_DP64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID, valid= ); + s->phys_lpi_config[domain].valid =3D false; + trace_gicv5_ist_invalid(domain_name[domain]); return; } cs->irs_ist_baser[domain] =3D value; + + if (FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID)) { + /* + * If the guest just set VALID then capture data into config struc= t, + * sanitize the reserved values, and expand fields out into byte c= ounts. + */ + GICv5ISTConfig *cfg =3D &s->phys_lpi_config[domain]; + uint8_t istbits, l2bits, l2_idx_bits; + uint8_t id_bits =3D FIELD_EX64(cs->irs_ist_cfgr[domain], + IRS_IST_CFGR, LPI_ID_BITS); + id_bits =3D MIN(MAX(id_bits, QEMU_GICV5_MIN_LPI_ID_BITS), QEMU_GIC= V5_ID_BITS); + + switch (FIELD_EX64(cs->irs_ist_cfgr[domain], IRS_IST_CFGR, ISTSZ))= { + case 0: + case 3: /* reserved: acts like the minimum required size */ + istbits =3D 2; + break; + case 1: + istbits =3D 3; + break; + case 2: + istbits =3D 4; + break; + default: + g_assert_not_reached(); + } + switch (FIELD_EX64(cs->irs_ist_cfgr[domain], IRS_IST_CFGR, L2SZ)) { + case 0: + case 3: /* reserved; CONSTRAINED UNPREDICTABLE */ + l2bits =3D 12; /* 4K: 12 bits */ + break; + case 1: + l2bits =3D 14; /* 16K: 14 bits */ + break; + case 2: + l2bits =3D 16; /* 64K: 16 bits */ + break; + default: + g_assert_not_reached(); + } + /* + * Calculate how many bits of an ID index the L2 table + * (e.g. if we need 14 bits to index each byte in a 16K L2 table, + * but each entry is 4 bytes wide then we need 14 - 2 =3D 12 bits + * to index an entry in the table). + */ + l2_idx_bits =3D l2bits - istbits; + cfg->base =3D cs->irs_ist_baser[domain] & R_IRS_IST_BASER_ADDR_MAS= K; + cfg->id_bits =3D id_bits; + cfg->istsz =3D 1 << istbits; + cfg->l2_idx_bits =3D l2_idx_bits; + cfg->structure =3D FIELD_EX64(cs->irs_ist_cfgr[domain], + IRS_IST_CFGR, STRUCTURE); + cfg->valid =3D true; + trace_gicv5_ist_valid(domain_name[domain], cfg->base, cfg->id_bits, + cfg->l2_idx_bits, cfg->istsz, cfg->structure= ); + } } =20 static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset, @@ -553,6 +612,11 @@ static void gicv5_reset_hold(Object *obj, ResetType ty= pe) if (c->parent_phases.hold) { c->parent_phases.hold(obj, type); } + + /* IRS_IST_BASER and IRS_IST_CFGR reset to 0, clear cached info */ + for (int i =3D 0; i < NUM_GICV5_DOMAINS; i++) { + s->phys_lpi_config[i].valid =3D false; + } } =20 static void gicv5_set_idregs(GICv5Common *cs) diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 0797a23c1a..80fc47794b 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -233,6 +233,8 @@ gicv5_badread(const char *domain, uint64_t offset, unsi= gned size) "GICv5 IRS %s gicv5_write(const char *domain, uint64_t offset, uint64_t data, unsigned s= ize) "GICv5 IRS %s config frame write: offset 0x%" PRIx64 " data 0x%" PRIx6= 4 " size %u" gicv5_badwrite(const char *domain, uint64_t offset, uint64_t data, unsigne= d size) "GICv5 IRS %s config frame write: offset 0x%" PRIx64 " data 0x%" PR= Ix64 " size %u: error" gicv5_spi(uint32_t id, int level) "GICv5 SPI ID %u asserted at level %d" +gicv5_ist_valid(const char *domain, uint64_t base, uint8_t id_bits, uint8_= t l2_idx_bits, uint8_t istsz, bool structure) "GICv5 IRS %s IST now valid: = base 0x%" PRIx64 " id_bits %u l2_idx_bits %u IST entry size %u 2-level %d" +gicv5_ist_invalid(const char *domain) "GICv5 IRS %s IST no longer valid" =20 # arm_gicv5_common.c gicv5_common_realize(uint32_t irsid, uint32_t num_cpus, uint32_t spi_base,= uint32_t spi_irs_range, uint32_t spi_range) "GICv5 IRS realized: IRS ID %u= , %u CPUs, SPI base %u, SPI IRS range %u, SPI range %u" diff --git a/include/hw/intc/arm_gicv5.h b/include/hw/intc/arm_gicv5.h index 42ccef8474..f6ecd9c323 100644 --- a/include/hw/intc/arm_gicv5.h +++ b/include/hw/intc/arm_gicv5.h @@ -17,11 +17,23 @@ =20 OBJECT_DECLARE_TYPE(GICv5, GICv5Class, ARM_GICV5) =20 +typedef struct GICv5ISTConfig { + hwaddr base; /* Base address */ + uint8_t id_bits; /* number of bits in an ID for this table */ + uint8_t l2_idx_bits; /* number of ID bits that index into L2 table */ + uint8_t istsz; /* L2 ISTE size in bytes */ + bool structure; /* true if using 2-level table */ + bool valid; /* true if this table is valid and usable */ +} GICv5ISTConfig; + /* * This class is for TCG-specific state for the GICv5. */ struct GICv5 { GICv5Common parent_obj; + + /* This is the info from IRS_IST_BASER and IRS_IST_CFGR */ + GICv5ISTConfig phys_lpi_config[NUM_GICV5_DOMAINS]; }; =20 struct GICv5Class { --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610394; cv=none; d=zohomail.com; s=zohoarc; b=H3AZ3f4Ih1HkYXz8BO2KtYJ5r1TMFf+fWau3wgMkywOhV/qejRsV8Vivm2c4F+p8NpHdV7ZI9fHGElSYAXP3vSaFjwgVLPKflgkiPFfdNHMr8zWMZMyhrUc9vnr0wMGGmHU/3ssQq4FIy9yCG9FnRhYlFgAaiX8/WNcbkPNUGpo= ARC-Message-Signature: i=1; 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This acts by looking the interrupt ID up in the Interrupt State Table and storing the new priority value into the table entry. The memory transaction has to have the right transaction attributes for the domain it is for; we precalculate these and keep them in the GICv5ISTConfig. The GIC has an optional software-error reporting mechanism via the IRS_SWERR_* registers; this does not report all failure cases, only those that would be annoying to detect and debug in some other way. We choose not to implement this, but include some comments for reportable error cases for future reference. Our LOG_GUEST_ERROR logging is a superset of this. At this point we implement only handling of SetPriority for LPIs; we will add SPI handling in a later commit. Virtual interrupts aren't supported by this initial EL1-only GICv5 implementation. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5.c | 233 +++++++++++++++++++++++++++++ hw/intc/trace-events | 1 + include/hw/intc/arm_gicv5.h | 1 + include/hw/intc/arm_gicv5_stream.h | 29 ++++ include/hw/intc/arm_gicv5_types.h | 10 ++ 5 files changed, 274 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 172c5be0d4..3588f3323f 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -9,6 +9,7 @@ #include "qemu/osdep.h" #include "hw/core/registerfields.h" #include "hw/intc/arm_gicv5.h" +#include "hw/intc/arm_gicv5_stream.h" #include "qapi/error.h" #include "qemu/log.h" #include "trace.h" @@ -23,6 +24,25 @@ static const char *domain_name[] =3D { [GICV5_ID_REALM] =3D "Realm", }; =20 +static const char *inttype_name(GICv5IntType t) +{ + /* + * We have to be more cautious with getting human readable names + * for a GICv5IntType for trace strings than we do with the domain + * enum, because here the value can come from a guest register + * field. + */ + static const char *names[] =3D { + [GICV5_PPI] =3D "PPI", + [GICV5_LPI] =3D "LPI", + [GICV5_SPI] =3D "SPI", + }; + if (t >=3D ARRAY_SIZE(names) || !names[t]) { + return "RESERVED"; + } + return names[t]; +} + REG32(IRS_IDR0, 0x0) FIELD(IRS_IDR0, INT_DOM, 0, 2) FIELD(IRS_IDR0, PA_RANGE, 2, 4) @@ -265,6 +285,218 @@ REG64(IRS_SWERR_SYNDROMER0, 0x3c8) REG64(IRS_SWERR_SYNDROMER1, 0x3d0) FIELD(IRS_SWERR_SYNDROMER2, ADDR, 3, 53) =20 +FIELD(L1_ISTE, VALID, 0, 1) +FIELD(L1_ISTE, L2_ADDR, 12, 44) + +FIELD(L2_ISTE, PENDING, 0, 1) +FIELD(L2_ISTE, ACTIVE, 1, 1) +FIELD(L2_ISTE, HM, 2, 1) +FIELD(L2_ISTE, ENABLE, 3, 1) +FIELD(L2_ISTE, IRM, 4, 1) +FIELD(L2_ISTE, HWU, 9, 2) +FIELD(L2_ISTE, PRIORITY, 11, 5) +FIELD(L2_ISTE, IAFFID, 16, 16) + +static MemTxAttrs irs_txattrs(GICv5Common *cs, GICv5Domain domain) +{ + /* + * Return a MemTxAttrs to use for IRS memory accesses. IRS_CR1 + * has the usual Arm cacheability/shareability attributes, but + * QEMU doesn't care about those. All we need to specify here is + * the correct security attributes, which depend on the interrupt + * domain. Conveniently, our GICv5Domain encoding matches the + * ARMSecuritySpace one (because both follow an architecturally + * specified field). The exception is that the EL3 domain must be + * Secure instead of Root if we don't implement Realm. + */ + if (domain =3D=3D GICV5_ID_EL3 && + !gicv5_domain_implemented(cs, GICV5_ID_REALM)) { + domain =3D GICV5_ID_S; + } + return (MemTxAttrs) { + .space =3D domain, + .secure =3D domain =3D=3D GICV5_ID_S || domain =3D=3D GICV5_ID_EL3, + }; +} + +static hwaddr l1_iste_addr(GICv5Common *cs, const GICv5ISTConfig *cfg, + uint32_t id) +{ + /* + * In a 2-level IST configuration, return the address of the L1 + * IST entry for this interrupt ID. The bottom l2_idx_bits of the + * ID value are the index into the L2 table, and the higher bits + * of the ID index the L1 table. + */ + uint32_t l1_index =3D id >> cfg->l2_idx_bits; + return cfg->base + (l1_index * 8); +} + +static bool get_l2_iste_addr(GICv5Common *cs, const GICv5ISTConfig *cfg, + uint32_t id, hwaddr *l2_iste_addr) +{ + /* + * Get the address of the L2 interrupt state table entry for this + * interrupt. On success, fill in l2_iste_addr and return true. + * On failure, return false. + */ + hwaddr l2_base; + + if (!cfg->valid) { + return false; + } + + if (id >=3D (1 << cfg->id_bits)) { + return false; + } + + if (cfg->structure) { + /* + * 2-level table: read the L1 IST. The bottom l2_idx_bits of + * the ID value are the index into the L2 table, and the + * higher bits of the ID index the L1 table. There is always + * at least one L1 table entry. + */ + hwaddr l1_addr =3D l1_iste_addr(cs, cfg, id); + uint64_t l1_iste; + MemTxResult res; + + l1_iste =3D address_space_ldq_le(&cs->dma_as, l1_addr, + cfg->txattrs, &res); + if (res !=3D MEMTX_OK) { + /* Reportable with EC=3D0x01 if sw error reporting implemented= */ + qemu_log_mask(LOG_GUEST_ERROR, "L1 ISTE lookup failed for ID 0= x%x" + " at physical address 0x" HWADDR_FMT_plx "\n", + id, l1_addr); + return false; + } + if (!FIELD_EX64(l1_iste, L1_ISTE, VALID)) { + return false; + } + l2_base =3D l1_iste & R_L1_ISTE_L2_ADDR_MASK; + id =3D extract32(id, 0, cfg->l2_idx_bits); + } else { + /* 1-level table */ + l2_base =3D cfg->base; + } + + *l2_iste_addr =3D l2_base + (id * cfg->istsz); + return true; +} + +static bool read_l2_iste_mem(GICv5Common *cs, const GICv5ISTConfig *cfg, + hwaddr addr, uint32_t *l2_iste) +{ + MemTxResult res; + + *l2_iste =3D address_space_ldl_le(&cs->dma_as, addr, cfg->txattrs, &re= s); + if (res !=3D MEMTX_OK) { + /* Reportable with EC=3D0x02 if sw error reporting implemented */ + qemu_log_mask(LOG_GUEST_ERROR, "L2 ISTE read failed at physical " + "address 0x" HWADDR_FMT_plx "\n", addr); + } + return res =3D=3D MEMTX_OK; +} + +static bool write_l2_iste_mem(GICv5Common *cs, const GICv5ISTConfig *cfg, + hwaddr addr, uint32_t l2_iste) +{ + MemTxResult res; + + address_space_stl_le(&cs->dma_as, addr, l2_iste, cfg->txattrs, &res); + if (res !=3D MEMTX_OK) { + /* Reportable with EC=3D0x02 if sw error reporting implemented */ + qemu_log_mask(LOG_GUEST_ERROR, "L2 ISTE write failed at physical " + "address 0x" HWADDR_FMT_plx "\n", addr); + } + return res =3D=3D MEMTX_OK; +} + +/* + * This is returned by get_l2_iste() and has everything we need to do + * the writeback of the L2 ISTE word in put_l2_iste(). Currently the + * get/put functions always directly do guest memory reads and writes + * to update the L2 ISTE. In a future commit we will add support for a + * cache of some of the ISTE data in a local hashtable; the APIs are + * designed with that in mind. + */ +typedef struct L2_ISTE_Handle { + hwaddr l2_iste_addr; + uint32_t l2_iste; +} L2_ISTE_Handle; + +static uint32_t *get_l2_iste(GICv5Common *cs, const GICv5ISTConfig *cfg, + uint32_t id, L2_ISTE_Handle *h) +{ + /* + * Find the L2 ISTE for the interrupt @id. + * + * We return a pointer to the ISTE: the caller can freely read and + * modify the uint64_t pointed to to update the ISTE. If the + * caller modifies the L2 ISTE word, it must call put_l2_iste(), + * passing it @h, to write back the ISTE. If the caller is only + * reading the L2 ISTE, it does not need to call put_l2_iste(). + * + * We fill in @h with information needed for put_l2_iste(). + * + * If the ISTE could not be read (typically because of a memory + * error), return NULL. + */ + if (!get_l2_iste_addr(cs, cfg, id, &h->l2_iste_addr) || + !read_l2_iste_mem(cs, cfg, h->l2_iste_addr, &h->l2_iste)) { + return NULL; + } + return &h->l2_iste; +} + +static void put_l2_iste(GICv5Common *cs, const GICv5ISTConfig *cfg, + L2_ISTE_Handle *h) +{ + /* + * Write back the modified L2_ISTE word found with get_l2_iste(). + * Once this has been called the L2_ISTE_Handle @h and the pointer + * to the L2 ISTE word are no longer valid. + */ + write_l2_iste_mem(cs, cfg, h->l2_iste_addr, h->l2_iste); +} + +void gicv5_set_priority(GICv5Common *cs, uint32_t id, uint8_t priority, + GICv5Domain domain, GICv5IntType type, bool virtua= l) +{ + GICv5 *s =3D ARM_GICV5(cs); + + trace_gicv5_set_priority(domain_name[domain], inttype_name(type), virt= ual, + id, priority); + /* We must ignore unimplemented low-order priority bits */ + priority &=3D MAKE_64BIT_MASK(5 - QEMU_GICV5_PRI_BITS, QEMU_GICV5_PRI_= BITS); + + if (virtual) { + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_priority: tried to set " + "priority of a virtual interrupt\n"); + return; + } + + switch (type) { + case GICV5_LPI: + { + const GICv5ISTConfig *cfg =3D &s->phys_lpi_config[domain]; + L2_ISTE_Handle h; + uint32_t *l2_iste_p =3D get_l2_iste(cs, cfg, id, &h); + + if (!l2_iste_p) { + return; + } + *l2_iste_p =3D FIELD_DP32(*l2_iste_p, L2_ISTE, PRIORITY, priority); + put_l2_iste(cs, cfg, &h); + break; + } + default: + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_priority: tried to set " + "priority of bad interrupt type %d\n", type); + return; + } +} + static void irs_ist_baser_write(GICv5 *s, GICv5Domain domain, uint64_t val= ue) { GICv5Common *cs =3D ARM_GICV5_COMMON(s); @@ -331,6 +563,7 @@ static void irs_ist_baser_write(GICv5 *s, GICv5Domain d= omain, uint64_t value) */ l2_idx_bits =3D l2bits - istbits; cfg->base =3D cs->irs_ist_baser[domain] & R_IRS_IST_BASER_ADDR_MAS= K; + cfg->txattrs =3D irs_txattrs(cs, domain), cfg->id_bits =3D id_bits; cfg->istsz =3D 1 << istbits; cfg->l2_idx_bits =3D l2_idx_bits; diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 80fc47794b..42f5e73d54 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -235,6 +235,7 @@ gicv5_badwrite(const char *domain, uint64_t offset, uin= t64_t data, unsigned size gicv5_spi(uint32_t id, int level) "GICv5 SPI ID %u asserted at level %d" gicv5_ist_valid(const char *domain, uint64_t base, uint8_t id_bits, uint8_= t l2_idx_bits, uint8_t istsz, bool structure) "GICv5 IRS %s IST now valid: = base 0x%" PRIx64 " id_bits %u l2_idx_bits %u IST entry size %u 2-level %d" gicv5_ist_invalid(const char *domain) "GICv5 IRS %s IST no longer valid" +gicv5_set_priority(const char *domain, const char *type, bool virtual, uin= t32_t id, uint8_t priority) "GICv5 IRS SetPriority %s %s virtual:%d ID %u p= rio %u" =20 # arm_gicv5_common.c gicv5_common_realize(uint32_t irsid, uint32_t num_cpus, uint32_t spi_base,= uint32_t spi_irs_range, uint32_t spi_range) "GICv5 IRS realized: IRS ID %u= , %u CPUs, SPI base %u, SPI IRS range %u, SPI range %u" diff --git a/include/hw/intc/arm_gicv5.h b/include/hw/intc/arm_gicv5.h index f6ecd9c323..c631ecc3e8 100644 --- a/include/hw/intc/arm_gicv5.h +++ b/include/hw/intc/arm_gicv5.h @@ -19,6 +19,7 @@ OBJECT_DECLARE_TYPE(GICv5, GICv5Class, ARM_GICV5) =20 typedef struct GICv5ISTConfig { hwaddr base; /* Base address */ + MemTxAttrs txattrs; /* TX attrs to use for this table */ uint8_t id_bits; /* number of bits in an ID for this table */ uint8_t l2_idx_bits; /* number of ID bits that index into L2 table */ uint8_t istsz; /* L2 ISTE size in bytes */ diff --git a/include/hw/intc/arm_gicv5_stream.h b/include/hw/intc/arm_gicv5= _stream.h index 7257ddde90..e1649cbb40 100644 --- a/include/hw/intc/arm_gicv5_stream.h +++ b/include/hw/intc/arm_gicv5_stream.h @@ -12,6 +12,7 @@ #define HW_INTC_ARM_GICV5_STREAM_H =20 #include "target/arm/cpu-qom.h" +#include "hw/intc/arm_gicv5_types.h" =20 typedef struct GICv5Common GICv5Common; =20 @@ -29,4 +30,32 @@ typedef struct GICv5Common GICv5Common; */ bool gicv5_set_gicv5state(ARMCPU *cpu, GICv5Common *cs); =20 +/* + * The architected Stream Protocol is asynchronous; commands can be + * initiated both from the IRS and from the CPU interface, and some + * require acknowledgement. For QEMU, we simplify this because we know + * that in the CPU interface code we hold the BQL and so our IRS model + * is not going to be busy; when we send commands from the CPUIF + * ("upstream commands") we can model this as a synchronous function + * call whose return corresponds to the acknowledgement of a completed + * command. + */ + +/** + * gicv5_set_priority + * @cs: GIC IRS to send command to + * @id: interrupt ID + * @priority: priority to set + * @domain: interrupt Domain to act on + * @type: interrupt type (LPI or SPI) + * @virtual: true if this is a virtual interrupt + * + * Set priority of an interrupt; matches stream interface SetPriority + * command from CPUIF to IRS. There is no report back of + * success/failure to the CPUIF in the protocol. + */ +void gicv5_set_priority(GICv5Common *cs, uint32_t id, + uint8_t priority, GICv5Domain domain, + GICv5IntType type, bool virtual); + #endif diff --git a/include/hw/intc/arm_gicv5_types.h b/include/hw/intc/arm_gicv5_= types.h index 7d23752ece..e2b937fe62 100644 --- a/include/hw/intc/arm_gicv5_types.h +++ b/include/hw/intc/arm_gicv5_types.h @@ -45,4 +45,14 @@ typedef enum GICv5Domain { #define GICV5_PPI_CNTP 30 #define GICV5_PPI_TRBIRQ 31 =20 +/* + * Type of the interrupt; these values match the 3-bit format + * specified in the GICv5 spec R_GYVWB. + */ +typedef enum GICv5IntType { + GICV5_PPI =3D 1, + GICV5_LPI =3D 2, + GICV5_SPI =3D 3, +} GICv5IntType; + #endif --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610511; cv=none; d=zohomail.com; s=zohoarc; b=JU+uu/YWoBngfIKU9NUC1eFnGYexuKTmy6MwfcAo6ULroknjuex9SYoijpE04l1rpMlQ8DmUJNkpFmd489FHsv/ire6ZcPFTyP05IMvs+kw5FYrVn5AOsqBbGsSLsoW6aPKWNzkw3MREn7fIP6zAabQbxTv7aLsUhbLwAP5TC6s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610511; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=x13cV/o1Pi9D6t5vPv/J+WSzawf4SKPSgV3PxkKGE6o=; b=OkT4YmIaJlYJndgc3u5b5FOxm1YEzQv1v4VNM0AK8FWwisqORUFM9VZb3Zf34r8LYhCbEzfwXKPlmq32SzA+RXDYCyN+zOdrRsSiyp7VmyWSziAVYKXj+Jhnpjnp9RRqC43y5N8xKSVNrWqkk4YeGagfzVcmiKuGoyt81uDDzgw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177461051106088.40155551054477; Fri, 27 Mar 2026 04:21:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65Bu-0006Zr-Oo; Fri, 27 Mar 2026 07:17:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65Br-0006WC-Av for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:23 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65Bp-0007vL-FH for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:23 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-439b2965d4bso1506662f8f.2 for ; Fri, 27 Mar 2026 04:17:20 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610240; x=1775215040; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=x13cV/o1Pi9D6t5vPv/J+WSzawf4SKPSgV3PxkKGE6o=; b=lpaPJ2uriPePz4a2UUxBagKMf4pthf9QUjn3bnncugnhq/ToIfiKIEpWFio7Orwe/1 DYYwUXchb4BHGhwWodMdlelGp0vhVzNK9rDOM5xQ5c95xZHtFXg/JcfgjLaVq+bS+woP 5uCmAoBhUPMXAj79HJUSDgBKbEwwQ+rQlibYaXHiksD7rlGp2L960cMkIeeNsaQgpack YK/X/rLsEdecR0qaKWCWCfJuzu4k0gcsWrJevXa6D/x1Z2ncG3bE/GYgcGMd9sYP2+cI JW6oEcRaQZ2vIBmRlLRZgvA5ak0RhwbOt3ZA2GCQ64/ccyPfe/vf6fpg/O0ItL8nP2pn 3p7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610240; x=1775215040; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=x13cV/o1Pi9D6t5vPv/J+WSzawf4SKPSgV3PxkKGE6o=; b=G1sQdBJSwJB0nAZgCCsIM0hp4L54wo5tmtbVzGF54/eAUlmpcjsgdC1LFUUW9enEPD 72cqs8paBufXJORtqAi91CPFIHe4XOcu9ZSuIUTEXH35fyanSMHBiLnYFqTA8/UqRNSZ /KQvbuwP1DV6lltsGhT+K8nj/YqkO6tyaI+OvirJ2H6oRvfBOQ6Bxljcd9YmD0em9YiI A5xNoyAbi9LRfqoY5ZNMNZ6Fmst+nJMtgKIzFX5YbDXiJQyLJElTfSKUvzKuKjSeEBal mekSDc732sKn2jNuWN948t/l3xEOjNDlX5DSyumvC8KbK5wKoTF5p12c9YL8U0cMt6DV 4d8A== X-Forwarded-Encrypted: i=1; AJvYcCVC5LsmWDR/FE+g1aZtYNQOLYfPVJ0bVlYbCuYkfhY9VUwV0YJwCmx9JOsgtdBKlbd1PEOurJuTFV1K@nongnu.org X-Gm-Message-State: AOJu0YwG49eymVRpqm4VMjpzDDk+TibML7JX5XuDGbWYCGw6jWfI7k53 uG8sh1rWzfKXjDbg+PlzzHdCgt6hbwLFyCEgp6FiAVYeCJ7anj7SFxcoWYaebC2+oVs= X-Gm-Gg: ATEYQzyXkvn8UwJ1i3bVv8bhVN+ZLLyZF+aI+nuZOwCG56OOQFymreJm8kR+chZnW7R hqUJPHHCuB+MmPqVAF7/meZpN/xeW0OtiFBTWhx0NqchGYX+Pgr8Q/v0fshO7uHPaANwxZaKjzk fdFHFWV+UqTWh63D/dr41wuQ1mI8LHjD87HjFMk8fK9P0NwcsNPt47Lw5tdAO7CjU2QmlDidhBE 7hUx9ym9O83S0DP8luqTWdqx6ZLmBWArYoluqf9DApRndSIffbSPIouNsmtwG3Y1eu3oUYp4IVu /o8p4noU42bZzFEqxAo1wweNaHU9bgQuCh8tCWkRF+aVKg9ABILxuD5jUu3xq/b/iF1zbfGnv1f 0wWDkPmJJ3uqDCEx9CgcIr+wk8M+LuoNjukQ+HEfX/bQfLXMn+Tyo9gXWuV5E+oi79AM/UGcSGx u4ngcxazFfsIGDpB4Y38Y0SARQ/J+/S24zuQEgf4dUlA95v6X16Jud6YiZegwD9h7/vm72JxEhr gSivNr5Mu61fG5QCYUGVNCW+tVamhE= X-Received: by 2002:a05:6000:40cd:b0:436:3707:2bf0 with SMTP id ffacd0b85a97d-43b9ea465e0mr3100215f8f.35.1774610239830; Fri, 27 Mar 2026 04:17:19 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 19/65] target/arm: GICv5 cpuif: Implement the GIC CDPRI instruction Date: Fri, 27 Mar 2026 11:16:14 +0000 Message-ID: <20260327111700.795099-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610512060154100 Content-Type: text/plain; charset="utf-8" Implement the CPU interface GIC CDPRI instruction, which is a wrapper around the SetPriority operation. As with the barrier insns, we omit for the moment details which are needed when the GICv5 supports virtualization: * traps when legacy GICv3 emulation is enabled * fine-grained-trap handling (which is done via registers that are new in GICv5) * sending the command for the virtual interrupt domain when inside a guest The CD instructions operate on the Current Physical Interrupt Domain, which is the one associated with the current security state and exception level. The spec also has the concept of a Logical Interrupt Domain, which is the one associated with the security state defined by SCR_EL3.{NS,NSE}. Mostly the logical interrupt domain is used by the LD instructions, which are EL3-only; but we will also want the concept later for handling some banked registers, so we define functions for both. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- target/arm/tcg/gicv5-cpuif.c | 58 ++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 7392a98c49..0c2bba5ce9 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -10,6 +10,59 @@ #include "cpu.h" #include "internals.h" #include "cpregs.h" +#include "hw/intc/arm_gicv5_stream.h" + +FIELD(GIC_CDPRI, ID, 0, 24) +FIELD(GIC_CDPRI, TYPE, 29, 3) +FIELD(GIC_CDPRI, PRIORITY, 35, 5) + +static GICv5Common *gicv5_get_gic(CPUARMState *env) +{ + return env->gicv5state; +} + +static GICv5Domain gicv5_logical_domain(CPUARMState *env) +{ + /* + * Return the Logical Interrupt Domain, which is the one associated + * with the security state selected by the SCR_EL3.{NS,NSE} bits + */ + switch (arm_security_space_below_el3(env)) { + case ARMSS_Secure: + return GICV5_ID_S; + case ARMSS_NonSecure: + return GICV5_ID_NS; + case ARMSS_Realm: + return GICV5_ID_REALM; + default: + g_assert_not_reached(); + } +} + +static GICv5Domain gicv5_current_phys_domain(CPUARMState *env) +{ + /* + * Return the Current Physical Interrupt Domain as + * defined by R_ZFCXM. + */ + if (arm_current_el(env) =3D=3D 3) { + return GICV5_ID_EL3; + } + return gicv5_logical_domain(env); +} + +static void gic_cdpri_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + GICv5Common *gic =3D gicv5_get_gic(env); + uint8_t priority =3D FIELD_EX64(value, GIC_CDPRI, PRIORITY); + GICv5IntType type =3D FIELD_EX64(value, GIC_CDPRI, TYPE); + uint32_t id =3D FIELD_EX64(value, GIC_CDPRI, ID); + bool virtual =3D false; + GICv5Domain domain =3D gicv5_current_phys_domain(env); + + gicv5_set_priority(gic, id, priority, domain, type, virtual); +} =20 static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { /* @@ -33,6 +86,11 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 0, .opc2 =3D 1, .access =3D PL1_W, .type =3D ARM_CP_NOP, }, + { .name =3D "GIC_CDPRI", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 2, + .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .writefn =3D gic_cdpri_write, + }, }; =20 void define_gicv5_cpuif_regs(ARMCPU *cpu) --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610564; cv=none; d=zohomail.com; s=zohoarc; b=PZuYd9A5FHeUhq0PRsHuYC13qlEa7hRgHV+400Dg9RMgOdwYVXHSq6Dcefxy1PI9CaaRrZAXyhMIKHydoWYROyCY1B7kbonb7vGcxPgVrkC0ybRG/UoPjaDYxbHr8vBWd2VFpx4KObQRRpl9aNb6XrNWZgHOCfEQm7WIjTXtkGc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610564; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=iFlZReDv+qQIw0DAeaun7wzY8NaJlNVkqk/yf85M5x8=; b=D0rF82jYBfiV6W66WfiaraAPmx4yaArtq+tIxbhJZ9mynGbjtW+TX9Ce0FoT7vhTjs/FfK1y4aEfMo3U6ShjXaq4j+xW1AnZN3pGtdkXO1XYPO+ZQHTzMK0jNIQDKMJma9552IcMPgEoClGK56dtPDNI63wijBGfVOHS4xCEPMI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610564166233.05572747108795; Fri, 27 Mar 2026 04:22:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65C0-0006io-C2; Fri, 27 Mar 2026 07:17:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65Bs-0006Xt-CV for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:24 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65Bq-0007vw-Eq for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:24 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-439b94a19fdso1876603f8f.0 for ; Fri, 27 Mar 2026 04:17:21 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610241; x=1775215041; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iFlZReDv+qQIw0DAeaun7wzY8NaJlNVkqk/yf85M5x8=; b=FzXQNF5U3EXkaEvMJ30UM51QB5TtiGoN7cTXZyGpM7C43HHKsJDCs4/nCrUlZjjA8r PkUFktMjuEGcnviwHNq2DvdSi74x0L/JOsmmz0kyS+b+t8oIwoGa+H4I6lrRbSmSItWX 2Xgnk5mz7+6S+VFZX2AjyMzAcw1foAP5V7pCqqM9DRz4la4bL/HeMxxgZA5d/+vc4btO mzylHFFJTBOfydFOHBQeDWEPUV1MeBg8sPLRVotoZYuvQgSFJTsmLfep1WFlIDeXFbYJ nIqrCNyL6r7J/TIIQjtVbPgHIduJPY3uMJaG/B1yy37yPBOmyuR8pTnOAEhavQz7hdCD /ZdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610241; x=1775215041; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=iFlZReDv+qQIw0DAeaun7wzY8NaJlNVkqk/yf85M5x8=; b=G7wdtU+dcCr1HTixW5yO5Zgm0F5Yhlc8U/8ctUApwkt2KQdpHcTE2BG9jo6SIYKREo ICJ1+tkWkZHCwINXWxiN0gEW1ksNn8kIaUmlTuTmL7KGcNrsMLwy2AV32Vj+ewcZOz/6 qeFqENuBUoJVVL9RuCPynStyMmM3sduJPiNWkp01JI3DJROTqQuO4U94HDbeuboEbNk/ u6eBBzOZ1OZyLfYBRMmNoLviU6AGyAfZg7jTzP2OJVBfGk1qRhhgsVKX5NBjiFtr8DAH SM7n2ZC6NWQj1fBiVxzwDBC12uBVihVaA0iaVJStMbk5ESaM3+pjREKRi4wjjEWYYu3D voYw== X-Forwarded-Encrypted: i=1; AJvYcCWg8L1Nj1ZxcaW6lqabVnLMN7LHMImIY10uoSy7e3xkezgdQqOKjCKA9CBwWzZEGB0wr132CGuVicBu@nongnu.org X-Gm-Message-State: AOJu0YwEC6ZhIkeJluQJfgshJPUIFCG6Urq2oq4v2UhH+JD81geFxFbw 3TFhZUOQvHRX/ZK2bzrLRWdSMyc64lTsq8JNR9nvTYzaPyvnBIriyz7+tVml8EQMom4= X-Gm-Gg: ATEYQzx3Yt+mcsxwfFe9y9X5vWB8AGKvmijCq13CZ5NAQkUol977yaESGdMhEivic/2 EduiwrACu7gSAv+c2OCa/wsHPdGyEGL4/LquXOZXn37V8WSJJ/+WUBxhOGBCgoCKGzDD77wgVGa I/Tvyi2e+/nE3o89z90LaJ+y4VZz9AejkmKEHjakV76Hrljn1zRnp5CnnwstuOyx0OvANowqy/l ITamfGX2gb5OLaYjdWdaT8NmwLiFqnfc80c4sn+UMnGd43G2NXfJUlGV9yTFR0Q1GGYpf3vyURt 4afMeyaImhYESweFRw0uCtP0pcE2wQzBL9jt1I06H5QDSHWASvPEm2c0Hbxqp0dqMrQu3aWa+Vg N+wavGXiCK7hhfLug0pX34klqhm0NJEr12lmsrXS6SPPEbab4cHJS9Ac4stm7Djm6eKTLrTxNW9 4kAmLrVMh3sYvtDirGnpnOo8XTWsD1rEEb32jHhqIRcHeC0h3xeTcYI2eu+WrpGQQx8H+tSUQFh WQqIG+JpYK1jH2z4FmdAAukpCoXdmA+jo96DNsVEg== X-Received: by 2002:a05:6000:2892:b0:43b:47bc:c147 with SMTP id ffacd0b85a97d-43b9ea66f1fmr3345875f8f.45.1774610240765; Fri, 27 Mar 2026 04:17:20 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 20/65] hw/intc/arm_gicv5: Implement IRS_MAP_L2_ISTR Date: Fri, 27 Mar 2026 11:16:15 +0000 Message-ID: <20260327111700.795099-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610566918154101 Content-Type: text/plain; charset="utf-8" The IRS register IRS_MAP_L2_ISTR is used by software to tell the IRS that it has updated the address in an L1 IST entry to point to an L2 IST. The sequence of events here is: * software writes to L1_ISTE.L2_ADDR for some L1 ISTE which is not valid (i.e. where L1_ISTE.VALID is 0); it leaves VALID at 0 * software writes to IRS_MAP_L2_ISTR with some INTID that is inside the range for this L1 ISTE * the IRS sets IRS_IST_STATUSR.IDLE to 0 * the IRS takes note of this information * the IRS writes to the L1_ISTE to set VALID=3D1 * the IRS sets IRS_IST_STATUSR.IDLE to 1 to indicate that the update is complete For QEMU, we're strictly synchronous, so (as with IRS_IST_BASER updates) we don't need to model the IDLE transitions and can have IRS_IST_STATUSR always return IDLE=3D1. We also don't currently cache anything for ISTE lookups, so we don't need to invalidate or update anything when software makes the L2 valid. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 3588f3323f..7d654a91e6 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -497,6 +497,43 @@ void gicv5_set_priority(GICv5Common *cs, uint32_t id, = uint8_t priority, } } =20 +static void irs_map_l2_istr_write(GICv5 *s, GICv5Domain domain, uint64_t v= alue) +{ + GICv5Common *cs =3D ARM_GICV5_COMMON(s); + GICv5ISTConfig *cfg =3D &s->phys_lpi_config[domain]; + uint32_t intid =3D FIELD_EX32(value, IRS_MAP_L2_ISTR, ID); + hwaddr l1_addr; + uint64_t l1_iste; + MemTxResult res; + + if (!FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID) || + !cfg->structure) { + /* WI if no IST set up or it is not 2-level */ + return; + } + + /* Find the relevant L1 ISTE and set its VALID bit */ + l1_addr =3D l1_iste_addr(cs, cfg, intid); + + l1_iste =3D address_space_ldq_le(&cs->dma_as, l1_addr, cfg->txattrs, &= res); + if (res !=3D MEMTX_OK) { + goto txfail; + } + + l1_iste =3D FIELD_DP64(l1_iste, L1_ISTE, VALID, 1); + + address_space_stq_le(&cs->dma_as, l1_addr, l1_iste, cfg->txattrs, &res= ); + if (res !=3D MEMTX_OK) { + goto txfail; + } + return; + +txfail: + /* Reportable with EC=3D0x0 if sw error reporting implemented */ + qemu_log_mask(LOG_GUEST_ERROR, "L1 ISTE update failed for ID 0x%x at " + "physical address 0x" HWADDR_FMT_plx "\n", intid, l1_add= r); +} + static void irs_ist_baser_write(GICv5 *s, GICv5Domain domain, uint64_t val= ue) { GICv5Common *cs =3D ARM_GICV5_COMMON(s); @@ -683,6 +720,9 @@ static bool config_writel(GICv5 *s, GICv5Domain domain,= hwaddr offset, cs->irs_ist_cfgr[domain] =3D data; } return true; + case A_IRS_MAP_L2_ISTR: + irs_map_l2_istr_write(s, domain, data); + return true; } =20 return false; --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610693; cv=none; d=zohomail.com; s=zohoarc; b=IOxjM2DsTC0v8raUhOGp8hlNKOdjDiViOWvuX8o5aD4MsW16VzNaKSxL39w69CYjbpfPipC1QFKJgNZFDMI9huq+9xCkO7fmXKQI6e+KZ6k2A48DWoCRTDo2xq2Btyox6naOXU+UFVnC/dFmG0w5LBeS5dXWING3ber1YcwWJmk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610693; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=MfAcFOEb2yOHFn+/VWKLIA0rIGdDdOhNemvo/o7rjjg=; b=dTsiOSeyKZCm364oB+OKV7GF744a9hB3te9/S3qUUyiGoIfWDc3Itt8+BTrgpeHuRlF9YWvb8Gpp/SP7RCEi0TtSdWauLC7FYfdjQ+FoPG1xvG0f8IhQ7JggiOiqEtRTP3QcM0K3+KAlxlJ5p0hAXMYC3UknIBzRjNz8b1gUQOE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610693559275.79513843861605; Fri, 27 Mar 2026 04:24:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65C0-0006jq-UD; Fri, 27 Mar 2026 07:17:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65Bu-0006ZR-Ar for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:26 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65Br-0007wO-U9 for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:26 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-4852b81c73aso17685745e9.3 for ; Fri, 27 Mar 2026 04:17:23 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610242; x=1775215042; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MfAcFOEb2yOHFn+/VWKLIA0rIGdDdOhNemvo/o7rjjg=; b=gwBiU4nW3LajCJSSixzPZ1UUhbPbt8X0J227js9ZhVWCDTjw5DIBwVgDweiDe4S8gd CS1aBTJ0ehAaDGvoy/4Mvu7HMMFhShmDCQvp7qGXe+9iQYb7+CzTfD8ilbdik1K3f/aQ MrbFcf3QZ1qKT9EKP6ApgeUJFELjsoowI/nnLDabHzexJ9BrXBcw5A065DGnefbakOPt CrZfsi56cEOxd7L2Xdx5aqvb3rQoDbYqMT3CHgIeYSkG9U0n501cAXsqAk2MyC0BPFgZ C+F6bijahSPXZtXMRuMrAtiWAtX5XBXPUd2e8/tUbM3wNbMYK5sbaCW1SNWkZaVaQglI f2Dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610242; x=1775215042; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=MfAcFOEb2yOHFn+/VWKLIA0rIGdDdOhNemvo/o7rjjg=; b=NdMfcgdQTJXWI8T3k0TuesI2oLsSBTRioW8slwCm7TxLVhh4Q5+rgENpFTimFdMXjn YXevsF0TEEyVtyVS7YwjkCnCb6PdEUGYqM7c1vJbgNTUPn4B94GwaQX/GkDqTfbgsbxH kCz1fricda0io5Z9h3NHH9IXNy5Vzx106l8E9+dKnsJdVkCuOk/FFmNUpuEdRYwem9Fo hpFsWT2t+Ty3LhWMFu6Y5V+GxtvmkL/K15ZlX141ifrpZLATIIo/qbmh2soiKTQbdHhI 3iU0q2WxPxyCgfioXft+xcI5HREDfP5yUQpMvFgGkLwOHtrrxWW22IrOPOEA9J/z7MdB vwKg== X-Forwarded-Encrypted: i=1; AJvYcCWSU+S63NvObFQBuIcLLSI09b7+08N2426+rR5AoTLNvcT7x3J64MzfPAJJTPwOQw+hbEC0WghFDcz2@nongnu.org X-Gm-Message-State: AOJu0YzCydHW2TZgPzpZQwWU+CdSY29S7gdJIDGDbCLmsdAtfnqjaWnC gz3G8Dvmm2DRhUj6s1gtphlyCUHrAMrND3jJ+QfFldaFUxZcjILKbIgnujLqF5KttTQ= X-Gm-Gg: ATEYQzw9vmbg5Q5ZBASa+pwwDZcETj1rAfEi9egHU+eiust7vNwFp/JsYRiAAv8l4Ph WYiDyYArwBT3DsE2LuxokJVW+cHEz1dV65IKl/gjOuYzaaqEVgnEeWm6xD31YzbPEBK1RlgnBoP FlKf4SdlsMulUr+gncLoGtcXYGfx/ikvfYOS8aWaSnN/eRrB15QgXk7xSxENm63h6z5OAD+suiX g8yP0jBwmG5p3DHmeWYLP9Uf64HWVrcAQEi6KdZmgbIJ09QMXrSrmNlrxnW/XT9wDmIa/71ugN0 zjZyUSqM3PBgoV0gUlRxR6h2EPiNh8b6/J4UQt2lRqqY/xkXLWSHOgZ7Ll/mr/yFcs6kIA+0UnB 6P7AVqKk2UHwS+hC5DZFc94z+cVLsuiedAW2HWLQpn4E0sH1xuZMVbblNS9aRfTxAmj/ZKsuj/w XcIjRXAtkPCmG/tTgL/aWrtPLdjtVj77CJfg8dpxzT2UV917WqXD3Zl9adnVFtRYZK5ea8nrfit TCMVNepiSa64FLWMuIEVZt42ZnKT18= X-Received: by 2002:a05:600c:a44:b0:486:fbf6:abd4 with SMTP id 5b1f17b1804b1-48727efc11dmr29574035e9.9.1774610241653; Fri, 27 Mar 2026 04:17:21 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 21/65] hw/intc/arm_gicv5: Implement remaining set-config functions Date: Fri, 27 Mar 2026 11:16:16 +0000 Message-ID: <20260327111700.795099-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610695076154100 Content-Type: text/plain; charset="utf-8" Implement the GICv5 functions corresponding to the stream protocol SetEnabled, SetPending, SetHandling, and SetTarget commands. These work exactly like SetPriority: the IRS looks up the L2TE and updates the corresponding field in it with the new value. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5.c | 152 +++++++++++++++++++++++++++++ hw/intc/trace-events | 4 + include/hw/intc/arm_gicv5_stream.h | 68 +++++++++++++ include/hw/intc/arm_gicv5_types.h | 15 +++ 4 files changed, 239 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 7d654a91e6..d1eb96fce0 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -497,6 +497,158 @@ void gicv5_set_priority(GICv5Common *cs, uint32_t id,= uint8_t priority, } } =20 +void gicv5_set_enabled(GICv5Common *cs, uint32_t id, bool enabled, + GICv5Domain domain, GICv5IntType type, bool virtual) +{ + GICv5 *s =3D ARM_GICV5(cs); + + trace_gicv5_set_enabled(domain_name[domain], inttype_name(type), virtu= al, + id, enabled); + if (virtual) { + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_enabled: tried to set " + "enable state of a virtual interrupt\n"); + return; + } + + switch (type) { + case GICV5_LPI: + { + const GICv5ISTConfig *cfg =3D &s->phys_lpi_config[domain]; + L2_ISTE_Handle h; + uint32_t *l2_iste_p =3D get_l2_iste(cs, cfg, id, &h); + + if (!l2_iste_p) { + return; + } + *l2_iste_p =3D FIELD_DP32(*l2_iste_p, L2_ISTE, ENABLE, enabled); + put_l2_iste(cs, cfg, &h); + break; + } + default: + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_enabled: tried to set " + "enable state of bad interrupt type %d\n", type); + return; + } +} + +void gicv5_set_pending(GICv5Common *cs, uint32_t id, bool pending, + GICv5Domain domain, GICv5IntType type, bool virtual) +{ + GICv5 *s =3D ARM_GICV5(cs); + + trace_gicv5_set_pending(domain_name[domain], inttype_name(type), virtu= al, + id, pending); + if (virtual) { + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_pending: tried to set " + "pending state of a virtual interrupt\n"); + return; + } + + switch (type) { + case GICV5_LPI: + { + const GICv5ISTConfig *cfg =3D &s->phys_lpi_config[domain]; + L2_ISTE_Handle h; + uint32_t *l2_iste_p =3D get_l2_iste(cs, cfg, id, &h); + + if (!l2_iste_p) { + return; + } + *l2_iste_p =3D FIELD_DP32(*l2_iste_p, L2_ISTE, PENDING, pending); + put_l2_iste(cs, cfg, &h); + break; + } + default: + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_pending: tried to set " + "pending state of bad interrupt type %d\n", type); + return; + } +} + +void gicv5_set_handling(GICv5Common *cs, uint32_t id, + GICv5HandlingMode handling, GICv5Domain domain, + GICv5IntType type, bool virtual) +{ + GICv5 *s =3D ARM_GICV5(cs); + + trace_gicv5_set_handling(domain_name[domain], inttype_name(type), virt= ual, + id, handling); + if (virtual) { + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_handling: tried to set " + "handling mode of a virtual interrupt\n"); + return; + } + + switch (type) { + case GICV5_LPI: + { + const GICv5ISTConfig *cfg =3D &s->phys_lpi_config[domain]; + L2_ISTE_Handle h; + uint32_t *l2_iste_p =3D get_l2_iste(cs, cfg, id, &h); + + if (!l2_iste_p) { + return; + } + *l2_iste_p =3D FIELD_DP32(*l2_iste_p, L2_ISTE, HM, handling); + put_l2_iste(cs, cfg, &h); + break; + } + default: + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_handling: tried to set " + "handling mode of bad interrupt type %d\n", type); + return; + } +} + +void gicv5_set_target(GICv5Common *cs, uint32_t id, uint32_t iaffid, + GICv5RoutingMode irm, GICv5Domain domain, + GICv5IntType type, bool virtual) +{ + GICv5 *s =3D ARM_GICV5(cs); + + trace_gicv5_set_target(domain_name[domain], inttype_name(type), virtua= l, + id, iaffid, irm); + if (virtual) { + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_target: tried to set " + "target of a virtual interrupt\n"); + return; + } + if (irm !=3D GICV5_TARGETED) { + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_target: tried to set " + "1-of-N routing\n"); + /* + * In the cpuif insn "GIC CDAFF", IRM is RES0 for a GIC which + * does not support 1-of-N routing. So warn, and fall through + * to treat IRM=3D1 the same as IRM=3D0. + */ + } + + switch (type) { + case GICV5_LPI: + { + const GICv5ISTConfig *cfg =3D &s->phys_lpi_config[domain]; + L2_ISTE_Handle h; + uint32_t *l2_iste_p =3D get_l2_iste(cs, cfg, id, &h); + + if (!l2_iste_p) { + return; + } + /* + * For QEMU we do not implement 1-of-N routing, and so + * L2_ISTE.IRM is RES0. We never read it, and we can skip + * explicitly writing it to zero here. + */ + *l2_iste_p =3D FIELD_DP32(*l2_iste_p, L2_ISTE, IAFFID, iaffid); + put_l2_iste(cs, cfg, &h); + break; + } + default: + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_target: tried to set " + "target of bad interrupt type %d\n", type); + return; + } +} + static void irs_map_l2_istr_write(GICv5 *s, GICv5Domain domain, uint64_t v= alue) { GICv5Common *cs =3D ARM_GICV5_COMMON(s); diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 42f5e73d54..37ca6e8e12 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -236,6 +236,10 @@ gicv5_spi(uint32_t id, int level) "GICv5 SPI ID %u ass= erted at level %d" gicv5_ist_valid(const char *domain, uint64_t base, uint8_t id_bits, uint8_= t l2_idx_bits, uint8_t istsz, bool structure) "GICv5 IRS %s IST now valid: = base 0x%" PRIx64 " id_bits %u l2_idx_bits %u IST entry size %u 2-level %d" gicv5_ist_invalid(const char *domain) "GICv5 IRS %s IST no longer valid" gicv5_set_priority(const char *domain, const char *type, bool virtual, uin= t32_t id, uint8_t priority) "GICv5 IRS SetPriority %s %s virtual:%d ID %u p= rio %u" +gicv5_set_enabled(const char *domain, const char *type, bool virtual, uint= 32_t id, bool enabled) "GICv5 IRS SetEnabled %s %s virtual:%d ID %u enabled= %d" +gicv5_set_pending(const char *domain, const char *type, bool virtual, uint= 32_t id, bool pending) "GICv5 IRS SetPending %s %s virtual:%d ID %u pending= %d" +gicv5_set_handling(const char *domain, const char *type, bool virtual, uin= t32_t id, int handling) "GICv5 IRS SetHandling %s %s virtual:%d ID %u handl= ing %d" +gicv5_set_target(const char *domain, const char *type, bool virtual, uint3= 2_t id, uint32_t iaffid, int irm) "GICv5 IRS SetTarget %s %s virtual:%d ID = %u IAFFID %u routingmode %d" =20 # arm_gicv5_common.c gicv5_common_realize(uint32_t irsid, uint32_t num_cpus, uint32_t spi_base,= uint32_t spi_irs_range, uint32_t spi_range) "GICv5 IRS realized: IRS ID %u= , %u CPUs, SPI base %u, SPI IRS range %u, SPI range %u" diff --git a/include/hw/intc/arm_gicv5_stream.h b/include/hw/intc/arm_gicv5= _stream.h index e1649cbb40..af2e1851c2 100644 --- a/include/hw/intc/arm_gicv5_stream.h +++ b/include/hw/intc/arm_gicv5_stream.h @@ -58,4 +58,72 @@ void gicv5_set_priority(GICv5Common *cs, uint32_t id, uint8_t priority, GICv5Domain domain, GICv5IntType type, bool virtual); =20 +/** + * gicv5_set_enabled + * @cs: GIC IRS to send command to + * @id: interrupt ID + * @enabled: new enabled state + * @domain: interrupt Domain to act on + * @type: interrupt type (LPI or SPI) + * @virtual: true if this is a virtual interrupt + * + * Set enabled state of an interrupt; matches stream interface + * SetEnabled command from CPUIF to IRS. There is no report back of + * success/failure to the CPUIF in the protocol. + */ +void gicv5_set_enabled(GICv5Common *cs, uint32_t id, + bool enabled, GICv5Domain domain, + GICv5IntType type, bool virtual); + +/** + * gicv5_set_pending + * @cs: GIC IRS to send command to + * @id: interrupt ID + * @pending: new pending state + * @domain: interrupt Domain to act on + * @type: interrupt type (LPI or SPI) + * @virtual: true if this is a virtual interrupt + * + * Set pending state of an interrupt; matches stream interface + * SetPending command from CPUIF to IRS. There is no report back of + * success/failure to the CPUIF in the protocol. + */ +void gicv5_set_pending(GICv5Common *cs, uint32_t id, + bool pending, GICv5Domain domain, + GICv5IntType type, bool virtual); + +/** + * gicv5_set_handling + * @cs: GIC IRS to send command to + * @id: interrupt ID + * @handling: new handling mode + * @domain: interrupt Domain to act on + * @type: interrupt type (LPI or SPI) + * @virtual: true if this is a virtual interrupt + * + * Set handling mode of an interrupt (edge/level); matches stream + * interface SetHandling command from CPUIF to IRS. There is no report + * back of success/failure to the CPUIF in the protocol. + */ +void gicv5_set_handling(GICv5Common *cs, uint32_t id, + GICv5HandlingMode handling, GICv5Domain domain, + GICv5IntType type, bool virtual); + +/** + * gicv5_set_target + * @cs: GIC IRS to send command to + * @id: interrupt ID + * @iaffid: new target PE's interrupt affinity + * @irm: interrupt routing mode (targeted vs 1-of-N) + * @domain: interrupt Domain to act on + * @type: interrupt type (LPI or SPI) + * @virtual: true if this is a virtual interrupt + * + * Set handling mode of an interrupt (edge/level); matches stream + * interface SetHandling command from CPUIF to IRS. There is no report + * back of success/failure to the CPUIF in the protocol. + */ +void gicv5_set_target(GICv5Common *cs, uint32_t id, uint32_t iaffid, + GICv5RoutingMode irm, GICv5Domain domain, + GICv5IntType type, bool virtual); #endif diff --git a/include/hw/intc/arm_gicv5_types.h b/include/hw/intc/arm_gicv5_= types.h index e2b937fe62..20de5b3f46 100644 --- a/include/hw/intc/arm_gicv5_types.h +++ b/include/hw/intc/arm_gicv5_types.h @@ -55,4 +55,19 @@ typedef enum GICv5IntType { GICV5_SPI =3D 3, } GICv5IntType; =20 +/* Interrupt handling mode (same encoding as L2_ISTE.HM) */ +typedef enum GICv5HandlingMode { + GICV5_EDGE =3D 0, + GICV5_LEVEL =3D 1, +} GICv5HandlingMode; + +/* + * Interrupt routing mode (same encoding as L2_ISTE.IRM). + * Note that 1-of-N support is option and QEMU does not implement it. + */ +typedef enum GICv5RoutingMode { + GICV5_TARGETED =3D 0, + GICV5_1OFN =3D 1, +} GICv5RoutingMode; + #endif --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610780; cv=none; d=zohomail.com; s=zohoarc; b=jtquUZIfPV4LEpQfgWyZxew7vVO+y90GfbH31kdlImpxUrTrjbcrBLc70tqF3LcSzQtsQdaUz/9My5qKoTWe260V/N40XyReoaVsdsavoCGb4CvF1wk9K+zihTwxvQMoEmY7dqmn4HHkBDpcQyihz9M+dG2GzbXg34POPE2atog= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610780; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mSHOw0ePxFClS8VZTB3TfGftr7NcOYKm+ePZhUgk940=; b=n22xZaVvUr8avh3P21ZuPDtHmjvsHtpMJKIeCSYq6M6EnwE35QJHv28R7a+OYrjuwR9t4JUIsvSpM2fvyFbieiOHcZLyWRAISOsgXi4K3ncPnjuqPfIbVbFb5dM+xj2cF6AOLLg+WT/FmGEiUxyvy7cP69pc3BciU1ii/zI+1F0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610780052987.2197817399131; Fri, 27 Mar 2026 04:26:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65C1-0006kH-7D; Fri, 27 Mar 2026 07:17:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65Bu-0006ZZ-Fr for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:26 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65Bs-0007we-Ed for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:26 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-43b5bded412so1432365f8f.0 for ; Fri, 27 Mar 2026 04:17:23 -0700 (PDT) Received: from lanath.. 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These are all simple wrappers around the equivalent gicv5_set_* functions, like GIC CDPRI. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- target/arm/tcg/gicv5-cpuif.c | 108 +++++++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 0c2bba5ce9..0c4349f8a7 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -16,6 +16,25 @@ FIELD(GIC_CDPRI, ID, 0, 24) FIELD(GIC_CDPRI, TYPE, 29, 3) FIELD(GIC_CDPRI, PRIORITY, 35, 5) =20 +FIELD(GIC_CDDIS, ID, 0, 24) +FIELD(GIC_CDDIS, TYPE, 29, 3) + +FIELD(GIC_CDEN, ID, 0, 24) +FIELD(GIC_CDEN, TYPE, 29, 3) + +FIELD(GIC_CDAFF, ID, 0, 24) +FIELD(GIC_CDAFF, IRM, 28, 1) +FIELD(GIC_CDAFF, TYPE, 29, 3) +FIELD(GIC_CDAFF, IAFFID, 32, 16) + +FIELD(GIC_CDPEND, ID, 0, 24) +FIELD(GIC_CDPEND, TYPE, 29, 3) +FIELD(GIC_CDPEND, PENDING, 32, 1) + +FIELD(GIC_CDHM, ID, 0, 24) +FIELD(GIC_CDHM, TYPE, 29, 3) +FIELD(GIC_CDHM, HM, 32, 1) + static GICv5Common *gicv5_get_gic(CPUARMState *env) { return env->gicv5state; @@ -51,6 +70,30 @@ static GICv5Domain gicv5_current_phys_domain(CPUARMState= *env) return gicv5_logical_domain(env); } =20 +static void gic_cddis_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + GICv5Common *gic =3D gicv5_get_gic(env); + GICv5IntType type =3D FIELD_EX64(value, GIC_CDDIS, TYPE); + uint32_t id =3D FIELD_EX64(value, GIC_CDDIS, ID); + bool virtual =3D false; + GICv5Domain domain =3D gicv5_current_phys_domain(env); + + gicv5_set_enabled(gic, id, false, domain, type, virtual); +} + +static void gic_cden_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + GICv5Common *gic =3D gicv5_get_gic(env); + GICv5IntType type =3D FIELD_EX64(value, GIC_CDEN, TYPE); + uint32_t id =3D FIELD_EX64(value, GIC_CDEN, ID); + bool virtual =3D false; + GICv5Domain domain =3D gicv5_current_phys_domain(env); + + gicv5_set_enabled(gic, id, true, domain, type, virtual); +} + static void gic_cdpri_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -64,6 +107,46 @@ static void gic_cdpri_write(CPUARMState *env, const ARM= CPRegInfo *ri, gicv5_set_priority(gic, id, priority, domain, type, virtual); } =20 +static void gic_cdaff_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + GICv5Common *gic =3D gicv5_get_gic(env); + uint32_t iaffid =3D FIELD_EX64(value, GIC_CDAFF, IAFFID); + GICv5RoutingMode irm =3D FIELD_EX64(value, GIC_CDAFF, IRM); + GICv5IntType type =3D FIELD_EX64(value, GIC_CDAFF, TYPE); + uint32_t id =3D FIELD_EX64(value, GIC_CDAFF, ID); + bool virtual =3D false; + GICv5Domain domain =3D gicv5_current_phys_domain(env); + + gicv5_set_target(gic, id, iaffid, irm, domain, type, virtual); +} + +static void gic_cdpend_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + GICv5Common *gic =3D gicv5_get_gic(env); + bool pending =3D FIELD_EX64(value, GIC_CDPEND, PENDING); + GICv5IntType type =3D FIELD_EX64(value, GIC_CDPEND, TYPE); + uint32_t id =3D FIELD_EX64(value, GIC_CDPEND, ID); + bool virtual =3D false; + GICv5Domain domain =3D gicv5_current_phys_domain(env); + + gicv5_set_pending(gic, id, pending, domain, type, virtual); +} + +static void gic_cdhm_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + GICv5Common *gic =3D gicv5_get_gic(env); + GICv5HandlingMode hm =3D FIELD_EX64(value, GIC_CDHM, HM); + GICv5IntType type =3D FIELD_EX64(value, GIC_CDAFF, TYPE); + uint32_t id =3D FIELD_EX64(value, GIC_CDAFF, ID); + bool virtual =3D false; + GICv5Domain domain =3D gicv5_current_phys_domain(env); + + gicv5_set_handling(gic, id, hm, domain, type, virtual); +} + static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { /* * Barrier: wait until the effects of a cpuif system register @@ -86,11 +169,36 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 0, .opc2 =3D 1, .access =3D PL1_W, .type =3D ARM_CP_NOP, }, + { .name =3D "GIC_CDDIS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .writefn =3D gic_cddis_write, + }, + { .name =3D "GIC_CDEN", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .writefn =3D gic_cden_write, + }, { .name =3D "GIC_CDPRI", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 2, .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, .writefn =3D gic_cdpri_write, }, + { .name =3D "GIC_CDAFF", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 3, + .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .writefn =3D gic_cdaff_write, + }, + { .name =3D "GIC_CDPEND", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 4, + .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .writefn =3D gic_cdpend_write, + }, + { .name =3D "GIC_CDHM", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .writefn =3D gic_cdhm_write, + }, }; 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610244; x=1775215044; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UVKXKj+EMraPZwBBktCBK5IhDrOS5hbt+kqBhK1xkvE=; b=gJfd9yUpkeBJ398W9L0HlHMk/EjEhxEu/7Kx76ZIKvlHTuZoJkZe2OmY3/tfGmfO+o CJm/JMTB/r7KxR7H8j2E5zxAeUgb2Eowvn7by90sVTdJSVOMcXbGT2IvxRCb0DY/pdGD rWthOXI4AP71qblYg2/0++SNv2z9zrK45+6h17Snqz00hEFBADDPMH9RcCxQgT5I6g8f jgSiIWuVefKeIN+02RGQbinnPXPxygn3/IKC6hRg4onyJzTQV6BoL/u7vEUeRSfB4LEj BA5JHP2wNf6wUrBiqi5kGvyUnOmFfNedGN3LeXOQEYZGc96Sp0Apj702ZRfefGXAbazj BhNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610244; x=1775215044; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=UVKXKj+EMraPZwBBktCBK5IhDrOS5hbt+kqBhK1xkvE=; b=QF69YwB8eII5iKlK/gFCVOuWAWBV2U7vIqztyfddtN/nSW7TWmEu9lr0pKrkF1riO7 ci5ANIWQj4P/gmtjT19ADba0lr4tMSgYUVAlB8NTsdJyvU+Trx9Wvg0oS2wKbb+5oM1t rmvg0ZuspWKQEVlEctC8RHXml5VM27EXWx7koxWfko+ysbDGFL42EhauP5k1n08NVbVK 3fs0JETwDHAfW7hge8H7mYNZsbsWnUChqDqUoPJ2k1U2VSOJj5PPO4ckI8SpVxf6GGRw dFXXZTerBLcsJ1ostTLjFA8DT1ar0xtJwqX8XlJkO9TzZdbAcx7TlPbOtfxvEJR46plL UPmw== X-Forwarded-Encrypted: i=1; AJvYcCVpSHaMvYsKuUkVCpSjtKRqN8wbPWmgRA7VsjG7AXpcboOX7Jd0WUcRINo7G1utYA6WuKFTVshZf//A@nongnu.org X-Gm-Message-State: AOJu0YxI5jHD9TuHk49sSIV9fFMw6WeO4bnisbN+/yd1rlVJ5FtKMQcr K3LRU9OET7JakpEOSZ10UeR4YbFxyg8OibSvnD7CFj/hzqFAU7CulObfQq03ptI228o= X-Gm-Gg: ATEYQzx+oA5buEoBiRiiPkFkFsHiEHjmFRwQaXd+py3c2iYewDWRYh/Z7ik3NPmIvFt 06754wlKqJVuI9o5DrclgNAGlgOcBIdlHeKAd38Sjo6xGRCBMy1xfYgGqn8dmwdXKSGuhWGWgNe SaDHKVDmQIg1EGfz7zjvBJYH94hvAzS7gxFJGGSYeKr+X94FDiCqhgWDFX5Y6tmYGV8Ypvi8GVk OWhHhLIDC+/Lku//DCdThvzOU9PJ5IkTS23jnVVJWLE9qT5533JmaODxLT0mujppgx2IHPYkVdn tRjbRifvpGPvK87TLuxHYjiY5gPcv9LNfuvn4pPQCIwx+5zP6Q2iJp19uWGdN/HebWslqNXg6oA /CLiwVKv3GcgazMxIp/+iDKqqqm0LsNy+HNw+nRU871vRZ3xeGDoJ/evlSPzjxaaxsWNrYyCR1s tCR0byHMonPGBytQ5QmZz83zXgmFact63NlRTjs/TfF11z5dayq5B63CwzN9F6N7O4yIkfgztOD CcxW5cQoMWRZ8VXinhTKhJajeNokZE= X-Received: by 2002:a05:600c:8b2a:b0:485:2c61:9457 with SMTP id 5b1f17b1804b1-48727d62cedmr34857025e9.10.1774610243959; Fri, 27 Mar 2026 04:17:23 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 23/65] hw/intc/arm_gicv5: Create backing state for SPIs Date: Fri, 27 Mar 2026 11:16:18 +0000 Message-ID: <20260327111700.795099-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610392948158500 Content-Type: text/plain; charset="utf-8" The GICv5 allows an IRS to implement SPIs, which are fixed-wire interrupts connected directly to the IRS. For QEMU we want to use these for all our traditional fixed-wire interrupt devices. (The other option the architecture permits is an Interrupt Wire Bridge (IWB), which converts from a fixed-wire interrupt to an interrupt event that is then translated through an ITS to send an LPI to the ITS -- this is much more complexity than we need or want.) SPI configuration is set via the same CPUIF instructions as LPI configuration. Create an array of structs which track the SPI state information listed in I_JVVTZ and I_BWPPP (ignoring for the moment the VM assignment state, which we will add when we add virtualization support). Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5_common.c | 30 ++++++++++++++++++++++++++++++ include/hw/intc/arm_gicv5_common.h | 27 +++++++++++++++++++++++++++ include/hw/intc/arm_gicv5_types.h | 14 ++++++++++++++ 3 files changed, 71 insertions(+) diff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c index 44909d1b05..79876c4401 100644 --- a/hw/intc/arm_gicv5_common.c +++ b/hw/intc/arm_gicv5_common.c @@ -66,6 +66,34 @@ static void gicv5_common_reset_hold(Object *obj, ResetTy= pe type) =20 memset(cs->irs_ist_baser, 0, sizeof(cs->irs_ist_baser)); memset(cs->irs_ist_cfgr, 0, sizeof(cs->irs_ist_cfgr)); + + if (cs->spi) { + GICv5Domain mp_domain; + + /* + * D_YGLYC, D_TVVRZ: SPIs reset to edge-triggered, inactive, + * idle, disabled, targeted routing mode, not assigned to a + * VM, and assigned to the most-privileged interrupt domain. + * Other state is UNKNOWN: we choose to zero it. + */ + memset(cs->spi, 0, cs->spi_irs_range * sizeof(*cs->spi)); + + /* + * The most-privileged interrupt domain is effectively the + * first in the list (EL3, S, NS) that we implement. + */ + if (gicv5_domain_implemented(cs, GICV5_ID_EL3)) { + mp_domain =3D GICV5_ID_EL3; + } else if (gicv5_domain_implemented(cs, GICV5_ID_S)) { + mp_domain =3D GICV5_ID_S; + } else { + mp_domain =3D GICV5_ID_NS; + } + + for (int i =3D 0; i < cs->spi_irs_range; i++) { + cs->spi[i].domain =3D mp_domain; + } + } } =20 static void gicv5_common_init(Object *obj) @@ -144,6 +172,8 @@ static void gicv5_common_realize(DeviceState *dev, Erro= r **errp) =20 address_space_init(&cs->dma_as, cs->dma, "gicv5-sysmem"); =20 + cs->spi =3D g_new0(GICv5SPIState, cs->spi_irs_range); + trace_gicv5_common_realize(cs->irsid, cs->num_cpus, cs->spi_base, cs->spi_irs_range, cs->spi_ra= nge); } diff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5= _common.h index 9bfafcebfc..d3f4999321 100644 --- a/include/hw/intc/arm_gicv5_common.h +++ b/include/hw/intc/arm_gicv5_common.h @@ -53,6 +53,25 @@ =20 OBJECT_DECLARE_TYPE(GICv5Common, GICv5CommonClass, ARM_GICV5_COMMON) =20 +/* + * This is where we store the state the IRS handles for an SPI. + * Generally this corresponds to the spec's list of state in I_JVVTZ + * and J_BWPPP. level is a QEMU implementation detail and is where we + * store the actual current state of the incoming qemu_irq line. + */ +typedef struct GICv5SPIState { + uint32_t iaffid; + uint8_t priority; + bool level; + bool pending; + bool active; + bool enabled; + GICv5HandlingMode hm; + GICv5RoutingMode irm; + GICv5TriggerMode tm; + GICv5Domain domain; +} GICv5SPIState; + /* * This class is for common state that will eventually be shared * between TCG and KVM implementations of the GICv5. @@ -65,6 +84,14 @@ struct GICv5Common { uint64_t irs_ist_baser[NUM_GICV5_DOMAINS]; uint32_t irs_ist_cfgr[NUM_GICV5_DOMAINS]; =20 + /* + * Pointer to an array of state information for the SPIs. Array + * element 0 is SPI ID s->spi_base, and there are s->spi_irs_range + * elements in total. SPI state is not per-domain: SPI is + * configurable to a particular domain via IRS_SPI_DOMAINR. + */ + GICv5SPIState *spi; + /* Bits here are set for each physical interrupt domain implemented */ uint8_t implemented_domains; =20 diff --git a/include/hw/intc/arm_gicv5_types.h b/include/hw/intc/arm_gicv5_= types.h index 20de5b3f46..f6f8709a6a 100644 --- a/include/hw/intc/arm_gicv5_types.h +++ b/include/hw/intc/arm_gicv5_types.h @@ -70,4 +70,18 @@ typedef enum GICv5RoutingMode { GICV5_1OFN =3D 1, } GICv5RoutingMode; =20 +/* + * Interrupt trigger mode (same encoding as IRS_SPI_CFGR.TM) Note that + * this is not the same thing as handling mode, even though the two + * possible states have the same names. Trigger mode applies only for + * SPIs and tells the IRS what kinds of changes to the input signal + * wire should make it generate SET and CLEAR events. Handling mode + * affects whether the pending state of an interrupt is cleared when + * the interrupt is acknowledged, and applies to both SPIs and LPIs. + */ +typedef enum GICv5TriggerMode { + GICV5_TRIGGER_EDGE =3D 0, + GICV5_TRIGGER_LEVEL =3D 1, +} GICv5TriggerMode; + #endif --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610759; cv=none; d=zohomail.com; s=zohoarc; b=A28HqxVvjh3cW1rwZ2KEdYgDZ4QijmUAqOO6CI79TLnz1+H+ck4pVeiNFVXVaT2WHwUj6xtww24DNloiiudEExvFKWMa2P/zV4qcpN6BG7unEz73t1JE7SVXTlsBMHECWeH5IZ4uMMpL0bOQs6fp5ISBWCL/WV7XTFQB3ZtO90Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610759; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ZYcKb44qcAOTmabDFzYmilElxXC21N5X3c+i6UPowFQ=; b=D+uKgzdh8Ei9Fy/gM0HyjteQhxJCAfH8GR4x080wHafGylB+0pOSIyTs8FSDxQopQB48X71pnouzox2CJb3uqeIpCNInOR998LQZFj8qCFnvMpoPtMjDAfBMv+qPiWqTuSWtLWEafsyBLU0jBZNblHVAdzKOP7uKxCKgrnvrQkQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610759492110.04530307291941; Fri, 27 Mar 2026 04:25:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65C1-0006lF-Ke; Fri, 27 Mar 2026 07:17:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65Bw-0006eC-Kq for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:28 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65Bu-0007xa-MQ for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:28 -0400 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-439b2965d4bso1506705f8f.2 for ; Fri, 27 Mar 2026 04:17:26 -0700 (PDT) Received: from lanath.. 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Instead of ignoring the GICV5_SPI type in gicv5_set_priority() and friends, update the state in our SPI state array. Signed-off-by: Peter Maydell --- hw/intc/arm_gicv5.c | 64 ++++++++++++++++++++++++++++++ include/hw/intc/arm_gicv5_common.h | 40 +++++++++++++++++++ 2 files changed, 104 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index d1eb96fce0..9ca1826253 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -490,6 +490,19 @@ void gicv5_set_priority(GICv5Common *cs, uint32_t id, = uint8_t priority, put_l2_iste(cs, cfg, &h); break; } + case GICV5_SPI: + { + GICv5SPIState *spi =3D gicv5_spi_state(cs, id, domain); + + if (!spi) { + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_priority: tried to s= et " + "priority of unreachable SPI %d\n", id); + return; + } + + spi->priority =3D priority; + break; + } default: qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_priority: tried to set " "priority of bad interrupt type %d\n", type); @@ -524,6 +537,19 @@ void gicv5_set_enabled(GICv5Common *cs, uint32_t id, b= ool enabled, put_l2_iste(cs, cfg, &h); break; } + case GICV5_SPI: + { + GICv5SPIState *spi =3D gicv5_spi_state(cs, id, domain); + + if (!spi) { + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_enabled: tried to se= t " + "enable state of unreachable SPI %d\n", id); + return; + } + + spi->enabled =3D true; + break; + } default: qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_enabled: tried to set " "enable state of bad interrupt type %d\n", type); @@ -558,6 +584,19 @@ void gicv5_set_pending(GICv5Common *cs, uint32_t id, b= ool pending, put_l2_iste(cs, cfg, &h); break; } + case GICV5_SPI: + { + GICv5SPIState *spi =3D gicv5_spi_state(cs, id, domain); + + if (!spi) { + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_pending: tried to se= t " + "pending state of unreachable SPI %d\n", id); + return; + } + + spi->pending =3D true; + break; + } default: qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_pending: tried to set " "pending state of bad interrupt type %d\n", type); @@ -593,6 +632,18 @@ void gicv5_set_handling(GICv5Common *cs, uint32_t id, put_l2_iste(cs, cfg, &h); break; } + case GICV5_SPI: + { + GICv5SPIState *spi =3D gicv5_spi_state(cs, id, domain); + + if (!spi) { + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_handling: tried to s= et " + "priority of unreachable SPI %d\n", id); + } + + spi->hm =3D handling; + break; + } default: qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_handling: tried to set " "handling mode of bad interrupt type %d\n", type); @@ -642,6 +693,19 @@ void gicv5_set_target(GICv5Common *cs, uint32_t id, ui= nt32_t iaffid, put_l2_iste(cs, cfg, &h); break; } + case GICV5_SPI: + { + GICv5SPIState *spi =3D gicv5_spi_state(cs, id, domain); + + if (!spi) { + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_target: tried to set= " + "target of unreachable SPI %d\n", id); + return; + } + + spi->iaffid =3D iaffid; + break; + } default: qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_target: tried to set " "target of bad interrupt type %d\n", type); diff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5= _common.h index d3f4999321..a81c941765 100644 --- a/include/hw/intc/arm_gicv5_common.h +++ b/include/hw/intc/arm_gicv5_common.h @@ -189,4 +189,44 @@ static inline bool gicv5_domain_implemented(GICv5Commo= n *cs, GICv5Domain domain) */ const char *gicv5_class_name(void); =20 +/** + * gicv5_raw_spi_state + * @cs: GIC object + * @id: INTID of SPI to look up + * + * Return pointer to the GICv5SPIState for this SPI, or NULL if the + * interrupt ID is out of range. This does not do a check that the SPI + * is assigned to the right domain: generally you should call it via + * some other wrapper that performs an appropriate further check. + */ +static inline GICv5SPIState *gicv5_raw_spi_state(GICv5Common *cs, uint32_t= id) +{ + if (id < cs->spi_base || id >=3D cs->spi_base + cs->spi_irs_range) { + return NULL; + } + + return cs->spi + (id - cs->spi_base); +} + +/** + * gicv5_spi_state: + * @cs: GIC object + * @id: INTID of SPI to look up + * @domain: domain to check + * + * Return pointer to the GICv5SPIState for this SPI, or NULL if the + * interrupt is unreachable (which can be because the INTID is out of + * range, or because the SPI is configured for a different domain). + */ +static inline GICv5SPIState *gicv5_spi_state(GICv5Common *cs, uint32_t id, + GICv5Domain domain) +{ + GICv5SPIState *spi =3D gicv5_raw_spi_state(cs, id); + + if (!spi || spi->domain !=3D domain) { + return NULL; + } + return spi; +} + #endif --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610547; cv=none; d=zohomail.com; s=zohoarc; b=Yt1w0ya1BoEuJeCc0OsBt72OU6vBiIoa9dPxakARYLuaw+ywB1WMko/OHoYXPkZ0MFAxPYPVkTEbwQ2If5U379LDE03mL+tBA5Tmkl2U5wDL8sB3phgAtOXtEkE3qpJmYrsA8VlkCtM//Y3OrW5X+AWz79QSllmaoM8xQDHC7ts= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610547; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=JpR31boHFrDIOvEfT0ZIVwsIEVw9EEegLZSAQPBvMFc=; b=hrzvPLmrDAZxf4uqIPDtWhAQpPBuGSDx49ejrCfduKZa30WD+wi81oemKlbldRfh6zNzJxbCSoaiUiRup+iC8jinAVTAe0nt+UeJZllJhBk6aTPDxiC2k44WyB65BBS0PjygPmtoQtzeyya2ABSIQ2sDQ3hk26OY+I7R8z3gucg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610547755911.5736095178377; Fri, 27 Mar 2026 04:22:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65C3-0006nR-AK; Fri, 27 Mar 2026 07:17:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65Bx-0006gX-NJ for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:30 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65Bv-0007yC-Fn for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:29 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-48558d6ef83so18687375e9.3 for ; Fri, 27 Mar 2026 04:17:27 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610246; x=1775215046; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JpR31boHFrDIOvEfT0ZIVwsIEVw9EEegLZSAQPBvMFc=; b=BqguwpEnLEBI9Fn1Va7HgOM9555THo9ldjumgnEPOry8w60VnvZRYcM8tMaVyw1fMf rO3aqS/j8+Fb3Q8V7c604txgesrULCBe9EPFmaCqP+6euFpN/FZyelIXhV00KlM7/fy2 S0kjDATPdpYaPGlbCihw3NqLwKcPUrc1blqS0mXuAQxa/62ODBlzRNY9vqGm7b1Ly63Y aov20Dpw9nJef/UnP5XqShA2K9T6d7XHC6O+OtRp+uLQ7mKvJ5rjowEw0Fdl7r9SI6XC SM2YzFPHDWGK6aOYorFKmR0efTpBLfUc9pOEs0ZwOGgaISFFHL3PAJVkmm8yUI/VIW+1 JIIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610246; x=1775215046; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=JpR31boHFrDIOvEfT0ZIVwsIEVw9EEegLZSAQPBvMFc=; b=nKoNQBZwBdfO1mHMmwjZJv9t+AEMaefhw1yiq++1rHA5KS97+jiP3DEo5M6TMoER7T IeNHuvRDFYitntFa+2rh++5dBo2FBtg9nrX99jIzmQv56h3tLgNmVvOo1EQ43D/IS8qO YtbQRWQFAoK538MB2692jXrWkdaac1rYo3RfuXKxASLE4Trpp4+MBm/ceNSHonFOXWO3 16X3GOdWO8/PjbUFhqXx/N+lQKoAtiZZwVw3UCIk5Mevk+qG+0JO4K20re3dYoePK3NB FdXh46RZIuE5BGP1eoO1CM3Tv62wUjMbXsk6v4aATSTzlUnYiPIXeuDA+lkQX69My9y4 pBiA== X-Forwarded-Encrypted: i=1; AJvYcCVbtsctMZK4weW+BKiCUk3nfgL4lJqxkZ2B+re4kMaltUEXMq3YNeEmfELFbFfM60jIx+C7fvilKw8l@nongnu.org X-Gm-Message-State: AOJu0YxQKWZSaZIlGV/4HRYuMiLAFCRCUmg+qsaFWJZuaJijgidUwmdM /rDtPYedWMCONqlvTZY9QVh7rtGEKs1t+nvSv42nScxLxoG2fViAH44tUxKV035nfcU= X-Gm-Gg: ATEYQzxY/HAU0toKmnHIrxp80A3yiuU1EIVOkax5wqTHcVtL3o1vFRbOtxN9Wz92nP5 6wIyLB5thKL/kEFvR/apIvvacQbXnPjho6lvEgf4Psko6oZK1n3FboJ2zSv+cbgvLS25JaVRGio cxIi+qYkb9kA6ZfwNf4mCwCBQThM6y7a5+Qr7yvJ+NT9iryHxk0yGSzfMA9zNpaXUnMWWs5uNMO TCRkOhFQGw91cvgD6Yhc+2haULyr8wLadwf7FvvIBz66HmdiwZiwGxnRmD57H3YfuFLC/tZyA3p a538ZgWP/jEoh/K2Wx9/I1VNrw8Faxlhy8YvvvAC/hDYvhr2cGHcjrBSE6/5ei9M500uKvxUSDr cNVidvwewUskX+ZVTNTGT5qDErqNwg/O4ZKGHhEcqxRGdwgyOf1IIJegqC7qQ1xVvN5przI8x8X 35S+5IMBuMr9gLn+2YUlPBn70Q8zUefSwB7LnDYOV7enBY4TmWOMKKxeWeZzzi0lK7CBbo+2Kzl /FwjEjQYrZ11g0oiqCMsQ5tgcRQyjo= X-Received: by 2002:a05:600c:46c5:b0:485:39d1:b4dd with SMTP id 5b1f17b1804b1-48727ef0bcemr34056815e9.10.1774610245870; Fri, 27 Mar 2026 04:17:25 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 25/65] hw/intc/arm_gicv5: Implement gicv5_request_config() Date: Fri, 27 Mar 2026 11:16:20 +0000 Message-ID: <20260327111700.795099-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610550725154100 Content-Type: text/plain; charset="utf-8" Implement the gicv5_request_config() function, which corresponds to the RequestConfig command and its RequestConfigAck reply. We provide read_l2_iste() as a separate function to keep the "access the in-guest-memory data structure" layer separate from the "operate on the L2_ISTE values" layer. Signed-off-by: Peter Maydell --- hw/intc/arm_gicv5.c | 102 +++++++++++++++++++++++++++++ hw/intc/trace-events | 1 + include/hw/intc/arm_gicv5_stream.h | 24 +++++++ 3 files changed, 127 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 9ca1826253..04d4391ae5 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -297,6 +297,19 @@ FIELD(L2_ISTE, HWU, 9, 2) FIELD(L2_ISTE, PRIORITY, 11, 5) FIELD(L2_ISTE, IAFFID, 16, 16) =20 +/* + * Format used for gicv5_request_config() return value, which matches + * the ICC_ICSR_EL1 bit layout. + */ +FIELD(ICSR, F, 0, 1) +FIELD(ICSR, ENABLED, 1, 1) +FIELD(ICSR, PENDING, 2, 1) +FIELD(ICSR, IRM, 3, 1) +FIELD(ICSR, ACTIVE, 4, 1) +FIELD(ICSR, HM, 5, 1) +FIELD(ICSR, PRIORITY, 11, 5) +FIELD(ICSR, IAFFID, 32, 16) + static MemTxAttrs irs_txattrs(GICv5Common *cs, GICv5Domain domain) { /* @@ -713,6 +726,95 @@ void gicv5_set_target(GICv5Common *cs, uint32_t id, ui= nt32_t iaffid, } } =20 +static uint64_t l2_iste_to_icsr(GICv5Common *cs, const GICv5ISTConfig *cfg, + uint32_t id) +{ + uint64_t icsr =3D 0; + const uint32_t *l2_iste_p; + L2_ISTE_Handle h; + + l2_iste_p =3D get_l2_iste(cs, cfg, id, &h); + if (!l2_iste_p) { + return R_ICSR_F_MASK; + } + + /* + * The field locations in the L2 ISTE do not line up with the + * corresponding fields in the ICC_ICSR_EL1 register, so we need + * to extract and deposit them individually. + */ + icsr =3D FIELD_DP64(icsr, ICSR, F, 0); + icsr =3D FIELD_DP64(icsr, ICSR, ENABLED, FIELD_EX32(*l2_iste_p, L2_IST= E, ENABLE)); + icsr =3D FIELD_DP64(icsr, ICSR, PENDING, FIELD_EX32(*l2_iste_p, L2_IST= E, PENDING)); + icsr =3D FIELD_DP64(icsr, ICSR, IRM, FIELD_EX32(*l2_iste_p, L2_ISTE, I= RM)); + icsr =3D FIELD_DP64(icsr, ICSR, ACTIVE, FIELD_EX32(*l2_iste_p, L2_ISTE= , ACTIVE)); + icsr =3D FIELD_DP64(icsr, ICSR, HM, FIELD_EX32(*l2_iste_p, L2_ISTE, HM= )); + icsr =3D FIELD_DP64(icsr, ICSR, PRIORITY, FIELD_EX32(*l2_iste_p, L2_IS= TE, PRIORITY)); + icsr =3D FIELD_DP64(icsr, ICSR, IAFFID, FIELD_EX32(*l2_iste_p, L2_ISTE= , IAFFID)); + + return icsr; +} + +static uint64_t spi_state_to_icsr(GICv5SPIState *spi) +{ + uint64_t icsr =3D 0; + + icsr =3D FIELD_DP64(icsr, ICSR, F, 0); + icsr =3D FIELD_DP64(icsr, ICSR, ENABLED, spi->enabled); + icsr =3D FIELD_DP64(icsr, ICSR, PENDING, spi->pending); + icsr =3D FIELD_DP64(icsr, ICSR, IRM, spi->irm); + icsr =3D FIELD_DP64(icsr, ICSR, ACTIVE, spi->active); + icsr =3D FIELD_DP64(icsr, ICSR, HM, spi->hm); + icsr =3D FIELD_DP64(icsr, ICSR, PRIORITY, spi->priority); + icsr =3D FIELD_DP64(icsr, ICSR, IAFFID, spi->iaffid); + + return icsr; +} + +uint64_t gicv5_request_config(GICv5Common *cs, uint32_t id, GICv5Domain do= main, + GICv5IntType type, bool virtual) +{ + GICv5 *s =3D ARM_GICV5(cs); + uint64_t icsr; + + if (virtual) { + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_request_config: tried to " + "read config of a virtual interrupt\n"); + return R_ICSR_F_MASK; + } + + switch (type) { + case GICV5_LPI: + { + const GICv5ISTConfig *cfg =3D &s->phys_lpi_config[domain]; + + icsr =3D l2_iste_to_icsr(cs, cfg, id); + trace_gicv5_request_config(domain_name[domain], inttype_name(type), + virtual, id, icsr); + return icsr; + } + case GICV5_SPI: + { + GICv5SPIState *spi =3D gicv5_spi_state(cs, id, domain); + + if (!spi) { + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_request_config: tried to= " + "read config of unreachable SPI %d\n", id); + return R_ICSR_F_MASK; + } + + icsr =3D spi_state_to_icsr(spi); + trace_gicv5_request_config(domain_name[domain], inttype_name(type), + virtual, id, icsr); + return icsr; + } + default: + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_request_config: tried to " + "read config of bad interrupt type %d\n", type); + return R_ICSR_F_MASK; + } +} + static void irs_map_l2_istr_write(GICv5 *s, GICv5Domain domain, uint64_t v= alue) { GICv5Common *cs =3D ARM_GICV5_COMMON(s); diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 37ca6e8e12..409935e15a 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -240,6 +240,7 @@ gicv5_set_enabled(const char *domain, const char *type,= bool virtual, uint32_t i gicv5_set_pending(const char *domain, const char *type, bool virtual, uint= 32_t id, bool pending) "GICv5 IRS SetPending %s %s virtual:%d ID %u pending= %d" gicv5_set_handling(const char *domain, const char *type, bool virtual, uin= t32_t id, int handling) "GICv5 IRS SetHandling %s %s virtual:%d ID %u handl= ing %d" gicv5_set_target(const char *domain, const char *type, bool virtual, uint3= 2_t id, uint32_t iaffid, int irm) "GICv5 IRS SetTarget %s %s virtual:%d ID = %u IAFFID %u routingmode %d" +gicv5_request_config(const char *domain, const char *type, bool virtual, u= int32_t id, uint64_t icsr) "GICv5 IRS RequestConfig %s %s virtual:%d ID %u = ICSR 0x%" PRIx64 =20 # arm_gicv5_common.c gicv5_common_realize(uint32_t irsid, uint32_t num_cpus, uint32_t spi_base,= uint32_t spi_irs_range, uint32_t spi_range) "GICv5 IRS realized: IRS ID %u= , %u CPUs, SPI base %u, SPI IRS range %u, SPI range %u" diff --git a/include/hw/intc/arm_gicv5_stream.h b/include/hw/intc/arm_gicv5= _stream.h index af2e1851c2..670423fdad 100644 --- a/include/hw/intc/arm_gicv5_stream.h +++ b/include/hw/intc/arm_gicv5_stream.h @@ -126,4 +126,28 @@ void gicv5_set_handling(GICv5Common *cs, uint32_t id, void gicv5_set_target(GICv5Common *cs, uint32_t id, uint32_t iaffid, GICv5RoutingMode irm, GICv5Domain domain, GICv5IntType type, bool virtual); + +/** + * gicv5_request_config + * @cs: GIC IRS to send command to + * @id: interrupt ID + * @domain: interrupt domain to act on + * @type: interrupt type (LPI or SPI) + * @virtual: true if this is a virtual interrupt + * + * Query the current configuration of an interrupt; matches stream + * interface RequestConfig command from CPUIF to IRS and the + * RequestConfigAck reply to it. + * + * In the real stream protocol, the RequestConfigAck packet has the + * same information as the register but in a different order; we use + * the register order, not the packet order, so we don't need to + * unpack and repack in the cpuif. + * + * Returns: the config of the interrupt, in the format used by + * ICC_ICSR_EL1. + */ +uint64_t gicv5_request_config(GICv5Common *cs, uint32_t id, GICv5Domain do= main, + GICv5IntType type, bool virtual); + #endif --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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We mark ICC_ICSR_EL1 as ARM_CP_NO_RAW, because we do not want to have this migrated as part of the generic "system register" migration arrays. Instead we will do migration via a GICv5 cpuif vmstate section. This is necessary because some of the cpuif registers are banked by interrupt domain and so need special handling to migrate the data in all the banks; it's also how we handle the gicv3 cpuif registers. (We expect that KVM also will expose the cpuif registers via GIC-specific ioctls rather than as generic sysregs.) We'll mark all the GICv5 sysregs as NO_RAW. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- target/arm/cpu.h | 5 +++++ target/arm/tcg/gicv5-cpuif.c | 27 +++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 16de0ebfa8..1fdfd91ba4 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -597,6 +597,11 @@ typedef struct CPUArchState { uint64_t vmecid_a_el2; } cp15; =20 + struct { + /* GICv5 CPU interface data */ + uint64_t icc_icsr_el1; + } gicv5_cpuif; + struct { /* M profile has up to 4 stack pointers: * a Main Stack Pointer and a Process Stack Pointer for each diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 0c4349f8a7..8cf09791c1 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -35,6 +35,9 @@ FIELD(GIC_CDHM, ID, 0, 24) FIELD(GIC_CDHM, TYPE, 29, 3) FIELD(GIC_CDHM, HM, 32, 1) =20 +FIELD(GIC_CDRCFG, ID, 0, 24) +FIELD(GIC_CDRCFG, TYPE, 29, 3) + static GICv5Common *gicv5_get_gic(CPUARMState *env) { return env->gicv5state; @@ -134,6 +137,19 @@ static void gic_cdpend_write(CPUARMState *env, const A= RMCPRegInfo *ri, gicv5_set_pending(gic, id, pending, domain, type, virtual); } =20 +static void gic_cdrcfg_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + GICv5Common *gic =3D gicv5_get_gic(env); + GICv5IntType type =3D FIELD_EX64(value, GIC_CDRCFG, TYPE); + uint32_t id =3D FIELD_EX64(value, GIC_CDRCFG, ID); + bool virtual =3D false; + GICv5Domain domain =3D gicv5_current_phys_domain(env); + + env->gicv5_cpuif.icc_icsr_el1 =3D + gicv5_request_config(gic, id, domain, type, virtual); +} + static void gic_cdhm_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -194,11 +210,22 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, .writefn =3D gic_cdpend_write, }, + { .name =3D "GIC_CDRCFG", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 5, + .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .writefn =3D gic_cdrcfg_write, + }, { .name =3D "GIC_CDHM", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 2, .opc2 =3D 1, .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, .writefn =3D gic_cdhm_write, }, + { .name =3D "ICC_ICSR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 10, .opc2 =3D 4, + .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, + .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.icc_icsr_el1), + .resetvalue =3D 0, + }, }; =20 void define_gicv5_cpuif_regs(ARMCPU *cpu) --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610521134850.9723294053571; Fri, 27 Mar 2026 04:22:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65C4-0006og-8E; Fri, 27 Mar 2026 07:17:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65C0-0006it-As for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:32 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65By-0007zV-Ch for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:32 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-486fc4725f0so17971895e9.1 for ; Fri, 27 Mar 2026 04:17:29 -0700 (PDT) Received: from lanath.. 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The way these work is that the guest writes the ID of the interrupt it wants to configure to IRS_SPI_SELR, and then it can read and write the trigger mode of that SPI via IRS_SPI_CFGR and the domain via IRS_SPI_DOMAINR. IRS_SPI_STATUSR has a bit to indicate whether the SPI is valid, and the usual IDLE bit to allow for non-instantaneous updates (which QEMU doesn't do). Since the only domain which can configure the domain of an SPI is EL3 and our initial implementation is NS-only, technically the DOMAINR handling is unused code. However it is straightforward, being almost the same as the CFGR handling, and we'll need it later on. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5.c | 68 ++++++++++++++++++++++++++++++ hw/intc/arm_gicv5_common.c | 9 ++++ include/hw/intc/arm_gicv5_common.h | 1 + 3 files changed, 78 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 04d4391ae5..6ff3a79745 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -310,6 +310,22 @@ FIELD(ICSR, HM, 5, 1) FIELD(ICSR, PRIORITY, 11, 5) FIELD(ICSR, IAFFID, 32, 16) =20 +static GICv5SPIState *spi_for_selr(GICv5Common *cs, GICv5Domain domain) +{ + /* + * If the IRS_SPI_SELR value specifies an SPI that can be managed in + * this domain, return a pointer to its GICv5SPIState; otherwise + * return NULL. + */ + uint32_t id =3D FIELD_EX32(cs->irs_spi_selr[domain], IRS_SPI_SELR, ID); + GICv5SPIState *spi =3D gicv5_raw_spi_state(cs, id); + + if (spi && (domain =3D=3D GICV5_ID_EL3 || domain =3D=3D spi->domain)) { + return spi; + } + return NULL; +} + static MemTxAttrs irs_txattrs(GICv5Common *cs, GICv5Domain domain) { /* @@ -1010,6 +1026,38 @@ static bool config_readl(GICv5 *s, GICv5Domain domai= n, hwaddr offset, case A_IRS_IST_CFGR: *data =3D cs->irs_ist_cfgr[domain]; return true; + + case A_IRS_SPI_STATUSR: + /* + * QEMU writes to IRS_SPI_{CFGR,DOMAINR,SELR,VMR} take effect + * instantaneously, so the guest can never see the IDLE bit as 0. + */ + v =3D FIELD_DP32(v, IRS_SPI_STATUSR, V, + spi_for_selr(cs, domain) !=3D NULL); + v =3D FIELD_DP32(v, IRS_SPI_STATUSR, IDLE, 1); + *data =3D v; + return true; + + case A_IRS_SPI_CFGR: + { + GICv5SPIState *spi =3D spi_for_selr(cs, domain); + + if (spi) { + v =3D FIELD_DP32(v, IRS_SPI_CFGR, TM, spi->tm); + } + *data =3D v; + return true; + } + case A_IRS_SPI_DOMAINR: + if (domain =3D=3D GICV5_ID_EL3) { + /* This is RAZ/WI except for the EL3 domain */ + GICv5SPIState *spi =3D spi_for_selr(cs, domain); + if (spi) { + v =3D FIELD_DP32(v, IRS_SPI_DOMAINR, DOMAIN, spi->domain); + } + } + *data =3D v; + return true; } =20 return false; @@ -1041,6 +1089,26 @@ static bool config_writel(GICv5 *s, GICv5Domain doma= in, hwaddr offset, case A_IRS_MAP_L2_ISTR: irs_map_l2_istr_write(s, domain, data); return true; + case A_IRS_SPI_SELR: + cs->irs_spi_selr[domain] =3D data; + return true; + case A_IRS_SPI_CFGR: + { + GICv5SPIState *spi =3D spi_for_selr(cs, domain); + if (spi) { + spi->tm =3D FIELD_EX32(data, IRS_SPI_CFGR, TM); + } + return true; + } + case A_IRS_SPI_DOMAINR: + if (domain =3D=3D GICV5_ID_EL3) { + /* this is RAZ/WI except for the EL3 domain */ + GICv5SPIState *spi =3D spi_for_selr(cs, domain); + if (spi) { + spi->domain =3D FIELD_EX32(data, IRS_SPI_DOMAINR, DOMAIN); + } + } + return true; } =20 return false; diff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c index 79876c4401..0813f0ac66 100644 --- a/hw/intc/arm_gicv5_common.c +++ b/hw/intc/arm_gicv5_common.c @@ -94,6 +94,15 @@ static void gicv5_common_reset_hold(Object *obj, ResetTy= pe type) cs->spi[i].domain =3D mp_domain; } } + + for (int i =3D 0; i < NUM_GICV5_DOMAINS; i++) { + /* + * We reset irs_spi_selr to an invalid value so that our reset + * value for IRS_SPI_STATUSR.V is correctly 0. The guest can + * never read IRS_SPI_SELR directly. + */ + cs->irs_spi_selr[i] =3D cs->spi_base + cs->spi_irs_range; + } } =20 static void gicv5_common_init(Object *obj) diff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5= _common.h index a81c941765..61d017bf38 100644 --- a/include/hw/intc/arm_gicv5_common.h +++ b/include/hw/intc/arm_gicv5_common.h @@ -83,6 +83,7 @@ struct GICv5Common { =20 uint64_t irs_ist_baser[NUM_GICV5_DOMAINS]; uint32_t irs_ist_cfgr[NUM_GICV5_DOMAINS]; + uint32_t irs_spi_selr[NUM_GICV5_DOMAINS]; =20 /* * Pointer to an array of state information for the SPIs. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610249; x=1775215049; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xoyJziqdU/nken6or35eJw+c9H0GsrA0zPSsjs/9kKo=; b=wfEpRQj4+ZOWYQ/QpxkjZZo21umgPIEahwTvgyCVul4CY72Y1FKsDaIHW8FCQCBfYm THzE4jrJmrcrx4XS84j0ecrmmSXPeEypgW/5LGia0sADvV1J1TFoWeLSYT3cvDXrzPkF WSIJ6lWlskUr9jqLAZ5CQQND10SXbe8CJE5hjY3R4WHftGLK8274CiURaEWmVx73p6w3 hOF3VVdxja0xF1K4cJon+39PNachpbWzwBSguvxfDxcI64P77LwHZDxaum6jGmOFahjX 6RgI6jcyUNdQzhlpUtWk7hmxzUlh34ZiDd+meEiuxq3fG+eph15quS29e30+c0ugjuwR FEww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610249; x=1775215049; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=xoyJziqdU/nken6or35eJw+c9H0GsrA0zPSsjs/9kKo=; b=KR2QEJ8mCMFznnrgIHMI1gMNRjy47q8hvfDrSrqXP1V05D/8a6rnu1Yg9K1z5cmnd4 gU4B1F0IpsRXlHgYFZpFExa9T5OiFdjH/tuOPy1g3724iQiRgmdY/vOUHEQlNUM8NMW6 5619VURjjXixP1N+GoXUZJpD4WRTeuupCUWPpo+fUKvi+BtfHjsGV/rFDQSpHQZ7fHyK zZtLeGEXPCqhgYIlQ47+x4cYmQXJ0KooKoVB+EDMvCRd3+kKK8NKDXLMcfbyhNqu3r5N oUMEkAqM6eLr073YQ+1DYPtWVsOaQPndrPfEwMudruzgtg5ejHGk8AQj3c2gJ17MmyXn g3Pg== X-Forwarded-Encrypted: i=1; AJvYcCXFhKQ9ptDNpNbUEYO9KjdMCVh7ZywmYj0tEslWp/KLNxb3Ofr90WWyVvTFWjwE0Dx/9sxqza7WliSp@nongnu.org X-Gm-Message-State: AOJu0YyhlH9YRSG5cYu+IrEYILTDH+Z+/+Ya3K9z5dDoaazIQhBO3J+y ylEzACEVInAWcUqpM9Fds2rqkb0i0e7hQ0W3u0o/1bejKZEjZnWizEYJBTJ/XKgRuKE= X-Gm-Gg: ATEYQzxlWrye7sAbSQRxy+pkZMZ3TWauGyDFPsOzBA4gArNWE/icFSZ8haHqF9Sm3R3 FI3QQN9M4/8PjGzbFglV/n71wfwqkPtYVmx7q74BROS5b+WtMUl7e0azWd7Mw3Ooqt7iveZjMip veTTvx6KOpkTj/n90DwqiCrawTpANMldbc6sMat2d2D30x2AHz3PyikqoCExh5/YvDGq1VzbsF5 CD0hpKkivc6Hqpn++2wdgbQaYiejplWhv8LLTGWPd4vZGEQONrYMJbVohcFVZxw4CVv9j30ipla NF9RXlkpqx6SDGcWroGhH4SrO4TOFU5FOrG/P/fzMOU9CXPcauPnoJ736MdLizl/x1N95hrDk8l OwHf92CF4bodH2TsdDU3duHrmM9YYoUnb4pw4gOpoKjL2ausoALOMyjMAhAnPA0IcPXpf7CBrk8 7ZNA48PAxYSgLxTkMjB31E9KTQlAuvANjQc/V/fl3nVYvKD6WtvTp8ZmhKDLQxolmhhDD20/N1P BONKW9vOromS3Ct6wTOAgRntlYIE+rzC307pFfNDw== X-Received: by 2002:a05:6000:220c:b0:439:ca7b:f4b with SMTP id ffacd0b85a97d-43b9ea77996mr3253924f8f.50.1774610248816; Fri, 27 Mar 2026 04:17:28 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 28/65] hw/intc/arm_gicv5: Update SPI state for CLEAR/SET events Date: Fri, 27 Mar 2026 11:16:23 +0000 Message-ID: <20260327111700.795099-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610284221154100 Content-Type: text/plain; charset="utf-8" When an SPI irq line changes level, this causes what the spec describes as SET_LEVEL, SET_EDGE or CLEAR events. These also happen when the trigger mode is reconfigured, or when software requests a manual resample via the IRS_SPI_RESAMPLER register. SET_LEVEL and SET_EDGE events make the interrupt pending, and update its handler mode to match its trigger mode. CLEAR events make the interrupt no longer pending. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5.c | 59 ++++++++++++++++++++++++++++++++++++++++++++ hw/intc/trace-events | 1 + 2 files changed, 60 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 6ff3a79745..bc887233f5 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -946,6 +946,28 @@ static void irs_ist_baser_write(GICv5 *s, GICv5Domain = domain, uint64_t value) } } =20 +static void spi_sample(GICv5SPIState *spi) +{ + /* + * Sample the state of the SPI input line; this generates + * SET_EDGE, SET_LEVEL or CLEAR events which update the SPI's + * pending state and handling mode per R_HHKMN. The logic is the + * same for "the input line changed" (R_QBXXV) and "software asked + * us to resample" (R_DMTFM). + */ + if (spi->level) { + /* + * SET_LEVEL or SET_EDGE: interrupt becomes pending, and the + * handling mode is updated to match the trigger mode. + */ + spi->pending =3D true; + spi->hm =3D spi->tm =3D=3D GICV5_TRIGGER_EDGE ? GICV5_EDGE : GICV5= _LEVEL; + } else if (spi->tm =3D=3D GICV5_TRIGGER_LEVEL) { + /* falling edges only trigger a CLEAR event for level-triggered */ + spi->pending =3D false; + } +} + static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset, uint64_t *data, MemTxAttrs attrs) { @@ -1096,7 +1118,24 @@ static bool config_writel(GICv5 *s, GICv5Domain doma= in, hwaddr offset, { GICv5SPIState *spi =3D spi_for_selr(cs, domain); if (spi) { + GICv5TriggerMode old_tm =3D spi->tm; spi->tm =3D FIELD_EX32(data, IRS_SPI_CFGR, TM); + if (spi->tm !=3D old_tm) { + /* + * R_KBPXL: updates to SPI trigger mode can generate CLEAR= or + * SET_LEVEL events. This is not the same logic as spi_sam= ple(). + */ + if (spi->tm =3D=3D GICV5_TRIGGER_LEVEL) { + if (spi->level) { + spi->pending =3D true; + spi->hm =3D GICV5_LEVEL; + } else { + spi->pending =3D false; + } + } else if (spi->level) { + spi->pending =3D false; + } + } } return true; } @@ -1109,6 +1148,17 @@ static bool config_writel(GICv5 *s, GICv5Domain doma= in, hwaddr offset, } } return true; + case A_IRS_SPI_RESAMPLER: + { + uint32_t id =3D FIELD_EX32(data, IRS_SPI_RESAMPLER, SPI_ID); + GICv5SPIState *spi =3D gicv5_spi_state(cs, id, domain); + + if (spi) { + spi_sample(spi); + } + trace_gicv5_spi_state(id, spi->level, spi->pending, spi->active); + return true; + } } =20 return false; @@ -1259,8 +1309,17 @@ static void gicv5_set_spi(void *opaque, int irq, int= level) /* These irqs are all SPIs; the INTID is irq + s->spi_base */ GICv5Common *cs =3D ARM_GICV5_COMMON(opaque); uint32_t spi_id =3D irq + cs->spi_base; + GICv5SPIState *spi =3D gicv5_raw_spi_state(cs, spi_id); + + if (!spi || spi->level =3D=3D level) { + return; + } =20 trace_gicv5_spi(spi_id, level); + + spi->level =3D level; + spi_sample(spi); + trace_gicv5_spi_state(spi_id, spi->level, spi->pending, spi->active); } =20 static void gicv5_reset_hold(Object *obj, ResetType type) diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 409935e15a..4c55af2780 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -241,6 +241,7 @@ gicv5_set_pending(const char *domain, const char *type,= bool virtual, uint32_t i gicv5_set_handling(const char *domain, const char *type, bool virtual, uin= t32_t id, int handling) "GICv5 IRS SetHandling %s %s virtual:%d ID %u handl= ing %d" gicv5_set_target(const char *domain, const char *type, bool virtual, uint3= 2_t id, uint32_t iaffid, int irm) "GICv5 IRS SetTarget %s %s virtual:%d ID = %u IAFFID %u routingmode %d" gicv5_request_config(const char *domain, const char *type, bool virtual, u= int32_t id, uint64_t icsr) "GICv5 IRS RequestConfig %s %s virtual:%d ID %u = ICSR 0x%" PRIx64 +gicv5_spi_state(uint32_t spi_id, bool level, bool pending, bool active) "G= ICv5 IRS SPI ID %u now level %d pending %d active %d" =20 # arm_gicv5_common.c gicv5_common_realize(uint32_t irsid, uint32_t num_cpus, uint32_t spi_base,= uint32_t spi_irs_range, uint32_t spi_range) "GICv5 IRS realized: IRS ID %u= , %u CPUs, SPI base %u, SPI IRS range %u, SPI range %u" --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610508; cv=none; d=zohomail.com; s=zohoarc; b=KAMfSPhE8GyhpMyOT22B3FnEYS5bdWXtQPSTCJhW49A7j1JnpnDokiry5gxGz9MHVWB3BDc89hUle3+QalWwWiM+5ZlFh3SKKQnfuZ0rRqpnxlIaH3Y7OuX50npYP8tIy6ooIeUsnNLUepzM67NInlSbRTP/BrnpSLTPdk8gTzI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610508; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=6cD+byhD6HHL0QW4JTdgOkUxXSbgebUllweR4WzK/yw=; b=cgNat1yqpTBQwTdM7uAlnj61Or8n6UOMr4mXirpngdoJd1TkVlBmiSkl6ELTuUVZw/v0SWDHmr34gO0RZOLSuGpLCdbUEIYurWr0I5b8qnYkoTrZellcqbRYkdWdXeLCe1NSL9Gu8rsB/mjncEGE2bDn1PHBuNqRbiWlZnkQNIE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610508551137.81623673865295; Fri, 27 Mar 2026 04:21:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65C5-0006qM-Hi; Fri, 27 Mar 2026 07:17:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65C2-0006m9-86 for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:34 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65Bz-00081S-G9 for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:33 -0400 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-439b9cf8cb5so1919201f8f.0 for ; Fri, 27 Mar 2026 04:17:30 -0700 (PDT) Received: from lanath.. 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The IRS_CR1 register has cacheability, shareability and cache hint information to use for IRS memory accesses; since QEMU doesn't care about this we can make it simply reads-as-written. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5.c | 13 +++++++++++++ hw/intc/arm_gicv5_common.c | 2 ++ include/hw/intc/arm_gicv5_common.h | 2 ++ 3 files changed, 17 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index bc887233f5..3f397d9115 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -1080,6 +1080,13 @@ static bool config_readl(GICv5 *s, GICv5Domain domai= n, hwaddr offset, } *data =3D v; return true; + case A_IRS_CR0: + /* Enabling is instantaneous for us so IDLE is always 1 */ + *data =3D cs->irs_cr0[domain] | R_IRS_CR0_IDLE_MASK; + return true; + case A_IRS_CR1: + *data =3D cs->irs_cr1[domain]; + return true; } =20 return false; @@ -1159,6 +1166,12 @@ static bool config_writel(GICv5 *s, GICv5Domain doma= in, hwaddr offset, trace_gicv5_spi_state(id, spi->level, spi->pending, spi->active); return true; } + case A_IRS_CR0: + cs->irs_cr0[domain] =3D data & R_IRS_CR0_IRSEN_MASK; + return true; + case A_IRS_CR1: + cs->irs_cr1[domain] =3D data; + return true; } =20 return false; diff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c index 0813f0ac66..b1c8ec4521 100644 --- a/hw/intc/arm_gicv5_common.c +++ b/hw/intc/arm_gicv5_common.c @@ -66,6 +66,8 @@ static void gicv5_common_reset_hold(Object *obj, ResetTyp= e type) =20 memset(cs->irs_ist_baser, 0, sizeof(cs->irs_ist_baser)); memset(cs->irs_ist_cfgr, 0, sizeof(cs->irs_ist_cfgr)); + memset(cs->irs_cr0, 0, sizeof(cs->irs_cr0)); + memset(cs->irs_cr1, 0, sizeof(cs->irs_cr1)); =20 if (cs->spi) { GICv5Domain mp_domain; diff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5= _common.h index 61d017bf38..ac0532abe8 100644 --- a/include/hw/intc/arm_gicv5_common.h +++ b/include/hw/intc/arm_gicv5_common.h @@ -84,6 +84,8 @@ struct GICv5Common { uint64_t irs_ist_baser[NUM_GICV5_DOMAINS]; uint32_t irs_ist_cfgr[NUM_GICV5_DOMAINS]; uint32_t irs_spi_selr[NUM_GICV5_DOMAINS]; + uint32_t irs_cr0[NUM_GICV5_DOMAINS]; + uint32_t irs_cr1[NUM_GICV5_DOMAINS]; =20 /* * Pointer to an array of state information for the SPIs. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610251; x=1775215051; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xoRGta1aZeQteYUJwBZiFNsYjMFLQaWe8l3517JXolw=; b=gZws7ldrZOgt/fiKrjUZTsOBGyzFv+j0h4B/rleILE/svzuv8Yj2+xXE4uUMkw0fC1 HvdX45hHQsGqT9TNMqDQxx0vm/H6mc8tF7m4iXOTmwoGDpDM4DjTpywguFc0LSl8/gwc WqxFdVkwsfQzJc4U31wJOuhu0Qa2OzZecQDEgRP+zWAs/yYYnZmkIfEL2IPWu/6XPAy8 lj02SmRisptogSZf14xdiVa6O5fzvzoRE8irX6nVxlOiqYztJP4XynY2VTpdRXfog0I+ dqE1u/31hA3Lo4L9jFyWW5QvZ4fMGN7yarhXaepKKPfvpCxhkmytwbcPanOmwUZL/fVD OAfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610251; x=1775215051; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=xoRGta1aZeQteYUJwBZiFNsYjMFLQaWe8l3517JXolw=; b=dvAwHQYj7PI8ykfDH+FkDQR/K4JHB39qf+IXwdqTojMrw3jIz85eTYSxKSv76mIXE4 Tdp/EF474G2+HXex7ojyPmf2Ubltjq8qAuZZ6iWaBs3zYF4KkxzLuGt067W7qfke5Zu4 9+XmTPoTZmoJm1TyGHXJvucC2tpa7jX6lSR6Gn/3ji+NfyWNvKEmoBQ7nEvzgyYL3mlb mf2z1tc1jspHsP6ZxHdcAvdKxFqA2AgNoDhyE6VLzhEo/AH1HMxfrr4NmYIJvEZf7+AP 33TVI0M3DAYkmK6lvSRaPS2ADYE4OwYuRTY8TkqwK92Nc5EPjWryyWYJnJzAEQQ7akAN cS4A== X-Forwarded-Encrypted: i=1; AJvYcCXVoZqRZkFXXKm0MeEgCEQvc2FSobxX6Dbye4CKaBa3/Am/23oFSrwTHIbTLc7Iqx1J/37gBm0Wpn6+@nongnu.org X-Gm-Message-State: AOJu0Yw1jebvqD8BzKv01d21fV8rQlGEQg9E1TomWGBlr5EB8nKBh/VS IG48OOgTQt3i0smN+b15IuYWqWBwH71te0YjJXvUu2B+8ZekqmDWVpcMUkErhLiOSuI= X-Gm-Gg: ATEYQzyzXNNILLP62jtf7560R7jiUQooRllLfmqCMehHmOGOU00TXDU91IrH6392tLS OGJ4SRtigma4sZF+xcLHno8i5wt7doviNn4ZP3jbLvY3ITKtyj/nEHq6ne17sbQte0k2qSGxyzE zfaGXLijGWRWXxGRWw8UXYuOp9bjH6ChlJ2pS+Er8zttjzHdzMtS019wKMqTMNc/OHpKBS4OcP8 ahvQkAkGLZ+XR4dbEthKx0E12mOkg49uG2kTSVer/iW9vBaS6dWr+ZUp4z9EHNGAUvxApiFbaMV TBi0PZ0/kxu8zQfDDwhw+h84x6ttxwG3NCog5s9Q2V+hzlCTZS02y0rIwL1OIaEyqnUn0wnLFyz LnTqMaYtS32OumhoxsqtBojEeIwVX8CITmBDq+VS0pA4D3jv/6exmR9c9Yq7/f60qe9rbXih7Tu G2gV3+mfqHFj0lfnpJyZPIbE/wEmxv54XMQkx6yl5KF3MpBhDLbJC7w/k4hOeoVQqaRQfrL/mnB 47VsvoRXU8efqh092c7nXpKj3D1J9s= X-Received: by 2002:a05:600c:1e8c:b0:485:304a:58cd with SMTP id 5b1f17b1804b1-48727d5a25dmr34381805e9.4.1774610250547; Fri, 27 Mar 2026 04:17:30 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 30/65] hw/intc/arm_gicv5: Implement IRS_SYNCR and IRS_SYNC_STATUSR Date: Fri, 27 Mar 2026 11:16:25 +0000 Message-ID: <20260327111700.795099-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610276213154100 Content-Type: text/plain; charset="utf-8" The IRS_SYNCR register is used by software to request synchronization of interrupt events. This means that in-flight interrupt events are guaranteed to have been delivered. Since QEMU's implementation is entirely synchronous, syncs are a no-op for us. This means we can ignore writes to IRS_SYNCR and always report "sync complete" via the IDLE bit in IRS_SYNC_STATUSR. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 3f397d9115..7b0d9e16c4 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -1087,6 +1087,10 @@ static bool config_readl(GICv5 *s, GICv5Domain domai= n, hwaddr offset, case A_IRS_CR1: *data =3D cs->irs_cr1[domain]; return true; + case A_IRS_SYNC_STATUSR: + /* Sync is a no-op for QEMU: we are always IDLE */ + *data =3D R_IRS_SYNC_STATUSR_IDLE_MASK; + return true; } =20 return false; @@ -1172,6 +1176,9 @@ static bool config_writel(GICv5 *s, GICv5Domain domai= n, hwaddr offset, case A_IRS_CR1: cs->irs_cr1[domain] =3D data; return true; + case A_IRS_SYNCR: + /* Sync is a no-op for QEMU: ignore write */ + return true; } =20 return false; --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610565487608.982989603222; Fri, 27 Mar 2026 04:22:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65CE-00072g-Er; Fri, 27 Mar 2026 07:17:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65C3-0006nl-DT for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:35 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65C1-000822-4T for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:35 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-486fb14227cso24721415e9.3 for ; Fri, 27 Mar 2026 04:17:32 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610252; x=1775215052; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aRt8V9U0CkppqZyopaw8OtekbF4DU6MQ2QG3S20WAVo=; b=HD2Rk4VLF+MKesBYtu3KOBYiU2uPGp05PKU3FmtxfBfVk8cPrgyNfzGJe1vtChdZwM mmKK3VWp0PtBC5skkDcA9XTCE0Fr8D6YOvxl2A0U9YgYffWHWYPZPF3J2UvrvdnyHQP2 9M9SNMQ17AtcOyPREAJsWR3TD3fao7hCiCMGSUtty9QAk3r4j7FDfBuUUeaC+sMm5nuX 1qZAM3cebaP6grLdxC7ZxLwUXos0065z0g34B3ykm20uijic2N0VKzdlIP/jw5x0jMrW Sj5uCv82Sugxk0Rn7NBbIXIVf1ucmp3jFgyyCZ1H4rfSeCv5Tm0zueiNia/i+H9ewT3d WghA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610252; x=1775215052; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=aRt8V9U0CkppqZyopaw8OtekbF4DU6MQ2QG3S20WAVo=; b=PIDxYcUY9E421DM/yj33Run/k/14qidRqkJvkAyeg+Mz5uH/V+xMsUTM1a8FvVIk5f LsdqqxXLzhgvmBK34WsWrDtr5/wArdvKl60QJAluJ/1MacCJgzXVCReHXCttiv1lANKp hMfceNan1bLAU1mZHsWChCdfPyIt81p7v8F1qt42qF2rrazoptQZjEaw/OnQFE9xKHsm sfRH9Zbj/w0sWV9OFTitk6dnU8gINH1qh4+tgPJw8tswhQjyqvPxGVKOGfxIE8A7dS0V AikkP6KXojTargbKEb0/p6vLFbvRswk4X/lbr3dnBEIlgDzZbHcTfSZdWK0TtgDTl+Xt JKUg== X-Forwarded-Encrypted: i=1; AJvYcCVcoOjRh7Rv0M2HJ5kUV/o+OwHm7F7Kj8DvwUFVothuCRG2Qm+UeE3lJTpp0tXz3jTv/cAJLLlDHIfb@nongnu.org X-Gm-Message-State: AOJu0YyFWe1TcwrXgJoexNW7skkEP5NHs39XDOwVAHYDAXpTHPzEsgf+ ZJ3I5+2hC76OjCCh0dVh3Rg1irsWmlii+KjUtN9imIlxobDrVBAeTbgjQfhGzhQgsBE= X-Gm-Gg: ATEYQzyRIrgQhON1TBANOzygRuF3+IekEozT5p5vpIhAqOh2qK/nWxuykQ3xqHxl6Iw h9qPrLE1RoMKFbnPQIFfZhMFviT6SfaHo/ogbIXxT4R24zRTDE07j1fEbGCdmFgn8u6lcqxEjIV j0VUmpXsHYlgXQsu0cbVPrQroKMcIWkMqubclyeTn8emKzNbvBhOWkUxuG3TiSe9J8fh7eMBVV9 sXwx5wlnLEKY5Q8epIlinIE4/JqYFDV71Gt9swPjpFRMUgUTQ6w9t50CQN42U0MMQ1YwMv/rTZL 4v8czQH6RuOa028Wcw75fwJ7pN75USuLVSBkhBHOrD4Igqd4tI8POF//LFFZg04ky/hkUKzH5Fl sBQ6PG2FME65VOR5HFXvfZT70GtY+OmwkTvdUDZOec6gKntGfwvDpxy9THkInj5TAdhoR5BoLjL Yz+Zyw++C8m3YtYcPZmbgOWZX6SOYpmY8DTkxWVD3FuEKeWTRViOrhQaws2Dz4d1r7s+eBcm4M1 bLj4hOViGE2UPmXrS4SuIMsS2fkL6o= X-Received: by 2002:a05:600c:1546:b0:487:4eb:d125 with SMTP id 5b1f17b1804b1-48727ef0351mr33466895e9.9.1774610251476; Fri, 27 Mar 2026 04:17:31 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 31/65] hw/intc/arm_gicv5: Implement IRS_PE_{CR0, SELR, STATUSR} Date: Fri, 27 Mar 2026 11:16:26 +0000 Message-ID: <20260327111700.795099-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1774610567318158500 Content-Type: text/plain; charset="utf-8" The IRS_PE_CR0, IRS_PE_SELR, IRS_PE_STATUSR registers allow software to set and query per-CPU config. Software writes the AFFID of a CPU to IRS_PE_SELR, and can then read and write the 1ofN config for that CPU to IRS_PE_CR0, and read the CPU's online status from IRS_PE_STATUSR. For QEMU, we do not implement 1-of-N interrupt routing, so IRS_PE_CR0 can be RAZ/WI. Our CPUs are always online and selecting a new one via SELR is instantaneous, so IRS_PE_STATUSR will return either ONLINE | V | IDLE if a valid AFFID was written to SELR, or just IDLE if an invalid AFFID was written. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5.c | 39 ++++++++++++++++++++++++++++++ hw/intc/arm_gicv5_common.c | 1 + include/hw/intc/arm_gicv5_common.h | 1 + 3 files changed, 41 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 7b0d9e16c4..a95a9dc16b 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -968,6 +968,21 @@ static void spi_sample(GICv5SPIState *spi) } } =20 +static bool irs_pe_selr_valid(GICv5Common *cs, GICv5Domain domain) +{ + /* + * Return true if IRS_PE_SELR has a valid AFFID in it. We don't + * expect the guest to do this except perhaps once at startup, so + * do a simple linear scan through the cpu_iaffids array. + */ + for (int i =3D 0; i < cs->num_cpu_iaffids; i++) { + if (cs->irs_pe_selr[domain] =3D=3D cs->cpu_iaffids[i]) { + return true; + } + } + return false; +} + static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset, uint64_t *data, MemTxAttrs attrs) { @@ -1091,6 +1106,24 @@ static bool config_readl(GICv5 *s, GICv5Domain domai= n, hwaddr offset, /* Sync is a no-op for QEMU: we are always IDLE */ *data =3D R_IRS_SYNC_STATUSR_IDLE_MASK; return true; + case A_IRS_PE_SELR: + *data =3D cs->irs_pe_selr[domain]; + return true; + case A_IRS_PE_CR0: + /* We don't implement 1ofN, so this is RAZ/WI for us */ + *data =3D 0; + return true; + case A_IRS_PE_STATUSR: + /* + * Our CPUs are always online, so we're really just reporting + * whether the guest wrote a valid AFFID to IRS_PE_SELR + */ + v =3D R_IRS_PE_STATUSR_IDLE_MASK; + if (irs_pe_selr_valid(cs, domain)) { + v |=3D R_IRS_PE_STATUSR_V_MASK | R_IRS_PE_STATUSR_ONLINE_MASK; + } + *data =3D v; + return true; } =20 return false; @@ -1179,6 +1212,12 @@ static bool config_writel(GICv5 *s, GICv5Domain doma= in, hwaddr offset, case A_IRS_SYNCR: /* Sync is a no-op for QEMU: ignore write */ return true; + case A_IRS_PE_SELR: + cs->irs_pe_selr[domain] =3D data; + return true; + case A_IRS_PE_CR0: + /* We don't implement 1ofN, so this is RAZ/WI for us */ + return true; } =20 return false; diff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c index b1c8ec4521..5510e6239a 100644 --- a/hw/intc/arm_gicv5_common.c +++ b/hw/intc/arm_gicv5_common.c @@ -68,6 +68,7 @@ static void gicv5_common_reset_hold(Object *obj, ResetTyp= e type) memset(cs->irs_ist_cfgr, 0, sizeof(cs->irs_ist_cfgr)); memset(cs->irs_cr0, 0, sizeof(cs->irs_cr0)); memset(cs->irs_cr1, 0, sizeof(cs->irs_cr1)); + memset(cs->irs_pe_selr, 0, sizeof(cs->irs_pe_selr)); =20 if (cs->spi) { GICv5Domain mp_domain; diff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5= _common.h index ac0532abe8..34ad38c198 100644 --- a/include/hw/intc/arm_gicv5_common.h +++ b/include/hw/intc/arm_gicv5_common.h @@ -86,6 +86,7 @@ struct GICv5Common { uint32_t irs_spi_selr[NUM_GICV5_DOMAINS]; uint32_t irs_cr0[NUM_GICV5_DOMAINS]; uint32_t irs_cr1[NUM_GICV5_DOMAINS]; + uint32_t irs_pe_selr[NUM_GICV5_DOMAINS]; =20 /* * Pointer to an array of state information for the SPIs. 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Although we only have one callsite at the moment, the ITS config frame uses the same ID register values, so we abstract this out into a function we can reuse later. Signed-off-by: Peter Maydell --- hw/intc/arm_gicv5.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index a95a9dc16b..866c1333c3 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -285,6 +285,9 @@ REG64(IRS_SWERR_SYNDROMER0, 0x3c8) REG64(IRS_SWERR_SYNDROMER1, 0x3d0) FIELD(IRS_SWERR_SYNDROMER2, ADDR, 3, 53) =20 +REG32(IRS_IDREGS, 0xffd0) +REG32(IRS_DEVARCH, 0xffbc) + FIELD(L1_ISTE, VALID, 0, 1) FIELD(L1_ISTE, L2_ADDR, 12, 44) =20 @@ -310,6 +313,31 @@ FIELD(ICSR, HM, 5, 1) FIELD(ICSR, PRIORITY, 11, 5) FIELD(ICSR, IAFFID, 32, 16) =20 +#define IRS_DEVARCH_VALUE ((0x23b << 31) | (0x1 << 20) | 0x5a19) + +static uint32_t gicv5_idreg(int regoffset) +{ + /* + * As with the main IRS_IIDR, we don't identify as a specific + * hardware GICv5 implementation. Arm suggests that the + * Implementer, Product, etc in IRS_IIDR should also be reported + * here, so we do that. + */ + static const uint8_t gic_ids[] =3D { + QEMU_GICV5_IMPLEMENTER >> 8, 0x00, 0x00, 0x00, /* PIDR4..PIDR7 */ + QEMU_GICV5_PRODUCTID & 0xff, /* PIDR0 */ + ((QEMU_GICV5_PRODUCTID >> 8) | + ((QEMU_GICV5_IMPLEMENTER & 0xf) << 4)), /* PIDR1 */ + ((QEMU_GICV5_REVISION << 4) | (1 << 3) | + ((QEMU_GICV5_IMPLEMENTER & 0x70) >> 4)), /* PIDR2 */ + QEMU_GICV5_VARIANT << 4, /* PIDR3 */ + 0x0D, 0xF0, 0x05, 0xB1, /* CIDR0..CIDR3 */ + }; + + regoffset /=3D 4; + return gic_ids[regoffset]; +} + static GICv5SPIState *spi_for_selr(GICv5Common *cs, GICv5Domain domain) { /* @@ -1124,6 +1152,13 @@ static bool config_readl(GICv5 *s, GICv5Domain domai= n, hwaddr offset, } *data =3D v; return true; + case A_IRS_DEVARCH: + *data =3D IRS_DEVARCH_VALUE; + return true; + case A_IRS_IDREGS ... A_IRS_IDREGS + 0x2f: + /* CoreSight ID registers */ + *data =3D gicv5_idreg(offset - A_IRS_IDREGS); + return true; } =20 return false; --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610322; cv=none; d=zohomail.com; s=zohoarc; b=EWkaGu+e0oB06dcm2z2HWeuyuzReIplW9fHd0JRrLWukpvOez0/QIUn0IIV0IeN3DRUqV8H1U6qMcegCMHwMqkXFhQJuN/AZNzqplIfO4uy4JsY1qzEgkn9iFurjaWlLg1c3alr16a0Y8UBSDpACokdNqs+jmKrWkIK9hW2ijNc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610322; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=vEEJDQIfKatLAIWwp1VQVpGT8YNJGDnSyCNt4dE6jFI=; b=evVOZJH9h+0TFPIa4IhBbD7YB9Z1vPEei+a4wtWmW0VOoKcS2RwWf8ZUc8k37UA3b8eBw0MK9ROZq3gR0u1bj+aV3RZ2m7nS2ndwddL53g3O6JD0xc2cWPAG3bQDUN7tXfdhot1wzIg0XfhQn2QgKiqhCniPOAWa7mPsuzlTKN4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610322800596.1876258342573; Fri, 27 Mar 2026 04:18:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65CA-0006y3-6v; Fri, 27 Mar 2026 07:17:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65C5-0006qK-Dt for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:37 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65C3-000860-Ar for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:37 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-43b4f48c47cso1440834f8f.0 for ; Fri, 27 Mar 2026 04:17:34 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610254; x=1775215054; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vEEJDQIfKatLAIWwp1VQVpGT8YNJGDnSyCNt4dE6jFI=; b=jkEcsttFw5z4iFEEkEwQR+a7kDtPyAUTz1jLDfy8J2gac34zxpeZwQEg4hd7zUAEpt i03kRsdFzV3b9+ZPmEftTWZry6uk43dhs/+QGEVMKL1i9F/eJH+or7hahbeBUTy0UKp4 rh0WYu34lby4DJgWpwUD8AqQoV3Fj+AmTcPWrLpHZt2YKN9tiXwyyHRqlqndR3vnl7Ny ItF1wAhu6CIzScO2lbkmnZcZ4Xn4vuKJkGOuWEPgk6x2S2s9PA1kR+tilZW5T9hmsXj3 37hoZriDxGjet+P9Mjh7w1rrmOdKtKN5XkVRKf5BQyl7MlM4WkF1X1KAewl+YufHjpeP Ul7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610254; x=1775215054; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=vEEJDQIfKatLAIWwp1VQVpGT8YNJGDnSyCNt4dE6jFI=; b=fWFm1VSwgmPP0BYoWlpW+oaFQ94RTjvRICq1o97CFpM2zQLpowVoY3AUPrtLpXp3BM xj3QFgAPTEwGxUa1alrxKjDvcKyL2f4TSk6E7ckMXMcj9G89/HfyanL6Gx/IiHFLienl tdnzSA3WeKO+FU2g5mQbPVwuRvqy+vlvWExVlA727iOu697TBBlX7Uat3AIu3Bz0pfke uxTTl/oJV+u+znyxqcoDDexbBmHt8so8LqUpg0RacetDQ4z7gItuJtfxzJhNvNEuKa6A aDtuNsyVFFmwlgTDRn6/22xOIuHJP8bDi8VvPY89oLaqjvxFNrmTjDGuB/6sAwXCb0Ew YxDA== X-Forwarded-Encrypted: i=1; AJvYcCUDiPvEiyi9IF38EJWsKCmoKxN60so1g/tUyVankyvaRlek27dpj9FVtLazuMGn9rNwQTMH5TE2Id+7@nongnu.org X-Gm-Message-State: AOJu0Yx2Zj666WL9KZi/NYjBwG6cs1Mx/qp8WvKCp79iuMMPj/YHY7cp GZdcuM7MiIp3f2MVZhPFrL2stOah9dgT2NsEs7KG8N6HJPOg1eRH1aR584KZZsZAdvYvXUmEvyQ trmCDkvM= X-Gm-Gg: ATEYQzyHj2sy2qYdeZNh7A3zLcfpQpk+0HtrAxUT2/CvOyEKrcc95won0EsW49rMbuE wogEo8Mc0kfzoHf/2rVK7EvoybWSNODCxIklKSL1mYGm7unIrHJGOr4dbZJvet11puL31XqpX3s MbsSWSB6W4Li0ZW1k2dH0Hvp2pDbWbo7xyWlpulNHdv1ueZ9l4io3WFgoanc+sz7CR/10Lrj+D9 VimiwEHAUgZmOG1v2h+8E3TJUQ4wFoTpxjLH4Ddwf61HcfoHfUse0u3ewEbH5f2SD4PKcytbJ+l cTtmeXFA4Sq+UeXU0hb4nOwOeotbHljae1SoL6URKjrTvHwaBu9PhY+cArXelOa1AJZtGllY3EB 4hmNDmOmni+s92ld/g0j1jLHS1RvYrAqeDLX0SbZhI9A6Lfg8dJh9B/FiRVLgKFLlJ2eJYig6jC hOq4AV0iVvkoIGAtJdz9hsqon0z3MQ9C0rqYI0jPSVUoHV5FhrJDV1yczMdIB8QbIrtLklHbNPr ZBoVwWCBwdvAa2sIFpmNmrR7183u/U= X-Received: by 2002:a5d:584b:0:b0:43b:5097:6f60 with SMTP id ffacd0b85a97d-43b9ea46b9fmr3077811f8f.32.1774610253735; Fri, 27 Mar 2026 04:17:33 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 33/65] hw/intc/arm_gicv5: Cache pending LPIs in a hash table Date: Fri, 27 Mar 2026 11:16:28 +0000 Message-ID: <20260327111700.795099-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610325124154100 Content-Type: text/plain; charset="utf-8" The GICv5 stores information about LPIs in a guest-memory data structure. Iterating through this to identify the highest priority pending interrupt would be expensive; to avoid this we will use a hash table which contains an entry for each pending LPI and which caches the L2 ISTE. Typically only a few LPIs will be pending at any one time, so iterating through the hash table should be fast. We can access an L2 ISTE whenever it is valid, and can freely cache the data for as long as the IST is valid. We only need to ensure that we have written back the data at the point where IRS_IST_BASER.VALID is written to 0. We add an LPI to the cache when the pending bit is written to 1, and remove it when it is written to 0. Handling of checking the cache, and of adding and removing entries, is handled within get_l2_iste() and put_l2_iste(), which all the operations that read and write ISTE words use. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5.c | 116 ++++++++++++++++++++++++++++++++++-- include/hw/intc/arm_gicv5.h | 2 + 2 files changed, 112 insertions(+), 6 deletions(-) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 866c1333c3..989492d4b6 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -471,15 +471,22 @@ static bool write_l2_iste_mem(GICv5Common *cs, const = GICv5ISTConfig *cfg, =20 /* * This is returned by get_l2_iste() and has everything we need to do - * the writeback of the L2 ISTE word in put_l2_iste(). Currently the - * get/put functions always directly do guest memory reads and writes - * to update the L2 ISTE. In a future commit we will add support for a - * cache of some of the ISTE data in a local hashtable; the APIs are - * designed with that in mind. + * the writeback of the L2 ISTE word in put_l2_iste(). Not all these + * fields are always valid; they are private to the implementation of + * get_l2_iste() and put_l2_iste(). */ typedef struct L2_ISTE_Handle { + /* Guest memory address of the L2 ISTE; valid only if !hashed */ hwaddr l2_iste_addr; - uint32_t l2_iste; + union { + /* Actual L2_ISTE word; valid only if !hashed */ + uint32_t l2_iste; + /* Pointer to L2 ISTE word; valid only if hashed */ + uint32_t *l2_iste_p; + }; + uint32_t id; + /* True if this ISTE is currently in the cache */ + bool hashed; } L2_ISTE_Handle; =20 static uint32_t *get_l2_iste(GICv5Common *cs, const GICv5ISTConfig *cfg, @@ -499,6 +506,25 @@ static uint32_t *get_l2_iste(GICv5Common *cs, const GI= Cv5ISTConfig *cfg, * If the ISTE could not be read (typically because of a memory * error), return NULL. */ + uint32_t *hashvalue; + + if (!cfg->valid) { + /* Catch invalid config early, it has no lpi_cache */ + return NULL; + } + + hashvalue =3D g_hash_table_lookup(cfg->lpi_cache, + GINT_TO_POINTER(id)); + + h->id =3D id; + + if (hashvalue) { + h->hashed =3D true; + h->l2_iste_p =3D hashvalue; + return hashvalue; + } + + h->hashed =3D false; if (!get_l2_iste_addr(cs, cfg, id, &h->l2_iste_addr) || !read_l2_iste_mem(cs, cfg, h->l2_iste_addr, &h->l2_iste)) { return NULL; @@ -514,6 +540,34 @@ static void put_l2_iste(GICv5Common *cs, const GICv5IS= TConfig *cfg, * Once this has been called the L2_ISTE_Handle @h and the pointer * to the L2 ISTE word are no longer valid. */ + if (h->hashed) { + uint32_t l2_iste =3D *h->l2_iste_p; + if (!FIELD_EX32(l2_iste, L2_ISTE, PENDING)) { + /* + * We just made this not pending: remove from hash table + * and write back to memory. + */ + hwaddr l2_iste_addr; + + g_hash_table_remove(cfg->lpi_cache, GINT_TO_POINTER(h->id)); + if (get_l2_iste_addr(cs, cfg, h->id, &l2_iste_addr)) { + write_l2_iste_mem(cs, cfg, l2_iste_addr, l2_iste); + /* Writeback errors are ignored. */ + } + } + return; + } + + if (FIELD_EX32(h->l2_iste, L2_ISTE, PENDING)) { + /* + * We just made this pending: add it to the hash table, and + * don't bother writing it back to memory. + */ + uint32_t *hashvalue =3D g_new(uint32_t, 1); + *hashvalue =3D h->l2_iste; + g_hash_table_insert(cfg->lpi_cache, GINT_TO_POINTER(h->id), hashva= lue); + return; + } write_l2_iste_mem(cs, cfg, h->l2_iste_addr, h->l2_iste); } =20 @@ -896,6 +950,39 @@ txfail: "physical address 0x" HWADDR_FMT_plx "\n", intid, l1_add= r); } =20 +/* Data we need to pass through to irs_clean_lpi_cache_entry() */ +typedef struct CleanLPICacheUserData { + GICv5Common *cs; + GICv5ISTConfig *cfg; +} CleanLPICacheUserData; + +static gboolean irs_clean_lpi_cache_entry(gpointer key, gpointer value, + gpointer user_data) +{ + /* Drop this entry from the LPI cache, writing it back to guest memory= . */ + CleanLPICacheUserData *ud =3D user_data; + hwaddr l2_iste_addr; + uint64_t id =3D GPOINTER_TO_INT(key); + uint32_t l2_iste =3D *(uint32_t *)value; + + if (!get_l2_iste_addr(ud->cs, ud->cfg, id, &l2_iste_addr) || + !write_l2_iste_mem(ud->cs, ud->cfg, l2_iste_addr, l2_iste)) { + /* We drop the cached entry regardless of writeback errors */ + return true; + } + return true; +} + +static void irs_clean_lpi_cache(GICv5Common *cs, GICv5ISTConfig *cfg) +{ + /* Write everything in the LPI cache out to guest memory */ + CleanLPICacheUserData ud; + ud.cs =3D cs; + ud.cfg =3D cfg; + + g_hash_table_foreach_remove(cfg->lpi_cache, irs_clean_lpi_cache_entry,= &ud); +} + static void irs_ist_baser_write(GICv5 *s, GICv5Domain domain, uint64_t val= ue) { GICv5Common *cs =3D ARM_GICV5_COMMON(s); @@ -907,6 +994,7 @@ static void irs_ist_baser_write(GICv5 *s, GICv5Domain d= omain, uint64_t value) /* Ignore 1->1 transition */ return; } + irs_clean_lpi_cache(cs, &s->phys_lpi_config[domain]); cs->irs_ist_baser[domain] =3D FIELD_DP64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID, valid= ); s->phys_lpi_config[domain].valid =3D false; @@ -968,6 +1056,15 @@ static void irs_ist_baser_write(GICv5 *s, GICv5Domain= domain, uint64_t value) cfg->l2_idx_bits =3D l2_idx_bits; cfg->structure =3D FIELD_EX64(cs->irs_ist_cfgr[domain], IRS_IST_CFGR, STRUCTURE); + if (!cfg->lpi_cache) { + /* + * Keys are GINT_TO_POINTER(intid), so we want the g_direct_ha= sh + * and g_direct_equal hash and equality functions. We don't + * want to free the keys, but we do want to free the values + * (which are pointer-to-uint32_t). + */ + cfg->lpi_cache =3D g_hash_table_new_full(NULL, NULL, NULL, g_f= ree); + } cfg->valid =3D true; trace_gicv5_ist_valid(domain_name[domain], cfg->base, cfg->id_bits, cfg->l2_idx_bits, cfg->istsz, cfg->structure= ); @@ -1428,6 +1525,13 @@ static void gicv5_reset_hold(Object *obj, ResetType = type) /* IRS_IST_BASER and IRS_IST_CFGR reset to 0, clear cached info */ for (int i =3D 0; i < NUM_GICV5_DOMAINS; i++) { s->phys_lpi_config[i].valid =3D false; + /* + * If we got reset (power-cycled) with data in the cache, don't + * write it out to guest memory; just return to "empty cache". + */ + if (s->phys_lpi_config[i].lpi_cache) { + g_hash_table_remove_all(s->phys_lpi_config[i].lpi_cache); + } } } =20 diff --git a/include/hw/intc/arm_gicv5.h b/include/hw/intc/arm_gicv5.h index c631ecc3e8..fb13de0d01 100644 --- a/include/hw/intc/arm_gicv5.h +++ b/include/hw/intc/arm_gicv5.h @@ -25,6 +25,8 @@ typedef struct GICv5ISTConfig { uint8_t istsz; /* L2 ISTE size in bytes */ bool structure; /* true if using 2-level table */ bool valid; /* true if this table is valid and usable */ + /* This caches IST information about pending LPIs */ + GHashTable *lpi_cache; } GICv5ISTConfig; =20 /* --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610289; cv=none; d=zohomail.com; s=zohoarc; b=ly3C+0JTEH+cuNLO/dMUgQteHU4qbBwdztui2SetrLHpcyrDlRkgRPtmYK4pQvEV822KmyKIuPa0KMpzrZWTXoWOT4lV2/S4tpmc3W+p8AhqxjJNgKLIjAhaFXJb7lguyqRPYGZxhI+DciKevuipuLeaXQZ/QS1EeflwcPRcrs4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610289; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=xnrF8FhdNtpjJjbzEATZqeP00jwVSkGfClNmWr825JA=; b=RkgokzJtv2O+3xbErV99YrtkdE8HTDBJn9ngecQUFByT7vSoV7dEi7h9Q8LaGhtf/NB5QF1S1AJ/o79GA8Inq+BI35MddpL78lyCpz/lZFuuNNc21O9NgGeuXZEUUuHnxD0fmncAwoaHHjADrZDPo82j47aU41yXwh5S75LZd2g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610289016180.1211128217019; Fri, 27 Mar 2026 04:18:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65C9-0006wO-FJ; Fri, 27 Mar 2026 07:17:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65C6-0006sm-U0 for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:38 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65C4-000880-EC for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:38 -0400 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-439b9cf8cb5so1919286f8f.0 for ; Fri, 27 Mar 2026 04:17:35 -0700 (PDT) Received: from lanath.. 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Implement this register. In real hardware using the stream protocol, the IRS tells the CPU its IAFFID using a DownstreamControl command as part of the handshake process when the IRS-CPU link is brought online. Our analogue of this is to pass the IAFFID as an extra argument to gicv5_set_gicv5state(). (We could have the CPU call into the GIC every time to ask for the value, but this would mean we had to search the cpus[] array for the right CPU to return its IAFFID.) Note that we don't put the IAFFID into the gicv5_cpuif sub-struct, because that part of the CPU struct is zeroed on reset, and we must keep the IAFFID across reset (we only set it up when the GIC device is created). Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5_common.c | 5 +++-- include/hw/intc/arm_gicv5_stream.h | 3 ++- target/arm/cpu.c | 5 +++-- target/arm/cpu.h | 2 ++ target/arm/tcg/gicv5-cpuif.c | 11 +++++++++++ 5 files changed, 21 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c index 5510e6239a..0b5303f370 100644 --- a/hw/intc/arm_gicv5_common.c +++ b/hw/intc/arm_gicv5_common.c @@ -175,9 +175,10 @@ static void gicv5_common_realize(DeviceState *dev, Err= or **errp) } =20 for (int i =3D 0; i < cs->num_cpus; i++) { - if (!gicv5_set_gicv5state(cs->cpus[i], cs)) { + if (!gicv5_set_gicv5state(cs->cpus[i], cs, cs->cpu_iaffids[i])) { error_setg(errp, - "CPU %d does not implement GICv5 CPU interface", i); + "CPU %d (IAFFID 0x%x) does not implement GICv5 CPU = interface", + i, cs->cpu_iaffids[i]); return; } } diff --git a/include/hw/intc/arm_gicv5_stream.h b/include/hw/intc/arm_gicv5= _stream.h index 670423fdad..136b6339ee 100644 --- a/include/hw/intc/arm_gicv5_stream.h +++ b/include/hw/intc/arm_gicv5_stream.h @@ -20,6 +20,7 @@ typedef struct GICv5Common GICv5Common; * gicv5_set_gicv5state * @cpu: CPU object to tell about its IRS * @cs: the GIC IRS it is connected to + * @iaffid: the IAFFID of this CPU * * Set the CPU object's GICv5 pointer to point to this GIC IRS. The * IRS must call this when it is realized, for each CPU it is @@ -28,7 +29,7 @@ typedef struct GICv5Common GICv5Common; * Returns true on success, false if the CPU doesn't implement the * GICv5 CPU interface. */ -bool gicv5_set_gicv5state(ARMCPU *cpu, GICv5Common *cs); +bool gicv5_set_gicv5state(ARMCPU *cpu, GICv5Common *cs, uint32_t iaffid); =20 /* * The architected Stream Protocol is asynchronous; commands can be diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4044bce5b6..ceb303a55a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1087,16 +1087,17 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *= f, int flags) } =20 #ifndef CONFIG_USER_ONLY -bool gicv5_set_gicv5state(ARMCPU *cpu, GICv5Common *cs) +bool gicv5_set_gicv5state(ARMCPU *cpu, GICv5Common *cs, uint32_t iaffid) { /* * Set this CPU's gicv5state pointer to point to the GIC that we are - * connected to. + * connected to, and record our IAFFID. */ if (!cpu_isar_feature(aa64_gcie, cpu)) { return false; } cpu->env.gicv5state =3D cs; + cpu->env.gicv5_iaffid =3D iaffid; return true; } #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1fdfd91ba4..a32c5f3ab1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -819,6 +819,8 @@ typedef struct CPUArchState { void *gicv3state; /* Similarly, for a GICv5Common */ void *gicv5state; + /* For GICv5, this CPU's IAFFID */ + uint64_t gicv5_iaffid; #else /* CONFIG_USER_ONLY */ /* For usermode syscall translation. */ bool eabi; diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 8cf09791c1..005e2fa8d2 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -226,6 +226,17 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.icc_icsr_el1), .resetvalue =3D 0, }, + { .name =3D "ICC_IAFFIDR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 10, .opc2 =3D 5, + .access =3D PL1_R, .type =3D ARM_CP_NO_RAW, + /* ICC_IAFFIDR_EL1 holds the IAFFID only, in its low bits */ + .fieldoffset =3D offsetof(CPUARMState, gicv5_iaffid), + /* + * The field is a constant value set in gicv5_set_gicv5state(), + * so don't allow it to be overwritten by reset. + */ + .resetfn =3D arm_cp_reset_ignore, + }, }; =20 void define_gicv5_cpuif_regs(ARMCPU *cpu) --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610367; cv=none; d=zohomail.com; s=zohoarc; b=mlaNSPOF0mKco4BmumxduCHBrcHg/dl0HiDFe38SE9I2SACrs/WHZk6hUzBhKZ/uk40xNySy2Maoo4EDBtS3Pq9u7pZVr9P7DpHF3UfOGJ0hJhYEQQ0u8WRP2vAYfo0i41WhE7vryWH3/jTaDjnRQf1WHHH7d8gTfrFrWwvLttc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610367; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ajCMEb2lQLuc5DJ03lNLJ9KK+fIl70fxwg3ayKyNDHE=; b=GbHudP0AtOLt4e8AP/rgzHZVf3tf208dOmaxJTDNU0bMbksooE8i0IWAmb1yY5x3NobjUy14QR5dUn1nmvNBlsDVYvd3Jqzbzc424YCfqHsFW9D81T58+alebvgjktWprOUsrwI6FGtK5iEqFKD/0ZJb4ezk3hsczUUk+fhZEP4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610367023443.303208004882; Fri, 27 Mar 2026 04:19:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65CA-0006xw-1D; Fri, 27 Mar 2026 07:17:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65C7-0006sy-0F for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:39 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65C5-00088z-7Y for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:38 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-439d8df7620so1409170f8f.0 for ; Fri, 27 Mar 2026 04:17:36 -0700 (PDT) Received: from lanath.. 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Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- target/arm/tcg/gicv5-cpuif.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 005e2fa8d2..497c09474b 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -38,6 +38,18 @@ FIELD(GIC_CDHM, HM, 32, 1) FIELD(GIC_CDRCFG, ID, 0, 24) FIELD(GIC_CDRCFG, TYPE, 29, 3) =20 +FIELD(ICC_IDR0_EL1, ID_BITS, 0, 4) +FIELD(ICC_IDR0_EL1, PRI_BITS, 4, 4) +FIELD(ICC_IDR0_EL1, GCIE_LEGACY, 8, 4) + +/* + * We implement 24 bits of interrupt ID, the mandated 5 bits of priority, + * and no legacy GICv3.3 vcpu interface (yet) + */ +#define QEMU_ICC_IDR0 \ + ((4 << R_ICC_IDR0_EL1_PRI_BITS_SHIFT) | \ + (1 << R_ICC_IDR0_EL1_ID_BITS_SHIFT)) + static GICv5Common *gicv5_get_gic(CPUARMState *env) { return env->gicv5state; @@ -220,6 +232,11 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, .writefn =3D gic_cdhm_write, }, + { .name =3D "ICC_IDR0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 10, .opc2 =3D 2, + .access =3D PL1_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, + .resetvalue =3D QEMU_ICC_IDR0, + }, { .name =3D "ICC_ICSR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 10, .opc2 =3D 4, .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610565; cv=none; d=zohomail.com; s=zohoarc; b=e1WYwIYmfZ1m3Iostu25xH14ppV6Bxkwoj6jES7PwjLNt9SuhOAbskpNmqBCU6YUHxltlqVjkqvUmiGCvG4O2d6M1jCsX3H1GqOVKvgNEquVFpDRNr6BPOONvuqqvSty8BUivo8XCDme9IUbfdz7i6s2T8pvwxKfCTLM3u/kaI4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610565; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=kxB5i187u8Un3u8aoHnxELkuuEe7fJmA9lYGeZQAHAk=; b=oDBZ2QRIcv8X1boWVCaat7AHiWQITE+axKgcuTKXOAarp52yEaWjLZCiJuUfW04tGzKUXCvWAstlrNCx5JzJfBnXHVbY9TTUQVOomtf3Jqye//c7dfgjUhOuT5vSsrb1tlxIdI9NyAnnI5jUOE2PODzLhMjsmaK3PJqfpVFFC8E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610565145854.2666395145332; Fri, 27 Mar 2026 04:22:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65CG-00074Q-Ie; Fri, 27 Mar 2026 07:17:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65C8-0006vh-UM for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:40 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65C6-0008Aw-AD for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:39 -0400 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-439cd6b09f8so1307546f8f.3 for ; Fri, 27 Mar 2026 04:17:37 -0700 (PDT) Received: from lanath.. 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Implement the access system registers for the PPI active state; this is a pair of registers, one of which has "write 1 to clear" behaviour and the other of which has "write 1 to set". In both cases, reads return the current state. We start here by implementing the accessors for the underlying state; we don't yet attempt to do anything (e.g. recalculating the highest priority pending PPI) when the state changes. That will come in subsequent commits. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- target/arm/cpu.h | 5 +++++ target/arm/tcg/gicv5-cpuif.c | 38 ++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a32c5f3ab1..dd4dc12feb 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -257,6 +257,9 @@ typedef enum ARMFPStatusFlavour { } ARMFPStatusFlavour; #define FPST_COUNT 10 =20 +/* Architecturally there are 128 PPIs in a GICv5 */ +#define GICV5_NUM_PPIS 128 + typedef struct CPUArchState { /* Regs for current mode. */ uint32_t regs[16]; @@ -600,6 +603,8 @@ typedef struct CPUArchState { struct { /* GICv5 CPU interface data */ uint64_t icc_icsr_el1; + /* Most PPI registers have 1 bit per PPI, so 64 PPIs to a register= */ + uint64_t ppi_active[GICV5_NUM_PPIS / 64]; } gicv5_cpuif; =20 struct { diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 497c09474b..6672cda37f 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -175,6 +175,20 @@ static void gic_cdhm_write(CPUARMState *env, const ARM= CPRegInfo *ri, gicv5_set_handling(gic, id, hm, domain, type, virtual); } =20 +static void gic_ppi_cactive_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t old =3D raw_read(env, ri); + raw_write(env, ri, old & ~value); +} + +static void gic_ppi_sactive_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t old =3D raw_read(env, ri); + raw_write(env, ri, old | value); +} + static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { /* * Barrier: wait until the effects of a cpuif system register @@ -254,6 +268,30 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { */ .resetfn =3D arm_cp_reset_ignore, }, + { .name =3D "ICC_PPI_CACTIVER0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 13, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO= _RAW, + .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_active[0]), + .writefn =3D gic_ppi_cactive_write, + }, + { .name =3D "ICC_PPI_CACTIVER1_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 13, .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO= _RAW, + .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_active[1]), + .writefn =3D gic_ppi_cactive_write, + }, + { .name =3D "ICC_PPI_SACTIVER0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 13, .opc2 =3D 2, + .access =3D PL1_RW, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_active[0]), + .writefn =3D gic_ppi_sactive_write, + }, + { .name =3D "ICC_PPI_SACTIVER1_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 13, .opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_active[1]), + .writefn =3D gic_ppi_sactive_write, + }, }; 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Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- target/arm/cpu.h | 1 + target/arm/tcg/gicv5-cpuif.c | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index dd4dc12feb..4574f7005d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -605,6 +605,7 @@ typedef struct CPUArchState { uint64_t icc_icsr_el1; /* Most PPI registers have 1 bit per PPI, so 64 PPIs to a register= */ uint64_t ppi_active[GICV5_NUM_PPIS / 64]; + uint64_t ppi_hm[GICV5_NUM_PPIS / 64]; } gicv5_cpuif; =20 struct { diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 6672cda37f..e65bd56b3d 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -50,6 +50,16 @@ FIELD(ICC_IDR0_EL1, GCIE_LEGACY, 8, 4) ((4 << R_ICC_IDR0_EL1_PRI_BITS_SHIFT) | \ (1 << R_ICC_IDR0_EL1_ID_BITS_SHIFT)) =20 +/* + * PPI handling modes are fixed and not software configurable. + * R_CFSKX defines them for the architected PPIs: they are all Level, + * except that PPI 24 (CTIIRQ) is IMPDEF and PPI 3 (SW_PPI) is Edge. + * For unimplemented PPIs the field is RES0. The PPI register bits + * are 1 for Level and 0 for Edge. + */ +#define PPI_HMR0_RESET (~(1ULL << GICV5_PPI_SW_PPI)) +#define PPI_HMR1_RESET (~0ULL) + static GICv5Common *gicv5_get_gic(CPUARMState *env) { return env->gicv5state; @@ -292,6 +302,18 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_active[1]), .writefn =3D gic_ppi_sactive_write, }, + { .name =3D "ICC_PPI_HMR0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 10, .opc2 =3D 0, + .access =3D PL1_R, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_hm[0]), + .resetvalue =3D PPI_HMR0_RESET, + }, + { .name =3D "ICC_PPI_HMR1_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 10, .opc2 =3D 1, + .access =3D PL1_R, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_hm[1]), + .resetvalue =3D PPI_HMR1_RESET, + }, }; =20 void define_gicv5_cpuif_regs(ARMCPU *cpu) --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610312; cv=none; d=zohomail.com; s=zohoarc; b=nvEjUNbUd2ypqt7cxYWhjCdVEKkp2cO2AkZXK9dI4zLKpBf6lYs+86HPgln0FIgBsDwp3j23rLpEPABDek71M4X6OqTyaIP9HRyU8JM+nd5G0JFh0L87PC0RUr13fqHY9WX8lrVhPBaG2nmg3u+Xu6wGPWQssYGdoHxnog2EWYc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610312; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=62e2nWfA5UikkCDTdbvEyXi6vb3nI0AfG+OjttEGIxs=; b=GCVsAX/mKFiRb2FYOqew7YQxw6l38BmqT7cSYHjdVzMkHi+0nTLnr1qy+hPIE3LxehHxPRkt2yeLPxC8TkVYZbzBWDiETIFPZG5TGAr5hh/mgPwzW+E8o/VswlmN7KVTZu9Ux3RIftNGICEr4pclvyFv887fVUgQy+RrRLW5AK0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610312914354.98866829816086; Fri, 27 Mar 2026 04:18:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65CC-00070q-8S; Fri, 27 Mar 2026 07:17:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65CA-0006yu-Ed for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:42 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65C8-0008DE-Ib for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:42 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-439b2965d4bso1506874f8f.2 for ; Fri, 27 Mar 2026 04:17:39 -0700 (PDT) Received: from lanath.. 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The pending state is read-only for PPIs where the handling mode is Edge. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- target/arm/cpu.h | 1 + target/arm/tcg/gicv5-cpuif.c | 44 ++++++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4574f7005d..980abda3ca 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -606,6 +606,7 @@ typedef struct CPUArchState { /* Most PPI registers have 1 bit per PPI, so 64 PPIs to a register= */ uint64_t ppi_active[GICV5_NUM_PPIS / 64]; uint64_t ppi_hm[GICV5_NUM_PPIS / 64]; + uint64_t ppi_pend[GICV5_NUM_PPIS / 64]; } gicv5_cpuif; =20 struct { diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index e65bd56b3d..ee97d98d7e 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -199,6 +199,26 @@ static void gic_ppi_sactive_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, raw_write(env, ri, old | value); } =20 +static void gic_ppi_cpend_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t old =3D raw_read(env, ri); + /* If ICC_PPI_HMR_EL1[n].HM is 1, PEND bits are RO */ + uint64_t hm =3D env->gicv5_cpuif.ppi_hm[ri->opc2 & 1]; + value &=3D ~hm; + raw_write(env, ri, old & ~value); +} + +static void gic_ppi_spend_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t old =3D raw_read(env, ri); + /* If ICC_PPI_HMR_EL1[n].HM is 1, PEND bits are RO */ + uint64_t hm =3D env->gicv5_cpuif.ppi_hm[ri->opc2 & 1]; + value &=3D ~hm; + raw_write(env, ri, old | value); +} + static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { /* * Barrier: wait until the effects of a cpuif system register @@ -314,6 +334,30 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_hm[1]), .resetvalue =3D PPI_HMR1_RESET, }, + { .name =3D "ICC_PPI_CPENDR0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 13, .opc2 =3D 4, + .access =3D PL1_RW, .type =3D ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO= _RAW, + .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_pend[0]), + .writefn =3D gic_ppi_cpend_write, + }, + { .name =3D "ICC_PPI_CPENDR1_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 13, .opc2 =3D 5, + .access =3D PL1_RW, .type =3D ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO= _RAW, + .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_pend[1]), + .writefn =3D gic_ppi_cpend_write, + }, + { .name =3D "ICC_PPI_SPENDR0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 13, .opc2 =3D 6, + .access =3D PL1_RW, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_pend[0]), + .writefn =3D gic_ppi_spend_write, + }, + { .name =3D "ICC_PPI_SPENDR0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 13, .opc2 =3D 7, + .access =3D PL1_RW, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_pend[1]), + .writefn =3D gic_ppi_spend_write, + }, }; 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Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- target/arm/cpu.h | 1 + target/arm/tcg/gicv5-cpuif.c | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 980abda3ca..915a225f8e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -607,6 +607,7 @@ typedef struct CPUArchState { uint64_t ppi_active[GICV5_NUM_PPIS / 64]; uint64_t ppi_hm[GICV5_NUM_PPIS / 64]; uint64_t ppi_pend[GICV5_NUM_PPIS / 64]; + uint64_t ppi_enable[GICV5_NUM_PPIS / 64]; } gicv5_cpuif; =20 struct { diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index ee97d98d7e..09cd56cbfa 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -219,6 +219,12 @@ static void gic_ppi_spend_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, raw_write(env, ri, old | value); } =20 +static void gic_ppi_enable_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + raw_write(env, ri, value); +} + static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { /* * Barrier: wait until the effects of a cpuif system register @@ -334,6 +340,18 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_hm[1]), .resetvalue =3D PPI_HMR1_RESET, }, + { .name =3D "ICC_PPI_ENABLER0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 10, .opc2 =3D 6, + .access =3D PL1_RW, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_enable[0]), + .writefn =3D gic_ppi_enable_write, + }, + { .name =3D "ICC_PPI_ENABLER1_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 10, .opc2 =3D 7, + .access =3D PL1_RW, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_enable[1]), + .writefn =3D gic_ppi_enable_write, + }, { .name =3D "ICC_PPI_CPENDR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 13, .opc2 =3D 4, .access =3D PL1_RW, .type =3D ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO= _RAW, --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610611; cv=none; d=zohomail.com; s=zohoarc; b=Wka3JM7cbxrRlA9Nk67XpfzJxyfNVjUzPhiEHzoz1oQt6aezgInPvbXQj4martRkBylEjo42rVAbrnk55nTJLQWd4HcLsqhUzeiFGmhHo7a/GpaGYmJQxzld1K/NaeftBIZPXDBnr/SueQ5/EwsEioYOmMkXBWzfSKzwgTVjw/Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610611; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=zO8+icgVC1WFthhuPn3fXGZ2vtbwSvDSsbRmXizchEg=; b=OgMrvagL+mc9PEAs5435KKxcREu3GNqhfsov/pV0G8XQv3qPBdCCt76GTEYXZQJgGyDzQVblkMKDfGi/c4FcXKsFJfQRhbjG8Lfk6e3vJVOl7bXcYiGjUgt4KyuaUYsmceok7hY1a2AMnCvuzjnNjFUROWJ4/WZMKkvjFTA+yc8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610611762987.4146055252265; Fri, 27 Mar 2026 04:23:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65CD-00071s-8W; Fri, 27 Mar 2026 07:17:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65CC-00070f-21 for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:44 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65CA-0008FE-07 for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:43 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-48557c8ad47so14776045e9.0 for ; Fri, 27 Mar 2026 04:17:41 -0700 (PDT) Received: from lanath.. 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Each 64-bit register has the priority fields for 8 PPIs, so there are 16 registers in total. This would be a lot of duplication if we wrote it out statically in the array, so instead create each register via a loop in define_gicv5_cpuif_regs(). Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- target/arm/cpu.h | 2 ++ target/arm/tcg/gicv5-cpuif.c | 23 +++++++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 915a225f8e..b97f659352 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -608,6 +608,8 @@ typedef struct CPUArchState { uint64_t ppi_hm[GICV5_NUM_PPIS / 64]; uint64_t ppi_pend[GICV5_NUM_PPIS / 64]; uint64_t ppi_enable[GICV5_NUM_PPIS / 64]; + /* The PRIO regs have 1 byte per PPI, so 8 PPIs to a register */ + uint64_t ppi_priority[GICV5_NUM_PPIS / 8]; } gicv5_cpuif; =20 struct { diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 09cd56cbfa..74132ca097 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -225,6 +225,12 @@ static void gic_ppi_enable_write(CPUARMState *env, con= st ARMCPRegInfo *ri, raw_write(env, ri, value); } =20 +static void gic_ppi_priority_write(CPUARMState *env, const ARMCPRegInfo *r= i, + uint64_t value) +{ + raw_write(env, ri, value); +} + static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { /* * Barrier: wait until the effects of a cpuif system register @@ -382,5 +388,22 @@ void define_gicv5_cpuif_regs(ARMCPU *cpu) { if (cpu_isar_feature(aa64_gcie, cpu)) { define_arm_cp_regs(cpu, gicv5_cpuif_reginfo); + + /* + * There are 16 ICC_PPI_PRIORITYR_EL1 regs, so define them + * programmatically rather than listing them all statically. + */ + for (int i =3D 0; i < 16; i++) { + g_autofree char *name =3D g_strdup_printf("ICC_PPI_PRIORITYR%d= _EL1", i); + ARMCPRegInfo ppi_prio =3D { + .name =3D name, .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, + .crm =3D 14 + (i >> 3), .opc2 =3D i & 7, + .access =3D PL1_RW, .type =3D ARM_CP_IO, + .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_pri= ority[i]), + .writefn =3D gic_ppi_priority_write, .raw_writefn =3D raw_= write, + }; + define_one_arm_cp_reg(cpu, &ppi_prio); + } } } --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610508; cv=none; d=zohomail.com; s=zohoarc; b=LtA2IE6ymzUKedMFEW7AlM0hMPHFtZlB0OMEDII8jwfU5y0LeoE3NZjc+i7foXNLaRB7Ja/PJllyO7yJFoFyImQ3UjA2myXD91coSwEEhJheupa7u7YYADLINZB4l02W8fcaMYEg/Y/CwhwQMcT/T2R95RbVv+7sxTTMNIVbWm8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610508; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=rWiLavvxAVAygJhnwAz/WH2EaKWfbUPcvwYUiTpOfXM=; b=Cus2DAnZOSHMlFEN+xHV6EV5zdjZ1VVmYnBhnf7hN7v5Jimb68WVVIpU+gkl7CihhSSZ/T4NLYtCwj0ss2lJn6mYFjbm8czSukJ0l2X3rqlC+vcT2VD8eAM8B5YQGSdV69GkfuKiMp4Y+eMPj/3BqJsMdFRAQQk8V9EjANp+TMU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610508926776.7425001415517; Fri, 27 Mar 2026 04:21:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65CH-00076A-NY; Fri, 27 Mar 2026 07:17:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65CD-00071u-Hg for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:45 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65CB-0008Go-8C for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:45 -0400 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-439fe4985efso1507656f8f.3 for ; Fri, 27 Mar 2026 04:17:42 -0700 (PDT) Received: from lanath.. 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Since the GICv5 always uses 5 bits of priority, this register always has 32 non-RES0 bits, and we don't need the complicated GICv3 setup where there might be 1, 2 or 4 APR registers. ICC_HAPR_EL1 is a read-only register which reports the current running priority. This is defined to be the lowest set bit (i.e. the highest priority) in the APR, or the Idle priority 0xff if there are no active interrupts, so it is effectively a convenience re-presentation of the APR register data. The APR register is banked per interrupt domain; ICC_APR_EL1 accesses the version of the register corresponding to the current logical interrupt domain. The APR data for the final domain (EL3) is accessed via ICC_APR_EL3. Although we are starting with an EL1-only implementation, we define the CPU state as banked here so we don't have to change our representation of it later when we add EL3 and RME support. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- include/hw/intc/arm_gicv5_types.h | 2 ++ target/arm/cpu.h | 2 ++ target/arm/tcg/gicv5-cpuif.c | 60 +++++++++++++++++++++++++++++++ 3 files changed, 64 insertions(+) diff --git a/include/hw/intc/arm_gicv5_types.h b/include/hw/intc/arm_gicv5_= types.h index f6f8709a6a..5966ebde05 100644 --- a/include/hw/intc/arm_gicv5_types.h +++ b/include/hw/intc/arm_gicv5_types.h @@ -84,4 +84,6 @@ typedef enum GICv5TriggerMode { GICV5_TRIGGER_LEVEL =3D 1, } GICv5TriggerMode; =20 +#define PRIO_IDLE 0xff + #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b97f659352..6841b6748f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -35,6 +35,7 @@ #include "target/arm/gtimer.h" #include "target/arm/cpu-sysregs.h" #include "target/arm/mmuidx.h" +#include "hw/intc/arm_gicv5_types.h" =20 #define EXCP_UDEF 1 /* undefined instruction */ #define EXCP_SWI 2 /* software interrupt */ @@ -603,6 +604,7 @@ typedef struct CPUArchState { struct { /* GICv5 CPU interface data */ uint64_t icc_icsr_el1; + uint64_t icc_apr[NUM_GICV5_DOMAINS]; /* Most PPI registers have 1 bit per PPI, so 64 PPIs to a register= */ uint64_t ppi_active[GICV5_NUM_PPIS / 64]; uint64_t ppi_hm[GICV5_NUM_PPIS / 64]; diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 74132ca097..33e4762ef4 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -95,6 +95,16 @@ static GICv5Domain gicv5_current_phys_domain(CPUARMState= *env) return gicv5_logical_domain(env); } =20 +static uint64_t gic_running_prio(CPUARMState *env, GICv5Domain domain) +{ + /* + * Return the current running priority; this is the lowest set bit in + * the Active Priority Register, or the idle priority if none (D_XMBQZ) + */ + uint64_t hap =3D ctz64(env->gicv5_cpuif.icc_apr[domain]); + return hap < 32 ? hap : PRIO_IDLE; +} + static void gic_cddis_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -231,6 +241,44 @@ static void gic_ppi_priority_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, raw_write(env, ri, value); } =20 +/* + * ICC_APR_EL1 is banked and reads/writes as the version for the + * current logical interrupt domain. + */ +static void gic_icc_apr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * With an architectural 5 bits of priority, this register has 32 + * non-RES0 bits + */ + GICv5Domain domain =3D gicv5_logical_domain(env); + value &=3D 0xffffffff; + env->gicv5_cpuif.icc_apr[domain] =3D value; +} + +static uint64_t gic_icc_apr_el1_read(CPUARMState *env, const ARMCPRegInfo = *ri) +{ + GICv5Domain domain =3D gicv5_logical_domain(env); + return env->gicv5_cpuif.icc_apr[domain]; +} + +static void gic_icc_apr_el1_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + for (int i =3D 0; i < ARRAY_SIZE(env->gicv5_cpuif.icc_apr); i++) { + env->gicv5_cpuif.icc_apr[i] =3D 0; + } +} + +static uint64_t gic_icc_hapr_el1_read(CPUARMState *env, const ARMCPRegInfo= *ri) +{ + /* + * ICC_HAPR_EL1 reports the current running priority, which can be + * calculated from the APR register. + */ + return gic_running_prio(env, gicv5_current_phys_domain(env)); +} + static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { /* * Barrier: wait until the effects of a cpuif system register @@ -382,6 +430,18 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_pend[1]), .writefn =3D gic_ppi_spend_write, }, + { .name =3D "ICC_APR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .readfn =3D gic_icc_apr_el1_read, + .writefn =3D gic_icc_apr_el1_write, + .resetfn =3D gic_icc_apr_el1_reset, + }, + { .name =3D "ICC_HAPR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 12, .crm =3D 0, .opc2 =3D 3, + .access =3D PL1_R, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .readfn =3D gic_icc_hapr_el1_read, .raw_writefn =3D arm_cp_write_i= gnore, + }, }; =20 void define_gicv5_cpuif_regs(ARMCPU *cpu) --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610369; cv=none; d=zohomail.com; s=zohoarc; b=LktsWp550fG9AhqJDZ45wnK6FRnVb20urlk4xozDAm4+yCl/iIE+vxeHM7s5oEDWYKmfpsZ7ibmCW81m7pNz+rOqdFTDlk7Eggv9pw38CBbcisrBBqsOF6JRzeFAcHdInkbFQKuRejGaMBagrLoX1o/q/EwtoHrowOlSv8oBykY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610369; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=dm3ZhTnNkibm1ZUH9sNTVGo5VIBCJ1V2I2Dxuffa51g=; b=YBAvzQDywjhG1Glo06zEGh5XQZ7ESl3MzU4WYihyqg0lA/kGN/nijN6WTWO6aycPxBD8aRx76HayhMtc1+vUdWci06O+hR5Uf70wEfaDp5RGHNf76lxWLRHnRSedYHvrz2243HAO23vhQGvGentSl4MAAF55HebHV0AKDgMoe5g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610369233267.3312264883955; Fri, 27 Mar 2026 04:19:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65CJ-00076o-Or; Fri, 27 Mar 2026 07:17:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65CF-00073k-6U for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:47 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65CB-0008Ii-Sx for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:46 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-486b96760easo22060375e9.2 for ; Fri, 27 Mar 2026 04:17:43 -0700 (PDT) Received: from lanath.. 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In subsequent commits we will use this cached value to provide the HPPI info to the guest, decide whether to signal IRQ or FIQ, handle interrupt acknowldge from the guest, and so on. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- include/hw/intc/arm_gicv5_types.h | 21 +++++++++++ meson.build | 1 + target/arm/cpu.h | 3 ++ target/arm/tcg/gicv5-cpuif.c | 58 +++++++++++++++++++++++++++++++ target/arm/tcg/trace-events | 5 +++ target/arm/tcg/trace.h | 1 + 6 files changed, 89 insertions(+) create mode 100644 target/arm/tcg/trace-events create mode 100644 target/arm/tcg/trace.h diff --git a/include/hw/intc/arm_gicv5_types.h b/include/hw/intc/arm_gicv5_= types.h index 5966ebde05..eaed42f49f 100644 --- a/include/hw/intc/arm_gicv5_types.h +++ b/include/hw/intc/arm_gicv5_types.h @@ -12,6 +12,8 @@ #ifndef HW_INTC_ARM_GICv5_TYPES_H #define HW_INTC_ARM_GICv5_TYPES_H =20 +#include "hw/core/registerfields.h" + /* * The GICv5 has four physical Interrupt Domains. This numbering must * match the encoding used in IRS_IDR0.INT_DOM. @@ -86,4 +88,23 @@ typedef enum GICv5TriggerMode { =20 #define PRIO_IDLE 0xff =20 +/* + * We keep track of candidate highest possible pending interrupts + * using this struct. + * + * Unlike GICv3, we don't need a separate NMI bool, because for GICv5 + * superpriority is signaled by @prio =3D=3D 0. + * + * In this struct the intid includes the interrupt type in bits + * [31:29] (i.e. it is in the form defined by R_TJPHS). + */ +typedef struct GICv5PendingIrq { + uint32_t intid; + uint8_t prio; +} GICv5PendingIrq; + +/* Fields in a generic 32-bit INTID, per R_TJPHS */ +FIELD(INTID, ID, 0, 24) +FIELD(INTID, TYPE, 29, 3) + #endif diff --git a/meson.build b/meson.build index d7c4095b39..85a3ab293f 100644 --- a/meson.build +++ b/meson.build @@ -3684,6 +3684,7 @@ if have_system or have_user 'hw/core', 'target/arm', 'target/arm/hvf', + 'target/arm/tcg', 'target/hppa', 'target/i386', 'target/i386/kvm', diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6841b6748f..e0a7d02386 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -612,6 +612,9 @@ typedef struct CPUArchState { uint64_t ppi_enable[GICV5_NUM_PPIS / 64]; /* The PRIO regs have 1 byte per PPI, so 8 PPIs to a register */ uint64_t ppi_priority[GICV5_NUM_PPIS / 8]; + + /* Cached highest-priority pending PPI for each domain */ + GICv5PendingIrq ppi_hppi[NUM_GICV5_DOMAINS]; } gicv5_cpuif; =20 struct { diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 33e4762ef4..6f8062ba17 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -11,6 +11,7 @@ #include "internals.h" #include "cpregs.h" #include "hw/intc/arm_gicv5_stream.h" +#include "trace.h" =20 FIELD(GIC_CDPRI, ID, 0, 24) FIELD(GIC_CDPRI, TYPE, 29, 3) @@ -105,6 +106,57 @@ static uint64_t gic_running_prio(CPUARMState *env, GIC= v5Domain domain) return hap < 32 ? hap : PRIO_IDLE; } =20 +static void gic_recalc_ppi_hppi(CPUARMState *env) +{ + /* + * Recalculate the HPPI PPI: this is the best PPI which is + * enabled, pending and not active. + */ + for (int i =3D 0; i < ARRAY_SIZE(env->gicv5_cpuif.ppi_hppi); i++) { + env->gicv5_cpuif.ppi_hppi[i].intid =3D 0; + env->gicv5_cpuif.ppi_hppi[i].prio =3D PRIO_IDLE; + }; + + for (int i =3D 0; i < ARRAY_SIZE(env->gicv5_cpuif.ppi_active); i++) { + uint64_t en_pend_nact =3D env->gicv5_cpuif.ppi_enable[i] & + env->gicv5_cpuif.ppi_pend[i] & + ~env->gicv5_cpuif.ppi_active[i]; + + while (en_pend_nact) { + /* + * When EL3 is supported ICC_PPI_DOMAINR_EL3 tells us + * the domain of each PPI. While we only support EL1, the + * domain is always NS. + */ + GICv5Domain ppi_domain =3D GICV5_ID_NS; + uint8_t prio; + int ppi; + int bit =3D ctz64(en_pend_nact); + + en_pend_nact &=3D ~(1 << bit); + + ppi =3D i * 64 + bit; + prio =3D extract64(env->gicv5_cpuif.ppi_priority[ppi / 8], + (ppi & 7) * 8, 5); + + if (prio < env->gicv5_cpuif.ppi_hppi[ppi_domain].prio) { + uint32_t intid =3D 0; + + intid =3D FIELD_DP32(intid, INTID, ID, ppi); + intid =3D FIELD_DP32(intid, INTID, TYPE, GICV5_PPI); + env->gicv5_cpuif.ppi_hppi[ppi_domain].intid =3D intid; + env->gicv5_cpuif.ppi_hppi[ppi_domain].prio =3D prio; + } + } + } + + for (int i =3D 0; i < ARRAY_SIZE(env->gicv5_cpuif.ppi_hppi); i++) { + trace_gicv5_recalc_ppi_hppi(i, + env->gicv5_cpuif.ppi_hppi[i].intid, + env->gicv5_cpuif.ppi_hppi[i].prio); + } +} + static void gic_cddis_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -200,6 +252,7 @@ static void gic_ppi_cactive_write(CPUARMState *env, con= st ARMCPRegInfo *ri, { uint64_t old =3D raw_read(env, ri); raw_write(env, ri, old & ~value); + gic_recalc_ppi_hppi(env); } =20 static void gic_ppi_sactive_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -207,6 +260,7 @@ static void gic_ppi_sactive_write(CPUARMState *env, con= st ARMCPRegInfo *ri, { uint64_t old =3D raw_read(env, ri); raw_write(env, ri, old | value); + gic_recalc_ppi_hppi(env); } =20 static void gic_ppi_cpend_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -217,6 +271,7 @@ static void gic_ppi_cpend_write(CPUARMState *env, const= ARMCPRegInfo *ri, uint64_t hm =3D env->gicv5_cpuif.ppi_hm[ri->opc2 & 1]; value &=3D ~hm; raw_write(env, ri, old & ~value); + gic_recalc_ppi_hppi(env); } =20 static void gic_ppi_spend_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -227,18 +282,21 @@ static void gic_ppi_spend_write(CPUARMState *env, con= st ARMCPRegInfo *ri, uint64_t hm =3D env->gicv5_cpuif.ppi_hm[ri->opc2 & 1]; value &=3D ~hm; raw_write(env, ri, old | value); + gic_recalc_ppi_hppi(env); } =20 static void gic_ppi_enable_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { raw_write(env, ri, value); + gic_recalc_ppi_hppi(env); } =20 static void gic_ppi_priority_write(CPUARMState *env, const ARMCPRegInfo *r= i, uint64_t value) { raw_write(env, ri, value); + gic_recalc_ppi_hppi(env); } =20 /* diff --git a/target/arm/tcg/trace-events b/target/arm/tcg/trace-events new file mode 100644 index 0000000000..7dc5f781c5 --- /dev/null +++ b/target/arm/tcg/trace-events @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# See docs/devel/tracing.rst for syntax documentation. + +# gicv5-cpuif.c +gicv5_recalc_ppi_hppi(int domain, uint32_t id, uint8_t prio) "domain %d ne= w PPI HPPI id 0x%x prio %u" diff --git a/target/arm/tcg/trace.h b/target/arm/tcg/trace.h new file mode 100644 index 0000000000..c6e89d018b --- /dev/null +++ b/target/arm/tcg/trace.h @@ -0,0 +1 @@ +#include "trace/trace-target_arm_tcg.h" --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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We implement this in the irs_recalc_hppi() function, which we call at every point where some relevant IRS state changes. This function calls gicv5_forward_interrupt() to do the equivalent of the GICv5 stream protocol Forward and Recall commands. For the moment we simply record the HPPI on the CPU interface side without trying to process it; the handling of the HPPI in the cpuif will be added in subsequent commits. There are some cases where we could skip doing the full HPPI recalculation, e.g. when the guest changes the config of an interrupt that is disabled; we expect that the guest will only do interrupt config at startup, so we don't attempt to optimise this. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5.c | 202 +++++++++++++++++++++++++++++ hw/intc/trace-events | 2 + include/hw/intc/arm_gicv5.h | 3 + include/hw/intc/arm_gicv5_stream.h | 24 ++++ target/arm/tcg/gicv5-cpuif.c | 9 ++ 5 files changed, 240 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 989492d4b6..12cbf9c51e 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -376,6 +376,157 @@ static MemTxAttrs irs_txattrs(GICv5Common *cs, GICv5D= omain domain) }; } =20 +/* Data we need to pass through to lpi_cache_get_hppi() */ +typedef struct GetHPPIUserData { + GICv5PendingIrq *best; + uint32_t iaffid; +} GetHPPIUserData; + +static void lpi_cache_get_hppi(gpointer key, gpointer value, gpointer user= _data) +{ + uint64_t id =3D GPOINTER_TO_INT(key); + uint64_t l2_iste =3D *(uint64_t *)value; + uint32_t prio, iaffid; + GetHPPIUserData *ud =3D user_data; + + if ((l2_iste & (R_L2_ISTE_PENDING_MASK | R_L2_ISTE_ACTIVE_MASK | R_L2_= ISTE_ENABLE_MASK)) + !=3D (R_L2_ISTE_PENDING_MASK | R_L2_ISTE_ENABLE_MASK)) { + return; + } + prio =3D FIELD_EX32(l2_iste, L2_ISTE, PRIORITY); + iaffid =3D FIELD_EX32(l2_iste, L2_ISTE, IAFFID); + if (iaffid =3D=3D ud->iaffid && prio < ud->best->prio) { + id =3D FIELD_DP32(id, INTID, TYPE, GICV5_LPI); + ud->best->intid =3D id; + ud->best->prio =3D prio; + } +} + +static int irs_cpuidx_from_iaffid(GICv5Common *cs, uint32_t iaffid) +{ + for (int i =3D 0; i < cs->num_cpus; i++) { + if (cs->cpu_iaffids[i] =3D=3D iaffid) { + return i; + } + } + return -1; +} + +static void irs_recalc_hppi(GICv5 *s, GICv5Domain domain, uint32_t iaffid) +{ + /* + * Recalculate the highest priority pending interrupt for the + * specified domain and cpuif. HPPI candidates must be pending, + * inactive and enabled. + */ + GICv5Common *cs =3D ARM_GICV5_COMMON(s); + int cpuidx =3D irs_cpuidx_from_iaffid(cs, iaffid); + ARMCPU *cpu =3D cpuidx >=3D 0 ? cs->cpus[cpuidx] : NULL; + GICv5PendingIrq best; + + best.intid =3D 0; + best.prio =3D PRIO_IDLE; + + if (!cpu) { + /* Nothing happens for iaffids targeting nonexistent CPUs */ + trace_gicv5_irs_recalc_hppi_fail(domain_name[domain], iaffid, + "IAFFID doesn't match any CPU"); + return; + } + + if (!FIELD_EX32(cs->irs_cr0[domain], IRS_CR0, IRSEN)) { + /* When the IRS is disabled we don't forward HPPIs */ + trace_gicv5_irs_recalc_hppi_fail(domain_name[domain], iaffid, + "IRS_CR0.IRSEN is zero"); + return; + } + + if (s->phys_lpi_config[domain].valid) { + GetHPPIUserData ud; + + ud.best =3D &best; + ud.iaffid =3D iaffid; + g_hash_table_foreach(s->phys_lpi_config[domain].lpi_cache, + lpi_cache_get_hppi, &ud); + } + + /* + * OPT: consider also caching the SPI interrupt information, + * similarly to how we handle LPIs, if iterating through the whole + * SPI array every time is too expensive. + */ + for (int i =3D 0; i < cs->spi_irs_range; i++) { + GICv5SPIState *spi =3D &cs->spi[i]; + + if (spi->active || !spi->pending || !spi->enabled) { + continue; + } + if (spi->domain !=3D domain || spi->iaffid !=3D iaffid) { + continue; + } + if (spi->priority < best.prio) { + uint32_t intid =3D 0; + intid =3D FIELD_DP32(intid, INTID, ID, i); + intid =3D FIELD_DP32(intid, INTID, TYPE, GICV5_SPI); + best.intid =3D intid; + best.prio =3D spi->priority; + } + } + + trace_gicv5_irs_recalc_hppi(domain_name[domain], iaffid, + best.intid, best.prio); + + s->hppi[domain][cpuidx] =3D best; + /* + * Now present the HPPI to the cpuif. In the real hardware stream + * protocol, the connection between IRS and cpuif is asynchronous, + * and so both ends track their idea of the current HPPI, with a + * back-and-forth sequence so they stay in sync and more + * interaction when the cpuif resets. For QEMU, we are strictly + * synchronous and the cpuif asking the IRS for data is a cheap + * function call, so we simplify this: + * - the IRS knows what the current HPPI is + * - s->hppi[][] is a cache we can recalculate + * - the IRS merely tells the cpuif "something changed", and + * the cpuif asks for the current HPPI when it needs it + * - the cpuif does not cache the HPPI on its end + */ + gicv5_forward_interrupt(cpu, domain); +} + +static void irs_recalc_hppi_all_cpus(GICv5 *s, GICv5Domain domain) +{ + /* + * Recalculate the HPPI for every CPU for this domain. This is + * not as efficient as it could be because we will scan through + * the LPI cached hash table and the SPI array for each CPU rather + * than doing a single combined scan, but we only need to do this + * very rarely, when the guest enables or disables the IST, so we + * implement this the simple way. + */ + GICv5Common *cs =3D ARM_GICV5_COMMON(s); + for (int i =3D 0; i < cs->num_cpus; i++) { + irs_recalc_hppi(s, domain, cs->cpu_iaffids[i]); + } +} + +static void irs_recall_hppis(GICv5 *s, GICv5Domain domain) +{ + /* + * The IRS was just disabled -- we must recall any pending HPPIs + * we have sent to the CPU interfaces. For us this means that we + * clear our cached HPPI data and tell the cpuif that it has + * changed. + */ + GICv5Common *cs =3D ARM_GICV5_COMMON(s); + + for (int i =3D 0; i < cs->num_cpus; i++) { + s->hppi[domain][i].intid =3D 0; + s->hppi[domain][i].prio =3D PRIO_IDLE; + gicv5_forward_interrupt(cs->cpus[i], domain); + } +} + static hwaddr l1_iste_addr(GICv5Common *cs, const GICv5ISTConfig *cfg, uint32_t id) { @@ -575,6 +726,7 @@ void gicv5_set_priority(GICv5Common *cs, uint32_t id, u= int8_t priority, GICv5Domain domain, GICv5IntType type, bool virtua= l) { GICv5 *s =3D ARM_GICV5(cs); + uint32_t iaffid; =20 trace_gicv5_set_priority(domain_name[domain], inttype_name(type), virt= ual, id, priority); @@ -598,6 +750,7 @@ void gicv5_set_priority(GICv5Common *cs, uint32_t id, u= int8_t priority, return; } *l2_iste_p =3D FIELD_DP32(*l2_iste_p, L2_ISTE, PRIORITY, priority); + iaffid =3D FIELD_EX32(*l2_iste_p, L2_ISTE, IAFFID); put_l2_iste(cs, cfg, &h); break; } @@ -612,6 +765,7 @@ void gicv5_set_priority(GICv5Common *cs, uint32_t id, u= int8_t priority, } =20 spi->priority =3D priority; + iaffid =3D spi->iaffid; break; } default: @@ -619,12 +773,15 @@ void gicv5_set_priority(GICv5Common *cs, uint32_t id,= uint8_t priority, "priority of bad interrupt type %d\n", type); return; } + + irs_recalc_hppi(s, domain, iaffid); } =20 void gicv5_set_enabled(GICv5Common *cs, uint32_t id, bool enabled, GICv5Domain domain, GICv5IntType type, bool virtual) { GICv5 *s =3D ARM_GICV5(cs); + uint32_t iaffid; =20 trace_gicv5_set_enabled(domain_name[domain], inttype_name(type), virtu= al, id, enabled); @@ -645,6 +802,7 @@ void gicv5_set_enabled(GICv5Common *cs, uint32_t id, bo= ol enabled, return; } *l2_iste_p =3D FIELD_DP32(*l2_iste_p, L2_ISTE, ENABLE, enabled); + iaffid =3D FIELD_EX32(*l2_iste_p, L2_ISTE, IAFFID); put_l2_iste(cs, cfg, &h); break; } @@ -659,6 +817,7 @@ void gicv5_set_enabled(GICv5Common *cs, uint32_t id, bo= ol enabled, } =20 spi->enabled =3D true; + iaffid =3D spi->iaffid; break; } default: @@ -666,12 +825,15 @@ void gicv5_set_enabled(GICv5Common *cs, uint32_t id, = bool enabled, "enable state of bad interrupt type %d\n", type); return; } + + irs_recalc_hppi(s, domain, iaffid); } =20 void gicv5_set_pending(GICv5Common *cs, uint32_t id, bool pending, GICv5Domain domain, GICv5IntType type, bool virtual) { GICv5 *s =3D ARM_GICV5(cs); + uint32_t iaffid; =20 trace_gicv5_set_pending(domain_name[domain], inttype_name(type), virtu= al, id, pending); @@ -692,6 +854,7 @@ void gicv5_set_pending(GICv5Common *cs, uint32_t id, bo= ol pending, return; } *l2_iste_p =3D FIELD_DP32(*l2_iste_p, L2_ISTE, PENDING, pending); + iaffid =3D FIELD_EX32(*l2_iste_p, L2_ISTE, IAFFID); put_l2_iste(cs, cfg, &h); break; } @@ -706,6 +869,7 @@ void gicv5_set_pending(GICv5Common *cs, uint32_t id, bo= ol pending, } =20 spi->pending =3D true; + iaffid =3D spi->iaffid; break; } default: @@ -713,6 +877,8 @@ void gicv5_set_pending(GICv5Common *cs, uint32_t id, bo= ol pending, "pending state of bad interrupt type %d\n", type); return; } + + irs_recalc_hppi(s, domain, iaffid); } =20 void gicv5_set_handling(GICv5Common *cs, uint32_t id, @@ -767,6 +933,7 @@ void gicv5_set_target(GICv5Common *cs, uint32_t id, uin= t32_t iaffid, GICv5IntType type, bool virtual) { GICv5 *s =3D ARM_GICV5(cs); + uint32_t old_iaffid; =20 trace_gicv5_set_target(domain_name[domain], inttype_name(type), virtua= l, id, iaffid, irm); @@ -800,6 +967,7 @@ void gicv5_set_target(GICv5Common *cs, uint32_t id, uin= t32_t iaffid, * L2_ISTE.IRM is RES0. We never read it, and we can skip * explicitly writing it to zero here. */ + old_iaffid =3D FIELD_EX32(*l2_iste_p, L2_ISTE, IAFFID); *l2_iste_p =3D FIELD_DP32(*l2_iste_p, L2_ISTE, IAFFID, iaffid); put_l2_iste(cs, cfg, &h); break; @@ -814,6 +982,7 @@ void gicv5_set_target(GICv5Common *cs, uint32_t id, uin= t32_t iaffid, return; } =20 + old_iaffid =3D spi->iaffid; spi->iaffid =3D iaffid; break; } @@ -822,6 +991,9 @@ void gicv5_set_target(GICv5Common *cs, uint32_t id, uin= t32_t iaffid, "target of bad interrupt type %d\n", type); return; } + + irs_recalc_hppi(s, domain, old_iaffid); + irs_recalc_hppi(s, domain, iaffid); } =20 static uint64_t l2_iste_to_icsr(GICv5Common *cs, const GICv5ISTConfig *cfg, @@ -942,6 +1114,12 @@ static void irs_map_l2_istr_write(GICv5 *s, GICv5Doma= in domain, uint64_t value) if (res !=3D MEMTX_OK) { goto txfail; } + /* + * It's CONSTRAINED UNPREDICTABLE to make an L2 IST valid when + * some of its entries have Pending already set, so we don't need + * to go through looking for Pending bits and pulling them into + * the cache, and we don't need to recalc our HPPI. + */ return; =20 txfail: @@ -999,6 +1177,7 @@ static void irs_ist_baser_write(GICv5 *s, GICv5Domain = domain, uint64_t value) IRS_IST_BASER, VALID, valid= ); s->phys_lpi_config[domain].valid =3D false; trace_gicv5_ist_invalid(domain_name[domain]); + irs_recalc_hppi_all_cpus(s, domain); return; } cs->irs_ist_baser[domain] =3D value; @@ -1068,6 +1247,7 @@ static void irs_ist_baser_write(GICv5 *s, GICv5Domain= domain, uint64_t value) cfg->valid =3D true; trace_gicv5_ist_valid(domain_name[domain], cfg->base, cfg->id_bits, cfg->l2_idx_bits, cfg->istsz, cfg->structure= ); + irs_recalc_hppi_all_cpus(s, domain); } } =20 @@ -1223,6 +1403,11 @@ static bool config_readl(GICv5 *s, GICv5Domain domai= n, hwaddr offset, case A_IRS_CR0: /* Enabling is instantaneous for us so IDLE is always 1 */ *data =3D cs->irs_cr0[domain] | R_IRS_CR0_IDLE_MASK; + if (FIELD_EX32(cs->irs_cr0[domain], IRS_CR0, IRSEN)) { + irs_recalc_hppi_all_cpus(s, domain); + } else { + irs_recall_hppis(s, domain); + } return true; case A_IRS_CR1: *data =3D cs->irs_cr1[domain]; @@ -1311,6 +1496,7 @@ static bool config_writel(GICv5 *s, GICv5Domain domai= n, hwaddr offset, } else if (spi->level) { spi->pending =3D false; } + irs_recalc_hppi(s, spi->domain, spi->iaffid); } } return true; @@ -1320,7 +1506,12 @@ static bool config_writel(GICv5 *s, GICv5Domain doma= in, hwaddr offset, /* this is RAZ/WI except for the EL3 domain */ GICv5SPIState *spi =3D spi_for_selr(cs, domain); if (spi) { + GICv5Domain old_domain =3D spi->domain; spi->domain =3D FIELD_EX32(data, IRS_SPI_DOMAINR, DOMAIN); + if (spi->domain !=3D old_domain) { + irs_recalc_hppi(s, old_domain, spi->iaffid); + irs_recalc_hppi(s, spi->domain, spi->iaffid); + } } } return true; @@ -1331,6 +1522,7 @@ static bool config_writel(GICv5 *s, GICv5Domain domai= n, hwaddr offset, =20 if (spi) { spi_sample(spi); + irs_recalc_hppi(s, spi->domain, spi->iaffid); } trace_gicv5_spi_state(id, spi->level, spi->pending, spi->active); return true; @@ -1499,6 +1691,7 @@ static void gicv5_set_spi(void *opaque, int irq, int = level) { /* These irqs are all SPIs; the INTID is irq + s->spi_base */ GICv5Common *cs =3D ARM_GICV5_COMMON(opaque); + GICv5 *s =3D ARM_GICV5(cs); uint32_t spi_id =3D irq + cs->spi_base; GICv5SPIState *spi =3D gicv5_raw_spi_state(cs, spi_id); =20 @@ -1511,6 +1704,8 @@ static void gicv5_set_spi(void *opaque, int irq, int = level) spi->level =3D level; spi_sample(spi); trace_gicv5_spi_state(spi_id, spi->level, spi->pending, spi->active); + + irs_recalc_hppi(s, spi->domain, spi->iaffid); } =20 static void gicv5_reset_hold(Object *obj, ResetType type) @@ -1591,6 +1786,7 @@ static void gicv5_set_idregs(GICv5Common *cs) =20 static void gicv5_realize(DeviceState *dev, Error **errp) { + GICv5 *s =3D ARM_GICV5(dev); GICv5Common *cs =3D ARM_GICV5_COMMON(dev); GICv5Class *gc =3D ARM_GICV5_GET_CLASS(dev); Error *migration_blocker =3D NULL; @@ -1618,6 +1814,12 @@ static void gicv5_realize(DeviceState *dev, Error **= errp) =20 gicv5_set_idregs(cs); gicv5_common_init_irqs_and_mmio(cs, gicv5_set_spi, config_frame_ops); + + for (int i =3D 0; i < NUM_GICV5_DOMAINS; i++) { + if (gicv5_domain_implemented(cs, i)) { + s->hppi[i] =3D g_new0(GICv5PendingIrq, cs->num_cpus); + } + } } =20 static void gicv5_init(Object *obj) diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 4c55af2780..6475ba5959 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -242,6 +242,8 @@ gicv5_set_handling(const char *domain, const char *type= , bool virtual, uint32_t gicv5_set_target(const char *domain, const char *type, bool virtual, uint3= 2_t id, uint32_t iaffid, int irm) "GICv5 IRS SetTarget %s %s virtual:%d ID = %u IAFFID %u routingmode %d" gicv5_request_config(const char *domain, const char *type, bool virtual, u= int32_t id, uint64_t icsr) "GICv5 IRS RequestConfig %s %s virtual:%d ID %u = ICSR 0x%" PRIx64 gicv5_spi_state(uint32_t spi_id, bool level, bool pending, bool active) "G= ICv5 IRS SPI ID %u now level %d pending %d active %d" +gicv5_irs_recalc_hppi_fail(const char *domain, uint32_t iaffid, const char= *reason) "GICv5 IRS %s IAFFID %u: no HPPI: %s" +gicv5_irs_recalc_hppi(const char *domain, uint32_t iaffid, uint32_t id, ui= nt8_t prio) "GICv5 IRS %s IAFFID %u: new HPPI ID 0x%x prio %u" =20 # arm_gicv5_common.c gicv5_common_realize(uint32_t irsid, uint32_t num_cpus, uint32_t spi_base,= uint32_t spi_irs_range, uint32_t spi_range) "GICv5 IRS realized: IRS ID %u= , %u CPUs, SPI base %u, SPI IRS range %u, SPI range %u" diff --git a/include/hw/intc/arm_gicv5.h b/include/hw/intc/arm_gicv5.h index fb13de0d01..b8baf003ad 100644 --- a/include/hw/intc/arm_gicv5.h +++ b/include/hw/intc/arm_gicv5.h @@ -37,6 +37,9 @@ struct GICv5 { =20 /* This is the info from IRS_IST_BASER and IRS_IST_CFGR */ GICv5ISTConfig phys_lpi_config[NUM_GICV5_DOMAINS]; + + /* We cache the HPPI for each CPU for each domain here */ + GICv5PendingIrq *hppi[NUM_GICV5_DOMAINS]; }; =20 struct GICv5Class { diff --git a/include/hw/intc/arm_gicv5_stream.h b/include/hw/intc/arm_gicv5= _stream.h index 136b6339ee..60c470b84c 100644 --- a/include/hw/intc/arm_gicv5_stream.h +++ b/include/hw/intc/arm_gicv5_stream.h @@ -151,4 +151,28 @@ void gicv5_set_target(GICv5Common *cs, uint32_t id, ui= nt32_t iaffid, uint64_t gicv5_request_config(GICv5Common *cs, uint32_t id, GICv5Domain do= main, GICv5IntType type, bool virtual); =20 +/** + * gicv5_forward_interrupt + * @cpu: CPU interface to forward interrupt to + * @domain: domain this interrupt is for + * + * Tell the CPU interface that the highest priority pending interrupt + * that the IRS has available for it has changed. This is the + * equivalent of the stream protocol's Forward packet, and also of its + * Recall packet. + * + * The stream protocol makes this asynchronous, allowing two Forward + * packets to be in flight and requiring an acknowledge, because the + * cpuif might be about to activate the previous forwarded interrupt + * while we are trying to tell it about a new one. But for QEMU we + * hold the BQL, so we know the vcpu might be executing guest code but + * it cannot be in the middle of changing cpuif state. So we can just + * synchronously tell it that a new HPPI exists (which might cause it + * to assert IRQ or FIQ to itself); this works as if the cpuif gave us + * a Release for the old HPPI. The cpuif will ask the IRS for the + * HPPI info via a function call, so we do not need to pass it across + * here. + */ +void gicv5_forward_interrupt(ARMCPU *cpu, GICv5Domain domain); + #endif diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 6f8062ba17..ed7c30c07c 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -157,6 +157,15 @@ static void gic_recalc_ppi_hppi(CPUARMState *env) } } =20 +void gicv5_forward_interrupt(ARMCPU *cpu, GICv5Domain domain) +{ + /* + * For now, we do nothing. Later we will recalculate the overall + * HPPI by combining the IRS HPPI with the PPI HPPI, and possibly + * signal IRQ/FIQ. + */ +} + static void gic_cddis_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610831; cv=none; d=zohomail.com; s=zohoarc; b=IE0rxWTnwxnRNmUCXr6j9JMmSh3/yP8dudZy/fiSx/tA9No7teX4RMLghRTTjYVmERY0GItJIVDp6qfmnbjRTy+h7zMwdxpNzKQGUIn3jHe/D38qV/7FjTL8Ugqj35TbXJ/+8kd8M4PnF/RHbO1aygix3wvOrwSFztr+UZDEwQI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610831; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=zvlMSNGdKIlUIEkOr6Lv47MQTuNcGu0po65x29YyYWY=; b=bDDL+odpP+T9EGUYKi8Mf/iiO5CXvCKTxzfxOTdTTemOsoKnWjNEwEI33wDGKtRM9jxobPlevHUIpp/pB55xkR9FYzLc9z8I+1PicZ6I1nr+ACxa/JeSCtSTMm4LB2c8NOzh3SjAMqFoon5+DX1P0Gj1vne735gDobHXcjzL9J4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610831016945.8114421026764; Fri, 27 Mar 2026 04:27:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65CK-00077m-2q; Fri, 27 Mar 2026 07:17:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65CG-000748-BJ for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:48 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65CD-0008Lh-L0 for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:47 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-439b97a8a8cso2030565f8f.1 for ; Fri, 27 Mar 2026 04:17:45 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610264; x=1775215064; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zvlMSNGdKIlUIEkOr6Lv47MQTuNcGu0po65x29YyYWY=; b=xvA08muiTPDIAglBq2VgMo9I+53CQBL9ClNG+yD0wi0AQw8U/ERkNTETYr/yZ/JSXP V2YetGN2p91aoOasnpvSUKa4hIUM0dQx//yrMDScvzfd+qRiX5c37WX67COfjZFXwg2C y1AILrI9auvrrEBv3P6V3TVJ7NvFRQIEm7fYhPT1X+e1k8MHEGPa0HzhEizcESCy/768 u50bHlqiWFNdABfHP8rJ6FblFn8QrgNj26ov8JxHPURk+z8dzYAEqYmrisXo74d0bIUF PC64sbz5h/JoMfqMAw2tjkdtNmgoaEEu9hAVUWZi3vcHmJ8GQEtk8y8/rbGTcmWAJ2hB n++g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610264; x=1775215064; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=zvlMSNGdKIlUIEkOr6Lv47MQTuNcGu0po65x29YyYWY=; b=r+KkJWRruufYQQRrqZl/RPK0AMiVHirxjmGmP5s4AQsdu9yt7w+AkwV7nsxFlEt4va vn05JwPSjjDRX64NCGalDTgV3D5DSr/6lDNVPmyrUX0B2KFr3rQM4Pe22GSdlDhVpptk FpCQX0Kkk1vDitVLLtmE81M9dlgC7wvo9Bs5rZE26EP1gus/rnc+2hOzFf8LRx4dVLrH uJzejWNG3XPzH6XOk/QW50bTaMyKY9J2KlokgbaK++kGkUi2/V5CkOVjk4Ll5wvhv56u dP/ASWVLcVdeClxVl76+YE6WjVh89jiQHDGLFda++AlaAbJSgC3cr4ja/sKIQN/n9etu RKAw== X-Forwarded-Encrypted: i=1; AJvYcCUkl2A0qRxsrG3UWDmAGoETK99lslkvesJiwMEBxo9m8tzFMyyP09uNpqSb1oTWY0ZIyhW7qpYlrkGm@nongnu.org X-Gm-Message-State: AOJu0YwhQxPBVEA2Ryhm1BHEdUHsgs/dn+/9fbH0X4pcz1UiYw1vuM0s wfN9HgJOyV2ZE0h/1aOnN/6FTCC3CzWaoIZQg4BTR16yNe4tR3frOqvivLfUw/h6zh6QlAYL1fC qfaA0P/s= X-Gm-Gg: ATEYQzw8jZR0BLtHAsaKWF+nr+izQEPGpJ7Oe/rIiGBabfHDdLEdoQTh29xIBtaYAvK SDPNgssZMfJyUvRH6iu5xrnqxmKDTVAVPrGFalGUwtf0xuxnHYjx90gQVtR4RH75OvNQeAljzSp 94BAxTPpWrkMkTKUTHuvnoWnJPpZl2Rx8HGTw71xlj5itOA/UXlA95lxkbLjp/RWgnCTxNYAf8z EiqSfNn6NVACm8uEv0Q/DQDZToDuKEEY+DzSRRsQhrhAQlt0vGG1KdB5dYxwAc7c0O2B9e2c0PU PmmAnEgtxIaU/4lmwi3a/YbC5utJH/iuyYYN72Zmq/nltcE+rCFXC5jYqotZ5538/DfDDnoDQ5p 9c4y5H8nzAFAXGHkCpy8gbFNS/USUNQki65RgPdFlUGbNyWFNvgvXFiTBYqKcmLl667ozoc2M/u /eCQhlwAccBjlilITThShaXIzAKLabkFrpKnCwV2ESKg40nVGDHAX6qTFJqdy9kL8ySE9g4CdLU rREhapmX792q8fxYbqZ97JH80kAUDs= X-Received: by 2002:a05:6000:1787:b0:439:c5cf:fc73 with SMTP id ffacd0b85a97d-43b9e9e8c64mr3413778f8f.12.1774610264039; Fri, 27 Mar 2026 04:17:44 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 44/65] target/arm: GICv5 cpuif: Implement ICC_CR0_EL1 Date: Fri, 27 Mar 2026 11:16:39 +0000 Message-ID: <20260327111700.795099-45-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610833090154100 Content-Type: text/plain; charset="utf-8" Implement ICC_CR0_EL1, which is the main control register. This is banked between interrupt domains in the same way as ICC_APR_*. The GICv5 spec assumes that typically there will need to be a hardware handshake between the CPU and the IRS, which is kicked off by guest software setting a LINK bit in this register to bring the link between the two online. However it is permitted to have an implementation where the link is permanently up. We take advantage of this, so our LINK and LINK_IDLE bits are read-only and always 1. This means the only interesting bit in this register for us is the main enable bit: when disabled for a domain, the cpuif considers that there is never an available highest priority interrupt. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- target/arm/cpu.h | 1 + target/arm/tcg/gicv5-cpuif.c | 44 ++++++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e0a7d02386..1263841a1d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -605,6 +605,7 @@ typedef struct CPUArchState { /* GICv5 CPU interface data */ uint64_t icc_icsr_el1; uint64_t icc_apr[NUM_GICV5_DOMAINS]; + uint64_t icc_cr0[NUM_GICV5_DOMAINS]; /* Most PPI registers have 1 bit per PPI, so 64 PPIs to a register= */ uint64_t ppi_active[GICV5_NUM_PPIS / 64]; uint64_t ppi_hm[GICV5_NUM_PPIS / 64]; diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index ed7c30c07c..50aa81d74f 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -43,6 +43,12 @@ FIELD(ICC_IDR0_EL1, ID_BITS, 0, 4) FIELD(ICC_IDR0_EL1, PRI_BITS, 4, 4) FIELD(ICC_IDR0_EL1, GCIE_LEGACY, 8, 4) =20 +FIELD(ICC_CR0, EN, 0, 1) +FIELD(ICC_CR0, LINK, 1, 1) +FIELD(ICC_CR0, LINK_IDLE, 2, 1) +FIELD(ICC_CR0, IPPT, 32, 6) +FIELD(ICC_CR0, PID, 38, 1) + /* * We implement 24 bits of interrupt ID, the mandated 5 bits of priority, * and no legacy GICv3.3 vcpu interface (yet) @@ -346,6 +352,37 @@ static uint64_t gic_icc_hapr_el1_read(CPUARMState *env= , const ARMCPRegInfo *ri) return gic_running_prio(env, gicv5_current_phys_domain(env)); } =20 +/* ICC_CR0_EL1 is also banked */ +static uint64_t gic_icc_cr0_el1_read(CPUARMState *env, const ARMCPRegInfo = *ri) +{ + GICv5Domain domain =3D gicv5_logical_domain(env); + return env->gicv5_cpuif.icc_cr0[domain]; +} + +static void gic_icc_cr0_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * For our implementation the link to the IRI is always connected, + * so LINK and LINK_IDLE are always 1. Without EL3, PID and IPPT + * are RAZ/WI, so the only writeable bit is the main enable bit EN. + */ + GICv5Domain domain =3D gicv5_logical_domain(env); + value &=3D R_ICC_CR0_EN_MASK; + value |=3D R_ICC_CR0_LINK_MASK | R_ICC_CR0_LINK_IDLE_MASK; + + env->gicv5_cpuif.icc_cr0[domain] =3D value; +} + +static void gic_icc_cr0_el1_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* The link is always connected so we reset with LINK and LINK_IDLE se= t */ + for (int i =3D 0; i < ARRAY_SIZE(env->gicv5_cpuif.icc_cr0); i++) { + env->gicv5_cpuif.icc_cr0[i] =3D + R_ICC_CR0_LINK_MASK | R_ICC_CR0_LINK_IDLE_MASK; + } +} + static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { /* * Barrier: wait until the effects of a cpuif system register @@ -504,6 +541,13 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { .writefn =3D gic_icc_apr_el1_write, .resetfn =3D gic_icc_apr_el1_reset, }, + { .name =3D "ICC_CR0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 12, .crm =3D 0, .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .readfn =3D gic_icc_cr0_el1_read, + .writefn =3D gic_icc_cr0_el1_write, + .resetfn =3D gic_icc_cr0_el1_reset, + }, { .name =3D "ICC_HAPR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 1, .crn =3D 12, .crm =3D 0, .opc2 =3D 3, .access =3D PL1_R, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610748; cv=none; d=zohomail.com; s=zohoarc; b=Z/bqK64HF+6A+9cjAJ8qe7+a/d0Wnjt3kJYr6aUkhusn+hy1OUSqj/KqACHgyM5qkTIFD6NrXUKCGTVMNtka74PNaCm2zsDbamlTxWXvU/XmcNDBf7aF/0BzbLwvisjPdHxREh7iHQFYoRC/c7wY25tlJOMy8zBclgYkUi0wFtQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610748; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=SXyrPHrNeuNNGz1d/8IK0Sz1v5blPipkCHt4LvQFUGQ=; b=SMmoLZ0TBYMyXBDuFmEX8HeeFYrWthEI39mWmrHAo4nXtXOprHh93Cr99+4Fyl8w8ohdOje20pUkI3R41ggQgHhRFgIeCejxgRuKcJMI0GSfrYJXH59u80k7DTkfJfutT25fCbkjSyus1gmN7iRMp/gJaw6sr7xr4BTshdkHp8U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610748303373.2888956683263; Fri, 27 Mar 2026 04:25:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65CN-0007D0-GL; Fri, 27 Mar 2026 07:17:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65CH-00075S-2q for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:49 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65CE-0008Mi-It for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:48 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-48558d6ef83so18690575e9.3 for ; Fri, 27 Mar 2026 04:17:46 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610265; x=1775215065; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SXyrPHrNeuNNGz1d/8IK0Sz1v5blPipkCHt4LvQFUGQ=; b=HqKr8RpycMwHJTiydBjRkSsLu16gqDwVlY1zhgcV+5YWkFFKwnxptMDdddvEU1qp1p D7HrIipZnBQPqp9i6ZWGCisET0L9iOId39HBy8VkGPD4lB0IQknkOdx6BMWKf3Igyh2t /D4MOQ9b/Brrqp+0ZKO1N6Z/EXWJCQvuegvn+KbEiGGpi2ZP6KuX/rB8PzG1NAOzQEH2 sHm0tsxRI8NbNL66G92DfsoHDC4SSfFlZPTZ822yZBYfsw5EaOaIOF2VjA84cWPkpGcY IcLA+WIS+XBR8pT+NOTZ889VBAW1iNmSSCD+oIxX8OmKZR04hrRvrClwca3UQsNKf6Mi ZG+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610265; x=1775215065; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=SXyrPHrNeuNNGz1d/8IK0Sz1v5blPipkCHt4LvQFUGQ=; b=Vgl8r5lnbz2c4oA0xUduE4mReq+TPH8IlTpM5Tz1KBQ5nqEhpAFyv6LX6Lb7CDCvPg lYtLhwVU+FEDsUBBbIz862rljMKqlFIirDDnOsVtPLojt2NpgwL65pY+7INDaeA4QgF6 iuHsq+D5bT2iJe23E2h2cpoBOGZn5owVsAbkwJ0RTVFjd8ZSR9WbfEvCsRudPbjfUJ/B 1ZgWW4BUsh/rBWd4LVxXJCRhZAR8MW/tLNYKvdzv3W+VNlheV834RdW0XEwhwY61Lvtt 2/mO60iaWZaclKwBT7wTWuaaE0/ijRgn+CfcSvra/kd66558uTzseNoPmsKo/GYTjT9N +Q9A== X-Forwarded-Encrypted: i=1; AJvYcCV9yca5ea7RxbFnkVnR0WfqMsY2Z9Bg/4lGQkj2iMcAcN/M9NEp2JiDu6Em4xT6+bitr+9pk5So33j1@nongnu.org X-Gm-Message-State: AOJu0Yz8Gp/fIuBDjHjIFzJ4597nFqoAC5TOl2wYA8vEW04xqBx7Gh5M sTeOEIiHguCzSxGQ2Ha40Kxw2U9y9bhz4sA18JIGOoL4tWP7P0BbCYcXsgc21gkNpZk= X-Gm-Gg: ATEYQzxcd8TLWRqTt+9HVTb/tas0X9gDzEdNc5kEGnA/ZglWIzEPw/0morBlfkoV/Cw KGZq8fSTgwlnhzuCTfmHNTGidX8VwgEhV/vw9o3ZDg4o4v6EaV2ia/XbcZt0eq490DXHgBOXNqq Ma6SdMERvD2owqctnIzImzuhXUUwovm799TIcX93TCESgTFQKbu/XYnPJlEj2q1m3rOujYtxkuR QqLidWFxlCv04XSTwLrDr5+v2QMYNwZEsysL1d2eILYba0i0NljNZE56Hr+7Smc4zOYVfP+C6Cx 46ufBpWcNHhQ/coowikShhpvQOvBp7bCwmAvSen9iEc1H/KnSu+eZ5UwzwxDdpojDojV+b79w+V J0Tcgp3FOEkumcE4kJAAjbLZvPnWqJRQfPzPRz5ZL0UFgsu96MnbRH/d6a1I9OB0nu3A6AdPlV0 4P4aiKAuJ/pVmcYasrhRiqUmFFs07RQgk4WfeiDwRGV8sWtMdaMna+4Y3yfYZymQd3pmk8Omni3 bKppVJFMvrGG7uR+mH34tBgfGhVJtA= X-Received: by 2002:a05:600c:3586:b0:487:1fbf:e0bb with SMTP id 5b1f17b1804b1-48727d5a17cmr37323865e9.6.1774610264855; Fri, 27 Mar 2026 04:17:44 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 45/65] target/arm: GICv5 cpuif: Implement ICC_PCR_EL1 Date: Fri, 27 Mar 2026 11:16:40 +0000 Message-ID: <20260327111700.795099-46-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610749822154100 Content-Type: text/plain; charset="utf-8" Implement the ICC_PCR_* registers. These hold the physical priority mask for each interrupt domain -- an HPPI is only sufficiently high priority to preempt if it is higher priority than this mask value. Here we just implement the access to this data. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- target/arm/cpu.h | 1 + target/arm/tcg/gicv5-cpuif.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1263841a1d..651fccd59b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -606,6 +606,7 @@ typedef struct CPUArchState { uint64_t icc_icsr_el1; uint64_t icc_apr[NUM_GICV5_DOMAINS]; uint64_t icc_cr0[NUM_GICV5_DOMAINS]; + uint64_t icc_pcr[NUM_GICV5_DOMAINS]; /* Most PPI registers have 1 bit per PPI, so 64 PPIs to a register= */ uint64_t ppi_active[GICV5_NUM_PPIS / 64]; uint64_t ppi_hm[GICV5_NUM_PPIS / 64]; diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 50aa81d74f..b44b0d5398 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -49,6 +49,8 @@ FIELD(ICC_CR0, LINK_IDLE, 2, 1) FIELD(ICC_CR0, IPPT, 32, 6) FIELD(ICC_CR0, PID, 38, 1) =20 +FIELD(ICC_PCR, PRIORITY, 0, 5) + /* * We implement 24 bits of interrupt ID, the mandated 5 bits of priority, * and no legacy GICv3.3 vcpu interface (yet) @@ -383,6 +385,28 @@ static void gic_icc_cr0_el1_reset(CPUARMState *env, co= nst ARMCPRegInfo *ri) } } =20 +static uint64_t gic_icc_pcr_el1_read(CPUARMState *env, const ARMCPRegInfo = *ri) +{ + GICv5Domain domain =3D gicv5_logical_domain(env); + return env->gicv5_cpuif.icc_pcr[domain]; +} + +static void gic_icc_pcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + GICv5Domain domain =3D gicv5_logical_domain(env); + + value &=3D R_ICC_PCR_PRIORITY_MASK; + env->gicv5_cpuif.icc_pcr[domain] =3D value; +} + +static void gic_icc_pcr_el1_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + for (int i =3D 0; i < ARRAY_SIZE(env->gicv5_cpuif.icc_pcr); i++) { + env->gicv5_cpuif.icc_pcr[i] =3D 0; + } +} + static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { /* * Barrier: wait until the effects of a cpuif system register @@ -548,6 +572,13 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { .writefn =3D gic_icc_cr0_el1_write, .resetfn =3D gic_icc_cr0_el1_reset, }, + { .name =3D "ICC_PCR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 12, .crm =3D 0, .opc2 =3D 2, + .access =3D PL1_RW, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .readfn =3D gic_icc_pcr_el1_read, + .writefn =3D gic_icc_pcr_el1_write, + .resetfn =3D gic_icc_pcr_el1_reset, + }, { .name =3D "ICC_HAPR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 1, .crn =3D 12, .crm =3D 0, .opc2 =3D 3, .access =3D PL1_R, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610412; cv=none; d=zohomail.com; s=zohoarc; b=mzf76pufLk/NqXD+ph8AqnH4d4qIM8fL1vQfXVXHFix24j6vJecCl0BewtkXqgUnvOUq/uQ3+m+MA4FGAhRzXFjnmtEhZF/wo1j2jfvHqcrDucC0n1KWRQQoh9kxqqFF9ADJHc2W4UuFIZKZzhJa5B6Bgyt9S6iKAlhb/hhk+tw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610412; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=+PpzUIdcaAGfh+t+PosoBjEM0xn6FihXvA5kZznGsJk=; b=Kt/kDivNVKHUm9Ks5pmeKj51FiFQOHJ7DrWTcKShtN0jfiBCviwDigKGkObp3gL6tn4ql2Ex/quoVec0z9IUvbt+Otc4exe43sxyrZA9qXfsahQIC/kPEk5f7SfnTT1DLmiH3bdKjFQPgYOs9rJcB5e3wVDDks4EK8hNUntfbT0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610412668490.10353533483124; Fri, 27 Mar 2026 04:20:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65Cc-0007pw-3Q; Fri, 27 Mar 2026 07:18:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65CI-00076t-Fl for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:51 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65CF-0008NE-Vp for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:50 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-43b871dd06eso1154739f8f.0 for ; Fri, 27 Mar 2026 04:17:46 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610266; x=1775215066; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+PpzUIdcaAGfh+t+PosoBjEM0xn6FihXvA5kZznGsJk=; b=GJUv4C5ehAF9a44rDUtuswEQY/b+Yx91eF+CGHZ9enpgYUV8jpOYQ36kOpVtgaPSis 5G6mYVcv49yrVle4vod2AEAehNqAk32Pm32bjIL/hTlAYp82h7k6fRa3UChZRkml69Mv fSGIrrU9rTJ4WtoXy6MnvXBFpd+lKGvGqfpM3iQYaN8cX7RlH/ayYknnYtHsoGE0gOTo oDZQSqZwUxtV1zntl2Apx1+gteHPoFqtUvZTgR/tk9niIVUT4YiLgdYCnwa/a4LxNNFA Y+c00VsdCTWs2tNCzsE86zRLMZjtoiOUFsdvb8SdLnEP3BffZ689MVsRvZTWmDuk5fG0 qm2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610266; x=1775215066; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=+PpzUIdcaAGfh+t+PosoBjEM0xn6FihXvA5kZznGsJk=; b=DAJrrFXdEBCIw4VRxepDlpleG/V6nIH4THrkfJxT1CwnJ8DV8kPGxxE2RY9r/jdnQl 2mkX9ps27CjRYFmEtntLHmKHJ0LngIA4dNYn+bfoojznbKE2zO3Xm83cUNb8lvH8svFN wnVhzD8ZuDbXpHAQHOdfQx2iy+OAzKAk9TlgU1C4fDuOIX5GqStHFVgK13kpTwRSA4HF oOD41KqxaxAqv35ivy67YNdrc5flVh4LUX0gxaGWo5sX98J/IJCh7URPX89lpa/BYU6U 3OjLZ0njB2jccG3Hvaee1a9fkg+NQbxy/kNH0aBqKaJ/lD/9twMGEiU7UIncezIF+Qqa nKLw== X-Forwarded-Encrypted: i=1; AJvYcCVr/gVRRYIbLcfbGJAlbNawsGqlmHX6fna6EZlvqZ1j+yOfGOYBDjRCn+lm7tie98k+QUDjrUrnOKdJ@nongnu.org X-Gm-Message-State: AOJu0Yxisq4w/Pr4FZGQwX/E4N07EYjRZj00J4mQUJqCKfB2HUtJu69o VS0AUiFRAgN6UHDJrJAC3JBc69KwmmCWfLF+hjRbOhFKFbz5Gwbbqru6CiulX28ZIJY= X-Gm-Gg: ATEYQzzDh5FkIavangXwGOwESl5jnAAkB7RL9CMrq0ff453R07jFlNZeRnnYmRJxmcb Sx4tJvWOA/ECDkYtHUbhoJ+N0MvIDFDhIBR5ik6wJoW03rbhkGbawcF5S9oY1M6cG39vdvcNO9Q 5OayqfUdyLVJ45JJ7eqn/yHQKuaaS7nXnIeTBfjM3Z87EggUsqZnsBrUVF2oH7HbyF6LPaA+Tl9 SGhvkR7Rpd8qI7hgWCdQu0Y8T5uDtw/eQRgUpSETgWa7kr88OISRqtCMP6hTjYCFe7CV5egrgfD 47VgDt576IYL12quLEUw6PN1n+5hSrVRby5jVD6Tzqi6ol6IgvNXo66L4QB8e2Hv20iXgRvd1Fz Q3GBNsUia2EEoVziKsNI0/r5bGGql/0xxdAQxCvJwIk+KMdiRaY3t+T1B3zdTbvftJyTdlc3tBG jB/FawV+KYAxmN1KOGT44MxSKcR6GiygtRzxgbEB6547ag2+mDslxEbrg/mPGu6Poi9q+a0xe9p W/YFCeGyXatl8cmxOnCpvY3DnDTrNA= X-Received: by 2002:a05:6000:22c8:b0:43b:4966:744a with SMTP id ffacd0b85a97d-43b9ea77b34mr3305556f8f.50.1774610265741; Fri, 27 Mar 2026 04:17:45 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 46/65] target/arm: GICv5 cpuif: Implement ICC_HPPIR_EL1 Date: Fri, 27 Mar 2026 11:16:41 +0000 Message-ID: <20260327111700.795099-47-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610414295154100 Content-Type: text/plain; charset="utf-8" Implement ICC_HPPIR_EL1, which the guest can use to read the current highest priority pending interrupt. Like APR, PCR and CR0, this is banked, with the _EL1 register reading the answer for the current logical interrupt domain, and the _EL3 register reading the answer for the EL3 interrupt domain. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5.c | 10 +++++ include/hw/intc/arm_gicv5_stream.h | 13 +++++++ target/arm/tcg/gicv5-cpuif.c | 61 ++++++++++++++++++++++++++++++ 3 files changed, 84 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 12cbf9c51e..605cf6fd6f 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -527,6 +527,16 @@ static void irs_recall_hppis(GICv5 *s, GICv5Domain dom= ain) } } =20 +GICv5PendingIrq gicv5_get_hppi(GICv5Common *cs, GICv5Domain domain, + uint32_t iaffid) +{ + GICv5 *s =3D ARM_GICV5(cs); + int cpuidx =3D irs_cpuidx_from_iaffid(cs, iaffid); + + assert(cpuidx >=3D 0); + return s->hppi[domain][cpuidx]; +} + static hwaddr l1_iste_addr(GICv5Common *cs, const GICv5ISTConfig *cfg, uint32_t id) { diff --git a/include/hw/intc/arm_gicv5_stream.h b/include/hw/intc/arm_gicv5= _stream.h index 60c470b84c..cc1c7cc438 100644 --- a/include/hw/intc/arm_gicv5_stream.h +++ b/include/hw/intc/arm_gicv5_stream.h @@ -175,4 +175,17 @@ uint64_t gicv5_request_config(GICv5Common *cs, uint32_= t id, GICv5Domain domain, */ void gicv5_forward_interrupt(ARMCPU *cpu, GICv5Domain domain); =20 +/** + * gicv5_get_hppi + * @cs: GIC IRS to query + * @domain: interrupt domain to act on + * @iaffid: IAFFID of this CPU interface + * + * Ask the IRS for the highest priority pending interrupt that it has + * for this CPU. This returns the equivalent of what in the stream + * protocol is the outstanding interrupt sent with a Forward packet. + */ +GICv5PendingIrq gicv5_get_hppi(GICv5Common *cs, GICv5Domain domain, + uint32_t iaffid); + #endif diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index b44b0d5398..36bbb70c4a 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -51,6 +51,10 @@ FIELD(ICC_CR0, PID, 38, 1) =20 FIELD(ICC_PCR, PRIORITY, 0, 5) =20 +FIELD(ICC_HPPIR_EL1, ID, 0, 24) +FIELD(ICC_HPPIR_EL1, TYPE, 29, 3) +FIELD(ICC_HPPIR_EL1, HPPIV, 32, 1) + /* * We implement 24 bits of interrupt ID, the mandated 5 bits of priority, * and no legacy GICv3.3 vcpu interface (yet) @@ -114,6 +118,51 @@ static uint64_t gic_running_prio(CPUARMState *env, GIC= v5Domain domain) return hap < 32 ? hap : PRIO_IDLE; } =20 +static GICv5PendingIrq gic_hppi(CPUARMState *env, GICv5Domain domain) +{ + /* + * Return the current highest priority pending interrupt for the + * specified domain, if it has sufficient priority to preempt. The + * intid field of the return value will be in the format of the + * ICC_HPPIR register (and will be zero if and only if there is no + * interrupt that can preempt). + */ + + GICv5Common *gic =3D gicv5_get_gic(env); + GICv5PendingIrq best, irs_hppi; + + if (!(env->gicv5_cpuif.icc_cr0[domain] & R_ICC_CR0_EN_MASK)) { + /* If cpuif is disabled there is no HPPI */ + return (GICv5PendingIrq) { .intid =3D 0, .prio =3D PRIO_IDLE }; + } + + irs_hppi =3D gicv5_get_hppi(gic, domain, env->gicv5_iaffid); + + /* + * If the best PPI and the best interrupt from the IRS have the + * same priority, it's IMPDEF which we pick (R_VVBPS). We choose + * the PPI. + */ + if (env->gicv5_cpuif.ppi_hppi[domain].prio <=3D irs_hppi.prio) { + best =3D env->gicv5_cpuif.ppi_hppi[domain]; + } else { + best =3D irs_hppi; + } + + /* + * D_MSQKF: an interrupt has sufficient priority if its priority + * is higher than the current running priority and equal to or + * higher than the priority mask. + */ + if (best.prio =3D=3D PRIO_IDLE || + best.prio > env->gicv5_cpuif.icc_pcr[domain] || + best.prio >=3D gic_running_prio(env, domain)) { + return (GICv5PendingIrq) { .intid =3D 0, .prio =3D PRIO_IDLE }; + } + best.intid |=3D R_ICC_HPPIR_EL1_HPPIV_MASK; + return best; +} + static void gic_recalc_ppi_hppi(CPUARMState *env) { /* @@ -407,6 +456,13 @@ static void gic_icc_pcr_el1_reset(CPUARMState *env, co= nst ARMCPRegInfo *ri) } } =20 +static uint64_t gic_icc_hppir_el1_read(CPUARMState *env, const ARMCPRegInf= o *ri) +{ + GICv5Domain domain =3D gicv5_logical_domain(env); + GICv5PendingIrq hppi =3D gic_hppi(env, domain); + return hppi.intid; +} + static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { /* * Barrier: wait until the effects of a cpuif system register @@ -522,6 +578,11 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_hm[1]), .resetvalue =3D PPI_HMR1_RESET, }, + { .name =3D "ICC_HPPIR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 10, .opc2 =3D 3, + .access =3D PL1_R, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .readfn =3D gic_icc_hppir_el1_read, + }, { .name =3D "ICC_PPI_ENABLER0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 10, .opc2 =3D 6, .access =3D PL1_RW, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610501; cv=none; d=zohomail.com; s=zohoarc; b=TMKjti2qAST4zVFD1el0o3ys67KTTZD/LSZzyI1IW7Q4v9a50K7zkp1s89joxv6OYzOt0citVMBdhD8v8Q5mxWfuCMCLz8oX8Pe8C8bdmu7+z1nPCuQzXvOWWoKZnjEjfKjCKnG7hiWivf+Qv1pU7x3hkuhKNd6psI0v+QWr22E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610501; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=S+NND+DC3ZaHttRrG8gV6nmrowvOqHZWCsPNgUWAPHg=; b=UXlTYTO/qoFmVR57Tt167i8c4xdn5VK6EfROzfvs+hOKtl6rqL4LBjbiLCl4IOZwHIQhWVrfOV1mCth5UGm7lwUx24Dd8jqkK9UzsxOxLxop/cGQ6g5exYkub8936ofBSkkTD55HWkpUaTssnqzapXUee0tfpCsG6zUxPy1srxI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610501516452.6188433945739; Fri, 27 Mar 2026 04:21:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65Cb-0007nY-E8; Fri, 27 Mar 2026 07:18:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65CI-00076v-Rp for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:51 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65CG-0008Nc-7q for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:50 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-43b95e5b3afso1067303f8f.3 for ; Fri, 27 Mar 2026 04:17:47 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610267; x=1775215067; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=S+NND+DC3ZaHttRrG8gV6nmrowvOqHZWCsPNgUWAPHg=; b=IQT3bag1kNwaqchKmpNUPhjQ6ymAqdcSw0PXJkfBOBu1TvYIc2dfNXFDaFjuznCpWp Z54CBCGey0omDvkgtSLzC1DIgptbtQbsvnTPdDcL31oOakt90iVCwscRLyzWkhLRm1RQ 2Y6kfc0UqGtb5wG1kHOt/UYiPPRPna9P8vbuivM+MfMVSP9tx+G1s70F8ohP4FJh33u8 voYeVean2WhohpzHgCzh2AFvFAz5oT3C6fqXCDcl2F6v8anEN6XWt2IqtqCHrI949HNZ /zfPRUegFy++pRqNL7kQthPXOPsoHJICMlH79ku0nXV3j0N3j9NfgidzjE5PGzANC9ju wwwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610267; x=1775215067; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=S+NND+DC3ZaHttRrG8gV6nmrowvOqHZWCsPNgUWAPHg=; b=Zu5MWv1AsI4BbqpRqnUviSZXU5uR/JIJT59Lj5ZgyD310khjRd2Q3QmBQrtrD1D+Ir UsaI0sQfJnqa1R0YFcGVxMJry16Q/Ew9S5mytn5t4+yVNnaoCKanEFAZ1DiZLRc9hpaq SN9MjOsfV8XMbKT3w3qjurLoD4O5g2yGZIUUaKn1bDJ35xkpF0IRd1Dr/uENDpi6KKag sNVx5qKq7hHTSVQb0ZexK4dGtQrlOFEftyF4o4THR9t7f6z03+CG4OgtY0UhD2gbVWUi ECNNHPtl0nMMF1ZDuHBRkN/lLCeLSxF/9WyAkZRZKOHM6tzRRU1sC+Eaf9aU/AL1dAdz qnAQ== X-Forwarded-Encrypted: i=1; AJvYcCVyrkYqj6zZrJ5owhz0DbagqR8LLPEyXN7b51TxYmtmulfgCEoImQRXAK4gNoxi8hWRMgamHw+e3v84@nongnu.org X-Gm-Message-State: AOJu0YwTi56koP6j6216805oPj7xfOTkU1GbXm36dkIpAdKlCNPXmybH ugnsueJcz0KcQoenhvdrloaYXR1CKVXA4f5htl4qEDEfdYsB+YKqm8O1x/2JzTO8wLk= X-Gm-Gg: ATEYQzzFFhiRk0EVuLBlhGVOeoVZsa2bZVrpXyFyUXRysbuWIV6j/Rnk0h8ibGoHTNv qbm0xnt+8nBwVh3UUH19xUzp6NliAq5XNZwg4lehZLv7awaLLWEp3FEuwOTnvsuAhpNEokVuMhU teMf+qSsbZPNEutJqIrR1sUBAlELZP6SWdjKs8tgTBUiZdxI8B2AD3UjJor+YTCfdAHLqTSN6JZ JRwOME+ExhMuwyV1SlYq1a8+/yjharXyxpCj4vEux8CQqnL6jogzISz7mKgLMIIu6EoQEe7FIlo rdh3ih7WZ2nEB3nD+pz1Q2B9b4JLQZ1JA/GHAEoIUXaEWer4Q5XjqOppRUTQn5DLND6PZAdIvi7 WMvC3+hX7aPLgQ8hGU/aBY9xUr1YZmyM8T5XFNjgDFlkBoTSgSWSMWVqCXbkZ1A/rthN+Ut86Az 99v8wyTZjDcfyfbY362pFzw8HP1jgUEu+HihX5tGDBjhtVrPVJZcVHcbnvjR9Oq5Qju+c9XZf5I J1M0ylVFHjH3bJ+2SvzG+7AaHLFa4s= X-Received: by 2002:a05:6000:1448:b0:43b:4f0c:aefd with SMTP id ffacd0b85a97d-43b9e9a0c82mr2934674f8f.23.1774610266525; Fri, 27 Mar 2026 04:17:46 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 47/65] hw/intc/arm_gicv5: Implement Activate command Date: Fri, 27 Mar 2026 11:16:42 +0000 Message-ID: <20260327111700.795099-48-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610504088154100 Content-Type: text/plain; charset="utf-8" Implement the equivalent of the GICv5 stream protocol's Activate command, which lets the cpuif tell the IRS to move its current highest priority pending interrupt into the Active state, and to clear the Pending state for an Edge handling mode interrupt. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5.c | 58 ++++++++++++++++++++++++++++++ hw/intc/trace-events | 1 + include/hw/intc/arm_gicv5_stream.h | 23 ++++++++++++ 3 files changed, 82 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 605cf6fd6f..942f3eba2e 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -1095,6 +1095,64 @@ uint64_t gicv5_request_config(GICv5Common *cs, uint3= 2_t id, GICv5Domain domain, } } =20 +void gicv5_activate(GICv5Common *cs, uint32_t id, GICv5Domain domain, + GICv5IntType type, bool virtual) +{ + GICv5 *s =3D ARM_GICV5(cs); + uint32_t iaffid; + + trace_gicv5_activate(domain_name[domain], inttype_name(type), virtual,= id); + + if (virtual) { + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_activate: tried to " + "activate a virtual interrupt\n"); + return; + } + + switch (type) { + case GICV5_LPI: + { + const GICv5ISTConfig *cfg =3D &s->phys_lpi_config[domain]; + L2_ISTE_Handle h; + uint32_t *l2_iste_p =3D get_l2_iste(cs, cfg, id, &h); + + if (!l2_iste_p) { + return; + } + *l2_iste_p =3D FIELD_DP32(*l2_iste_p, L2_ISTE, ACTIVE, true); + if (FIELD_EX32(*l2_iste_p, L2_ISTE, HM) =3D=3D GICV5_EDGE) { + *l2_iste_p =3D FIELD_DP32(*l2_iste_p, L2_ISTE, PENDING, false); + } + iaffid =3D FIELD_EX32(*l2_iste_p, L2_ISTE, IAFFID); + put_l2_iste(cs, cfg, &h); + break; + } + case GICV5_SPI: + { + GICv5SPIState *spi =3D gicv5_spi_state(cs, id, domain); + + if (!spi) { + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_activate: tried to " + "activate unreachable SPI %d\n", id); + return; + } + + spi->active =3D true; + if (spi->hm =3D=3D GICV5_EDGE) { + spi->pending =3D false; + } + iaffid =3D spi->iaffid; + break; + } + default: + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_activate: tried to " + "activate bad interrupt type %d\n", type); + return; + } + + irs_recalc_hppi(s, domain, iaffid); +} + static void irs_map_l2_istr_write(GICv5 *s, GICv5Domain domain, uint64_t v= alue) { GICv5Common *cs =3D ARM_GICV5_COMMON(s); diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 6475ba5959..636c598970 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -241,6 +241,7 @@ gicv5_set_pending(const char *domain, const char *type,= bool virtual, uint32_t i gicv5_set_handling(const char *domain, const char *type, bool virtual, uin= t32_t id, int handling) "GICv5 IRS SetHandling %s %s virtual:%d ID %u handl= ing %d" gicv5_set_target(const char *domain, const char *type, bool virtual, uint3= 2_t id, uint32_t iaffid, int irm) "GICv5 IRS SetTarget %s %s virtual:%d ID = %u IAFFID %u routingmode %d" gicv5_request_config(const char *domain, const char *type, bool virtual, u= int32_t id, uint64_t icsr) "GICv5 IRS RequestConfig %s %s virtual:%d ID %u = ICSR 0x%" PRIx64 +gicv5_activate(const char *domain, const char *type, bool virtual, uint32_= t id) "GICv5 IRS Activate %s %s virtual:%d ID %u" gicv5_spi_state(uint32_t spi_id, bool level, bool pending, bool active) "G= ICv5 IRS SPI ID %u now level %d pending %d active %d" gicv5_irs_recalc_hppi_fail(const char *domain, uint32_t iaffid, const char= *reason) "GICv5 IRS %s IAFFID %u: no HPPI: %s" gicv5_irs_recalc_hppi(const char *domain, uint32_t iaffid, uint32_t id, ui= nt8_t prio) "GICv5 IRS %s IAFFID %u: new HPPI ID 0x%x prio %u" diff --git a/include/hw/intc/arm_gicv5_stream.h b/include/hw/intc/arm_gicv5= _stream.h index cc1c7cc438..7ac24f0f09 100644 --- a/include/hw/intc/arm_gicv5_stream.h +++ b/include/hw/intc/arm_gicv5_stream.h @@ -151,6 +151,29 @@ void gicv5_set_target(GICv5Common *cs, uint32_t id, ui= nt32_t iaffid, uint64_t gicv5_request_config(GICv5Common *cs, uint32_t id, GICv5Domain do= main, GICv5IntType type, bool virtual); =20 +/** + * gicv5_activate + * @cs: GIC IRS to send command to + * @id: interrupt ID + * @domain: interrupt domain to act on + * @type: interrupt type (LPI or SPI) + * @virtual: true if this is a virtual interrupt + * + * Activate the IRS's highest priority pending interrupt; matches the + * stream interface's Activate command. + * + * In the stream interface, the command has only the domain and + * virtual fields, because both the IRS and the CPUIF keep track of + * the IRS's current HPPI. In QEMU, we also have arguments here for + * @id and @type which are telling the IRS something that in hardware + * it already knows. This is because we have them to hand in the cpuif + * code, and it means we don't need to pass in an iaffid argument to + * tell the IRS which CPU we are so it can find the right element in + * its hppi[][] array. + */ +void gicv5_activate(GICv5Common *cs, uint32_t id, GICv5Domain domain, + GICv5IntType type, bool virtual); + /** * gicv5_forward_interrupt * @cpu: CPU interface to forward interrupt to --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610411; cv=none; d=zohomail.com; s=zohoarc; b=facf5RSDnBbFDDTB/jXWOBX0XRCD/Tu0qDtkIdUVT4/vm6LjrGBJeoCXASx5g8tLZZGMFeG4evaHuV8Xd1L2M74iQsQZ0/UUR5v+xBIKOROzaEVD9SyG8Z75F4e9ImJF+wK1DnvxGDDAbWf0ta4xz0jWXo8VJONSvk2FF1wfIpg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610411; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=nYwEiR5/cYmqAxk5dlNZzaCEtoWpF8rqG2y/FpqcXSc=; b=GAH6DvCBSDYckb1stcMezu83KYReRmFatzEuaIpqd79eSE1BptpASBoHE314pxmmYpQzBlLYbxFdZXNRPI06bgbF+45OCPTE7XK7UcX9vQCIgeFSA0boC/4CTEza1H19vxnExQKscerh7VTjjT0UcdZ+z+HeXjicdc708fRoMIs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610411414417.71623500683086; Fri, 27 Mar 2026 04:20:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65CZ-0007cC-Qv; Fri, 27 Mar 2026 07:18:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65CJ-00076y-Mk for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:51 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65CH-0008OQ-Az for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:51 -0400 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-43b40003d13so1406564f8f.2 for ; Fri, 27 Mar 2026 04:17:48 -0700 (PDT) Received: from lanath.. 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It returns a value corresponding to the HPPI for the current physical interrupt domain, if any, and moves that interrupt to being Active. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- target/arm/tcg/gicv5-cpuif.c | 101 +++++++++++++++++++++++++++++++++++ target/arm/tcg/trace-events | 2 + 2 files changed, 103 insertions(+) diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 36bbb70c4a..09870e0b09 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -39,6 +39,10 @@ FIELD(GIC_CDHM, HM, 32, 1) FIELD(GIC_CDRCFG, ID, 0, 24) FIELD(GIC_CDRCFG, TYPE, 29, 3) =20 +FIELD(GICR_CDIA, ID, 0, 24) +FIELD(GICR_CDIA, TYPE, 29, 3) +FIELD(GICR_CDIA, VALID, 32, 1) + FIELD(ICC_IDR0_EL1, ID_BITS, 0, 4) FIELD(ICC_IDR0_EL1, PRI_BITS, 4, 4) FIELD(ICC_IDR0_EL1, GCIE_LEGACY, 8, 4) @@ -463,6 +467,93 @@ static uint64_t gic_icc_hppir_el1_read(CPUARMState *en= v, const ARMCPRegInfo *ri) return hppi.intid; } =20 +static bool gic_hppi_is_nmi(CPUARMState *env, GICv5PendingIrq hppi, + GICv5Domain domain) +{ + /* + * For GICv5 an interrupt is an NMI if it is signaled with + * Superpriority and SCTLR_ELx.NMI for the current EL is 1. GICR + * CDIA/CDNMIA always work on the current interrupt domain, so we + * do not need to consider preemptive interrupts. This means that + * the interrupt has Superpriority if and only if it has priority 0. + */ + return hppi.prio =3D=3D 0 && arm_sctlr(env, arm_current_el(env)) & SCT= LR_NMI; +} + +static uint64_t gicr_cdia_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* Acknowledge HPPI in the current interrupt domain */ + GICv5Common *gic =3D gicv5_get_gic(env); + GICv5Domain domain =3D gicv5_current_phys_domain(env); + GICv5PendingIrq hppi =3D gic_hppi(env, domain); + GICv5IntType type =3D FIELD_EX64(hppi.intid, INTID, TYPE); + uint32_t id =3D FIELD_EX64(hppi.intid, INTID, ID); + + bool cdnmia =3D ri->opc2 =3D=3D 1; + + if (!hppi.intid) { + /* No interrupt available to acknowledge */ + trace_gicv5_gicr_cdia_fail(domain, + "no available interrupt to acknowledge"= ); + return 0; + } + assert(hppi.prio !=3D PRIO_IDLE); + + if (gic_hppi_is_nmi(env, hppi, domain) !=3D cdnmia) { + /* GICR CDIA only acknowledges non-NMI; GICR CDNMIA only NMI */ + trace_gicv5_gicr_cdia_fail(domain, + cdnmia ? "CDNMIA but HPPI is not NMI" : + "CDIA but HPPI is NMI"); + return 0; + } + + trace_gicv5_gicr_cdia(domain, hppi.intid); + + /* + * The interrupt becomes Active. If the handling mode of the + * interrupt is Edge then we also clear the pending state. + */ + + /* + * Set the appropriate bit in the APR to track active priorities. + * We do this now so that when gic_recalc_ppi_hppi() or + * gicv5_activate() cause a re-evaluation of HPPIs they use the + * right (new) running priority. + */ + env->gicv5_cpuif.icc_apr[domain] |=3D (1 << hppi.prio); + switch (type) { + case GICV5_PPI: + { + uint32_t ppireg, ppibit; + + assert(id < GICV5_NUM_PPIS); + ppireg =3D id / 64; + ppibit =3D 1 << (id % 64); + + env->gicv5_cpuif.ppi_active[ppireg] |=3D ppibit; + if (!(env->gicv5_cpuif.ppi_hm[ppireg] & ppibit)) { + /* handling mode is Edge: clear pending */ + env->gicv5_cpuif.ppi_pend[ppireg] &=3D ~ppibit; + } + gic_recalc_ppi_hppi(env); + break; + } + case GICV5_LPI: + case GICV5_SPI: + /* + * Send an Activate command to the IRS, which, despite the + * name of the stream command, does both "set Active" and + * "maybe set not Pending" as a single atomic action. + */ + gicv5_activate(gic, id, domain, type, false); + break; + default: + g_assert_not_reached(); + } + + return hppi.intid | R_GICR_CDIA_VALID_MASK; +} + static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { /* * Barrier: wait until the effects of a cpuif system register @@ -520,6 +611,16 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, .writefn =3D gic_cdhm_write, }, + { .name =3D "GICR_CDIA", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 3, .opc2 =3D 0, + .access =3D PL1_R, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .readfn =3D gicr_cdia_read, + }, + { .name =3D "GICR_CDNMIA", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 3, .opc2 =3D 1, + .access =3D PL1_R, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .readfn =3D gicr_cdia_read, + }, { .name =3D "ICC_IDR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 10, .opc2 =3D 2, .access =3D PL1_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, diff --git a/target/arm/tcg/trace-events b/target/arm/tcg/trace-events index 7dc5f781c5..13e15cfcfc 100644 --- a/target/arm/tcg/trace-events +++ b/target/arm/tcg/trace-events @@ -3,3 +3,5 @@ =20 # gicv5-cpuif.c gicv5_recalc_ppi_hppi(int domain, uint32_t id, uint8_t prio) "domain %d ne= w PPI HPPI id 0x%x prio %u" +gicv5_gicr_cdia_fail(int domain, const char *reason) "domain %d CDIA attem= pt failed: %s" +gicv5_gicr_cdia(int domain, uint32_t id) "domain %d CDIA acknowledge of in= terrupt 0x%x" --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610808; cv=none; d=zohomail.com; s=zohoarc; b=BMkyRTNeI6gVHpsGLqMT23TH+X4d/32pbgZh61q/albFAuDCp0e5Z8EzPzOc15shMUn8/P7t61NJW5nDM5XZe6Dui4bpYhkyuZ0GDBrBiDhOPkipziI5nygS4764mPef14g9psvDGJAgPwyqFYdcac2RnEPSNPpa65GeVDgUdqo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610808; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=UaZgT662lqVLo8fysFL+JEr5ubuoSNMh8uSkamaRExg=; b=g1CaKjWeRkoLuoXkKQEEB281LmeoMg9jncBhlbdX5WwixMVKrzVnxQHc5XjpivKIrtZPMt7KhQmSwR79IJ8qoUFlJBCTgo3l8WoC+uzXlez3kLPn53GuOyXJrcHqLgbpRgEB6Ywqce54+RAHQMQBXTVNkoLLfXtWl6Tzh0p0/dU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610808638305.9211333207189; Fri, 27 Mar 2026 04:26:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65CV-0007SB-L2; Fri, 27 Mar 2026 07:18:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65CJ-00077B-PK for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:51 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65CI-0008Ph-33 for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:51 -0400 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-43b5bded412so1432698f8f.0 for ; Fri, 27 Mar 2026 04:17:49 -0700 (PDT) Received: from lanath.. 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Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- target/arm/tcg/gicv5-cpuif.c | 21 +++++++++++++++++++++ target/arm/tcg/trace-events | 1 + 2 files changed, 22 insertions(+) diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 09870e0b09..0974637c92 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -554,6 +554,22 @@ static uint64_t gicr_cdia_read(CPUARMState *env, const= ARMCPRegInfo *ri) return hppi.intid | R_GICR_CDIA_VALID_MASK; } =20 +static void gic_cdeoi_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Perform Priority Drop in the current interrupt domain. + * This is just clearing the lowest set bit in the APR. + */ + GICv5Domain domain =3D gicv5_current_phys_domain(env); + uint64_t *apr =3D &env->gicv5_cpuif.icc_apr[domain]; + + trace_gicv5_cdeoi(domain); + + /* clear lowest bit, doing nothing if already zero */ + *apr &=3D *apr - 1; +} + static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { /* * Barrier: wait until the effects of a cpuif system register @@ -606,6 +622,11 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, .writefn =3D gic_cdrcfg_write, }, + { .name =3D "GIC_CDEOI", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 7, + .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .writefn =3D gic_cdeoi_write, + }, { .name =3D "GIC_CDHM", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 2, .opc2 =3D 1, .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, diff --git a/target/arm/tcg/trace-events b/target/arm/tcg/trace-events index 13e15cfcfc..fcb3106a96 100644 --- a/target/arm/tcg/trace-events +++ b/target/arm/tcg/trace-events @@ -5,3 +5,4 @@ gicv5_recalc_ppi_hppi(int domain, uint32_t id, uint8_t prio) "domain %d ne= w PPI HPPI id 0x%x prio %u" gicv5_gicr_cdia_fail(int domain, const char *reason) "domain %d CDIA attem= pt failed: %s" gicv5_gicr_cdia(int domain, uint32_t id) "domain %d CDIA acknowledge of in= terrupt 0x%x" +gicv5_cdeoi(int domain) "domain %d CDEOI performing priority drop" --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610645; cv=none; d=zohomail.com; s=zohoarc; b=Tujcdh1Lp3wQ6/zP+dCLDbZjKOkOi923mir5CQY8W57G4UDFG1TtTwkIPA9LU4K4aAoq6vYuM+nCIRMLRGhTjIkRbufDzDfXimyhTLSnwXSwrYjH6tuuBJh3ph+t/qlEYxHFouvgC7K0w111PkYEe/dFMRgpznkE3Jj967K3WAw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610645; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=JG5oo7kntdhv/cYWN2Y9FsfLDawmXg1ppysqyGtbv/k=; b=DFJhTDoC7bcrvgVenwLmJApWEGS5dYo3ohpqvhIDaYK1ttMY19ysFejewF97W8AJeFmiMh4P83axijCtGIG4WT9x0RdrgjVf5BG7vRFo58f/hEeQFQGR0wFpg5Mrx2qWR7tDihaCA4NEpA2H4NlAI/J7mRwz07ZHwB+jwLTH1Os= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610645832548.6342856820286; Fri, 27 Mar 2026 04:24:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65Dg-0000mP-TP; Fri, 27 Mar 2026 07:19:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65CL-0007DA-OX for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:55 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65CI-0008QT-VC for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:52 -0400 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-43b87970468so1944859f8f.3 for ; Fri, 27 Mar 2026 04:17:50 -0700 (PDT) Received: from lanath.. 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Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5.c | 52 ++++++++++++++++++++++++++++++ hw/intc/trace-events | 1 + include/hw/intc/arm_gicv5_stream.h | 14 ++++++++ 3 files changed, 67 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 942f3eba2e..493d664625 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -1153,6 +1153,58 @@ void gicv5_activate(GICv5Common *cs, uint32_t id, GI= Cv5Domain domain, irs_recalc_hppi(s, domain, iaffid); } =20 +void gicv5_deactivate(GICv5Common *cs, uint32_t id, GICv5Domain domain, + GICv5IntType type, bool virtual) +{ + GICv5 *s =3D ARM_GICV5(cs); + uint32_t iaffid; + + trace_gicv5_deactivate(domain_name[domain], inttype_name(type), virtua= l, id); + + if (virtual) { + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_deactivate: tried to " + "deactivate a virtual interrupt\n"); + return; + } + + switch (type) { + case GICV5_LPI: + { + const GICv5ISTConfig *cfg =3D &s->phys_lpi_config[domain]; + L2_ISTE_Handle h; + uint32_t *l2_iste_p =3D get_l2_iste(cs, cfg, id, &h); + + if (!l2_iste_p) { + return; + } + *l2_iste_p =3D FIELD_DP32(*l2_iste_p, L2_ISTE, ACTIVE, false); + iaffid =3D FIELD_EX32(*l2_iste_p, L2_ISTE, IAFFID); + put_l2_iste(cs, cfg, &h); + break; + } + case GICV5_SPI: + { + GICv5SPIState *spi =3D gicv5_spi_state(cs, id, domain); + + if (!spi) { + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_deactivate: tried to " + "deactivate unreachable SPI %d\n", id); + return; + } + + spi->active =3D false; + iaffid =3D spi->iaffid; + break; + } + default: + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_deactivate: tried to " + "deactivate bad interrupt type %d\n", type); + return; + } + + irs_recalc_hppi(s, domain, iaffid); +} + static void irs_map_l2_istr_write(GICv5 *s, GICv5Domain domain, uint64_t v= alue) { GICv5Common *cs =3D ARM_GICV5_COMMON(s); diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 636c598970..c6696f0e0a 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -242,6 +242,7 @@ gicv5_set_handling(const char *domain, const char *type= , bool virtual, uint32_t gicv5_set_target(const char *domain, const char *type, bool virtual, uint3= 2_t id, uint32_t iaffid, int irm) "GICv5 IRS SetTarget %s %s virtual:%d ID = %u IAFFID %u routingmode %d" gicv5_request_config(const char *domain, const char *type, bool virtual, u= int32_t id, uint64_t icsr) "GICv5 IRS RequestConfig %s %s virtual:%d ID %u = ICSR 0x%" PRIx64 gicv5_activate(const char *domain, const char *type, bool virtual, uint32_= t id) "GICv5 IRS Activate %s %s virtual:%d ID %u" +gicv5_deactivate(const char *domain, const char *type, bool virtual, uint3= 2_t id) "GICv5 IRS Deactivate %s %s virtual:%d ID %u" gicv5_spi_state(uint32_t spi_id, bool level, bool pending, bool active) "G= ICv5 IRS SPI ID %u now level %d pending %d active %d" gicv5_irs_recalc_hppi_fail(const char *domain, uint32_t iaffid, const char= *reason) "GICv5 IRS %s IAFFID %u: no HPPI: %s" gicv5_irs_recalc_hppi(const char *domain, uint32_t iaffid, uint32_t id, ui= nt8_t prio) "GICv5 IRS %s IAFFID %u: new HPPI ID 0x%x prio %u" diff --git a/include/hw/intc/arm_gicv5_stream.h b/include/hw/intc/arm_gicv5= _stream.h index 7ac24f0f09..3cc9f61155 100644 --- a/include/hw/intc/arm_gicv5_stream.h +++ b/include/hw/intc/arm_gicv5_stream.h @@ -211,4 +211,18 @@ void gicv5_forward_interrupt(ARMCPU *cpu, GICv5Domain = domain); GICv5PendingIrq gicv5_get_hppi(GICv5Common *cs, GICv5Domain domain, uint32_t iaffid); =20 +/** + * gicv5_deactivate + * @cs: GIC IRS to send command to + * @id: interrupt ID + * @domain: interrupt Domain to act on + * @type: interrupt type (LPI or SPI) + * @virtual: true if this is a virtual interrupt + * + * Deactivate the specified interrupt. There is no report back of + * success/failure to the CPUIF in the protocol. + */ +void gicv5_deactivate(GICv5Common *cs, uint32_t id, GICv5Domain domain, + GICv5IntType type, bool virtual); + #endif --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610503; cv=none; d=zohomail.com; s=zohoarc; b=H3fbSEZDe76OHPiJ4t4qgsrLARvhYBjs2/mSOy5wvuADDygj671zygvh+3/NPb1BdjB8X4ndduKVQmRopvaT3X2wfXIg6S6PsW+6FYHB/Pp/DlZGYld1mnCTxGSECy0PAONndQGslXSc4o1ZcC2IXAQtEjWRzlwQkLtF7NLyomw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610503; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2JOiLlKzr2TVNV+HAOZ57k8l0kQLTn+WAmtWxV5Vt4w=; b=Vrk2a7vS+FVbmjHvgpTWtXFSwlo4MIiD59n/oYkI12dy4MSwbJTdZTN/BHEkU7zZXIN5FiLgweSlrykNZRqYMyvxOAvDKNgG4v5/7HeuIltp8SIGVZqmGd4OYVDwT31qcGvVGVqqOl2B7kJlcyI6bfST1dK4lxsnkCMMHljg2uE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610503380232.06673674701676; Fri, 27 Mar 2026 04:21:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65D6-0008NW-PD; Fri, 27 Mar 2026 07:18:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65CL-0007D9-Nu for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:55 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65CJ-0008Qr-Rq for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:53 -0400 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-43b88b7ca76so1564198f8f.3 for ; Fri, 27 Mar 2026 04:17:51 -0700 (PDT) Received: from lanath.. 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Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- target/arm/tcg/gicv5-cpuif.c | 49 ++++++++++++++++++++++++++++++++++++ target/arm/tcg/trace-events | 1 + 2 files changed, 50 insertions(+) diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 0974637c92..94590bd765 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -17,6 +17,9 @@ FIELD(GIC_CDPRI, ID, 0, 24) FIELD(GIC_CDPRI, TYPE, 29, 3) FIELD(GIC_CDPRI, PRIORITY, 35, 5) =20 +FIELD(GIC_CDDI, ID, 0, 24) +FIELD(GIC_CDDI, TYPE, 29, 3) + FIELD(GIC_CDDIS, ID, 0, 24) FIELD(GIC_CDDIS, TYPE, 29, 3) =20 @@ -570,6 +573,47 @@ static void gic_cdeoi_write(CPUARMState *env, const AR= MCPRegInfo *ri, *apr &=3D *apr - 1; } =20 +static void gic_cddi_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Clear the Active state of the specified interrupt in the + * current interrupt domain. + */ + GICv5Common *gic =3D gicv5_get_gic(env); + GICv5Domain domain =3D gicv5_current_phys_domain(env); + GICv5IntType type =3D FIELD_EX64(value, GIC_CDDI, TYPE); + uint32_t id =3D FIELD_EX64(value, GIC_CDDI, ID); + bool virtual =3D false; + + trace_gicv5_cddi(domain, value); + + switch (type) { + case GICV5_PPI: + { + uint32_t ppireg, ppibit; + + if (id >=3D GICV5_NUM_PPIS) { + break; + } + + ppireg =3D id / 64; + ppibit =3D 1 << (id % 64); + + env->gicv5_cpuif.ppi_active[ppireg] &=3D ~ppibit; + gic_recalc_ppi_hppi(env); + break; + } + case GICV5_LPI: + case GICV5_SPI: + /* Tell the IRS to deactivate this interrupt */ + gicv5_deactivate(gic, id, domain, type, virtual); + break; + default: + break; + } +} + static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { /* * Barrier: wait until the effects of a cpuif system register @@ -627,6 +671,11 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, .writefn =3D gic_cdeoi_write, }, + { .name =3D "GIC_CDDI", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .writefn =3D gic_cddi_write, + }, { .name =3D "GIC_CDHM", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 2, .opc2 =3D 1, .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, diff --git a/target/arm/tcg/trace-events b/target/arm/tcg/trace-events index fcb3106a96..c60ce6834e 100644 --- a/target/arm/tcg/trace-events +++ b/target/arm/tcg/trace-events @@ -6,3 +6,4 @@ gicv5_recalc_ppi_hppi(int domain, uint32_t id, uint8_t prio= ) "domain %d new PPI gicv5_gicr_cdia_fail(int domain, const char *reason) "domain %d CDIA attem= pt failed: %s" gicv5_gicr_cdia(int domain, uint32_t id) "domain %d CDIA acknowledge of in= terrupt 0x%x" gicv5_cdeoi(int domain) "domain %d CDEOI performing priority drop" +gicv5_cddi(int domain, uint32_t id) "domain %d CDDI deactivating interrupt= ID 0x%x" --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610271; x=1775215071; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/538nhOyJvTtKUnWgIA1CYfboj+HJJDD3GUusHPw/0c=; b=NVgWrZ40Xdwe/MaVLkujszXmbDt7Y+/4UPFoSQxUViRE2iAytC6jMHcfQU8GMYAdSa 2GqTVvxZvoltPelST+H3Xc13pz5N5T04Rm/Slyl0+lPGUY2XYViAipQhdaCLyFBKOkJ3 iHsnifLsJZhweZPpW2cBciCNxxhZiNG7UxY58o/iSOLeQZ64C/lOnY3d/9dhq7ltkPLj e7dbInzQdMJJM1145ks5p/cmXPfZ7fhlwhsuLqFtbs3ZcfQW8qk8J2m75wMm6wil5RBL SV7OP1QF/VOkLRI4pMNnXVclJpBKtuTBCL8rnKR9oF3XK1nK8KMFT7Jm1CZxvwWvyDAP Zjng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610271; x=1775215071; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=/538nhOyJvTtKUnWgIA1CYfboj+HJJDD3GUusHPw/0c=; b=GFtM4yV+aQ8AZs2ye1+VCaV5A+kjI/FWFE+pDB0p4nyBWK2HD+Bkj9T/JNeGdfGlgb /K6ou7XBsZ8Hjbssm0xd+JHIECRfjnRM2FCVSxMRb+eaFDa7zT/CnlfTfgOvhlQTBNQB 59ah5JKpkFhbP6N6KKKcdrNbQOc1OsCXWtz1C/hdbMrVH49bFrRKJ1INwq6xPZnGdnBo 8VrNtCW95lcoaTv2hk/DBIPRHQIano2d5zpYDb+wnS74bdjQt/FLY4mQdRDzkVL2PtCe 8GTN5qxEQEvShOUstuDWzZd3ZKj2kq+OSeTtqerM13q96O2qCnPfDGfXDP4ZnKDh3GDx Hm+g== X-Forwarded-Encrypted: i=1; AJvYcCWSEAC3xqkWrrWZi1phzotZ2KONzljCYvkndHHpKIsY4xtz2qKqCcnnmMYXMcEzUvuFi2lZJvcG/7M+@nongnu.org X-Gm-Message-State: AOJu0YytVDYFW0uyIOUw2pHpKmOrxIZ2MjtKn4RITb9SAPcDzmZYxKus UmjuzJ2RWpDq98cGbezEMcoAh0eqPf3C//WA+Y4qI9KNWxL2UZL+k2epXb7vtwv6ylE= X-Gm-Gg: ATEYQzwCq6tfN6V9CijzGXYDdXfIpz44I50+j8hEHzrhPlO9W0bn63QOSPXyzD7jG6U rqjnrYRkwwXu41Vs9CBmkQB5JdmtLk2y7zFNR4pWANj+jiQhU9v8DCcSz3S9T62tY+w88KcKyGd PNlB9fsTKWCgClDoDMOWwVxXiOsNtd0v8Xz4KK/4/WxbM333+n5OEL+6vgLxvuN995UNvArEv09 KsmCnLF4AOmNR0dj7XCzVWQ4CzvL7UHcY6bmDxrjZLO7RcADF8Z5skqQIYlWtW7klRkIdjkNcJ0 LPwikpBxK1bfkRW7DSWscLXJZa4UmZqtapBLqyIF4gHGJw1QyZCyrWWeJnwCA3/K7zEk4yzyiyw udwa8yFQ03Bc2tiqOseq7O3plm391xeCicxDOp7/LACfBDnOcSXR1sdhG1LEJ/IxM7w1Lsrp2TF xUV/zXh/+Iogh8FjTyZR+TkMQ6Caj2+2ptY9xY3vdHgYjdytDsRkhbcebipaCrh3gN/3iTv4ULZ RDK+062tXPyU8xT4F+rkJ8h+dFXfao= X-Received: by 2002:a7b:c44f:0:b0:485:5403:7497 with SMTP id 5b1f17b1804b1-48722bed60fmr66821275e9.14.1774610271156; Fri, 27 Mar 2026 04:17:51 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 52/65] target/arm: GICv5 cpuif: Signal IRQ or FIQ Date: Fri, 27 Mar 2026 11:16:47 +0000 Message-ID: <20260327111700.795099-53-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610706188158500 Content-Type: text/plain; charset="utf-8" The CPU interface must signal IRQ or FIQ (possibly with superpriority) when there is a pending interrupt of sufficient priority available. Implement this logic. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- target/arm/tcg/gicv5-cpuif.c | 87 ++++++++++++++++++++++++++++++++++-- target/arm/tcg/trace-events | 1 + 2 files changed, 85 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 94590bd765..7caf2102a9 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -170,6 +170,84 @@ static GICv5PendingIrq gic_hppi(CPUARMState *env, GICv= 5Domain domain) return best; } =20 +static void cpu_interrupt_update(CPUARMState *env, int irqtype, bool new_s= tate) +{ + CPUState *cs =3D env_cpu(env); + + /* + * OPT: calling cpu_interrupt() and cpu_reset_interrupt() has the + * correct behaviour, but is not optimal for the case where we're + * setting the interrupt line to the same level it already has. + * + * Clearing an already clear interrupt is free (it's just doing an + * atomic AND operation). Signalling an already set interrupt is a + * bit less ideal (it might unnecessarily kick the CPU). + * + * We could potentially use cpu_test_interrupt(), like + * arm_cpu_update_{virq,vfiq,vinmi,vserr}, since we always hold + * the BQL here; or perhaps there is an abstraction we could + * provide in the core code that all these places could call. + * + * For now, this is simple and definitely correct. + */ + if (new_state) { + cpu_interrupt(cs, irqtype); + } else { + cpu_reset_interrupt(cs, irqtype); + } +} + +static void gicv5_update_irq_fiq(CPUARMState *env) +{ + /* + * Update whether we are signalling IRQ or FIQ based on the + * current state of the CPU interface (and in particular on the + * HPPI information from the IRS and for the PPIs for each + * interrupt domain); + * + * The logic here for IRQ and FIQ is defined by rules R_QLGBG and + * R_ZGHMN; whether to signal with superpriority is defined by + * rule R_CSBDX. + * + * For the moment, we do not consider preemptive interrupts, + * because these only occur when there is a HPPI of sufficient + * priority for another interrupt domain, and we only support EL1 + * and the NonSecure interrupt domain currently. + * + * NB: when we handle more than just EL1 we will need to arrange + * to call this function to re-evaluate the IRQ and FIQ state when + * we change EL. + */ + GICv5PendingIrq current_hppi; + bool irq, fiq, superpriority; + + /* + * We will never signal FIQ because FIQ is for preemptive + * interrupts or for EL3 HPPIs. + */ + fiq =3D false; + + /* + * We signal IRQ when we are not signalling FIQ and there is a + * HPPI of sufficient priority for the current domain. It has + * Superpriority if its priority is 0 (in which case it is + * CPU_INTERRUPT_NMI rather than CPU_INTERRUPT_HARD). + */ + current_hppi =3D gic_hppi(env, gicv5_current_phys_domain(env)); + superpriority =3D current_hppi.prio =3D=3D 0; + irq =3D current_hppi.prio !=3D PRIO_IDLE && !superpriority; + + /* + * Unlike a GICv3 or GICv2, there is no external IRQ or FIQ line + * to the CPU. Instead we directly signal the interrupt via + * cpu_interrupt()/cpu_reset_interrupt(). + */ + trace_gicv5_update_irq_fiq(irq, fiq, superpriority); + cpu_interrupt_update(env, CPU_INTERRUPT_HARD, irq); + cpu_interrupt_update(env, CPU_INTERRUPT_FIQ, fiq); + cpu_interrupt_update(env, CPU_INTERRUPT_NMI, superpriority); +} + static void gic_recalc_ppi_hppi(CPUARMState *env) { /* @@ -219,15 +297,16 @@ static void gic_recalc_ppi_hppi(CPUARMState *env) env->gicv5_cpuif.ppi_hppi[i].intid, env->gicv5_cpuif.ppi_hppi[i].prio); } + gicv5_update_irq_fiq(env); } =20 void gicv5_forward_interrupt(ARMCPU *cpu, GICv5Domain domain) { /* - * For now, we do nothing. Later we will recalculate the overall - * HPPI by combining the IRS HPPI with the PPI HPPI, and possibly - * signal IRQ/FIQ. + * IRS HPPI has changed: recalculate the IRQ/FIQ levels by + * combining the IRS HPPI with the PPI HPPI. */ + gicv5_update_irq_fiq(&cpu->env); } =20 static void gic_cddis_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -430,6 +509,7 @@ static void gic_icc_cr0_el1_write(CPUARMState *env, con= st ARMCPRegInfo *ri, value |=3D R_ICC_CR0_LINK_MASK | R_ICC_CR0_LINK_IDLE_MASK; =20 env->gicv5_cpuif.icc_cr0[domain] =3D value; + gicv5_update_irq_fiq(env); } =20 static void gic_icc_cr0_el1_reset(CPUARMState *env, const ARMCPRegInfo *ri) @@ -571,6 +651,7 @@ static void gic_cdeoi_write(CPUARMState *env, const ARM= CPRegInfo *ri, =20 /* clear lowest bit, doing nothing if already zero */ *apr &=3D *apr - 1; + gicv5_update_irq_fiq(env); } =20 static void gic_cddi_write(CPUARMState *env, const ARMCPRegInfo *ri, diff --git a/target/arm/tcg/trace-events b/target/arm/tcg/trace-events index c60ce6834e..2bfa8fc552 100644 --- a/target/arm/tcg/trace-events +++ b/target/arm/tcg/trace-events @@ -7,3 +7,4 @@ gicv5_gicr_cdia_fail(int domain, const char *reason) "domai= n %d CDIA attempt fai gicv5_gicr_cdia(int domain, uint32_t id) "domain %d CDIA acknowledge of in= terrupt 0x%x" gicv5_cdeoi(int domain) "domain %d CDEOI performing priority drop" gicv5_cddi(int domain, uint32_t id) "domain %d CDDI deactivating interrupt= ID 0x%x" +gicv5_update_irq_fiq(bool irq, bool fiq, bool nmi) "now IRQ %d FIQ %d NMI = %d" --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610613; cv=none; d=zohomail.com; s=zohoarc; b=AeB78UDZbE4zNIcoV6VH8qI6jDga0vtmXUJ3kIUulkCGIK1hNaqKQbSN93+OM3BLHFh6RvnwRQ/Dg1LGUefTNJy+82+uLMyWXEFXA0d2EyllTOJDnYbWw2A+m6gW9S8NyZgr7JTtbzUU0Ga5wDG10XMipq4NhcwPNKqiSYffVtA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610613; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=vYFn49wK2CtOBKQI7tWyVSTEU2OnE1N9jg68K1dqW5o=; b=k6V15ZSnjPR1h9G/QnnlauC2P06AdRv27I0n0KIf7BKiRNwo86eyT3076YoSBq/30mURyPr9IqQQej0izw6VXPZO3+Hgg0TKIKPopfVYcmBvTvBTW2H8ti3zN7uqsRHZdwUcM89OV5Z0MQKGPZdR6JB+F9Ilax57a1Jenb1R2vk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177461061305597.33997419261766; Fri, 27 Mar 2026 04:23:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65Di-00012B-W8; Fri, 27 Mar 2026 07:19:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65CP-0007G7-JT for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:59 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65CM-0008Td-VL for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:56 -0400 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-43b3d9d0695so1384636f8f.0 for ; Fri, 27 Mar 2026 04:17:53 -0700 (PDT) Received: from lanath.. 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For QEMU, this means the generic timers and the PMU. In GICv3, we implemented these as qemu_irq lines which connect up to the external interrupt controller device. In a GICv5, the PPIs are handled entirely inside the CPU interface, so there are no external signals. Instead we provide a gicv5_update_ppi_state() function which the emulated timer and PMU code uses to tell the CPU interface about the new state of the PPI source. We make the GICv5 function a no-op if there is no GICv5 present, so that calling code can do both "update the old irq lines" and "update the GICv5 PPI" without having to add conditionals. (In a GICv5 system the old irq lines won't be connected to anything, so the qemu_set_irq() will be a no-op.) Updating PPIs via either mechanism is unnecessary in user-only mode; we got away with not ifdeffing this away before because qemu_set_irq() is built for user-only mode, but since the GICv5 cpuif code is system-emulation only, we do need an ifdef now. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- target/arm/cpregs-pmu.c | 9 +++++++-- target/arm/helper.c | 20 ++++++++++++++++++++ target/arm/internals.h | 6 ++++++ target/arm/tcg/gicv5-cpuif.c | 28 ++++++++++++++++++++++++++++ target/arm/tcg/trace-events | 1 + 5 files changed, 62 insertions(+), 2 deletions(-) diff --git a/target/arm/cpregs-pmu.c b/target/arm/cpregs-pmu.c index 47e1e4652b..46df6597b1 100644 --- a/target/arm/cpregs-pmu.c +++ b/target/arm/cpregs-pmu.c @@ -428,9 +428,14 @@ static bool pmu_counter_enabled(CPUARMState *env, uint= 8_t counter) =20 static void pmu_update_irq(CPUARMState *env) { +#ifndef CONFIG_USER_ONLY ARMCPU *cpu =3D env_archcpu(env); - qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && - (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); + bool level =3D (env->cp15.c9_pmcr & PMCRE) && + (env->cp15.c9_pminten & env->cp15.c9_pmovsr); + + gicv5_update_ppi_state(env, GICV5_PPI_PMUIRQ, level); + qemu_set_irq(cpu->pmu_interrupt, level); +#endif } =20 static bool pmccntr_clockdiv_enabled(CPUARMState *env) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8faca360fc..488a91799e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1343,6 +1343,21 @@ uint64_t gt_get_countervalue(CPUARMState *env) return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / gt_cntfrq_period_ns(cpu= ); } =20 +static void gt_update_gicv5_ppi(CPUARMState *env, int timeridx, bool level) +{ + static int timeridx_to_ppi[] =3D { + [GTIMER_PHYS] =3D GICV5_PPI_CNTP, + [GTIMER_VIRT] =3D GICV5_PPI_CNTV, + [GTIMER_HYP] =3D GICV5_PPI_CNTHP, + [GTIMER_SEC] =3D GICV5_PPI_CNTPS, + [GTIMER_HYPVIRT] =3D GICV5_PPI_CNTHV, + [GTIMER_S_EL2_PHYS] =3D GICV5_PPI_CNTHPS, + [GTIMER_S_EL2_VIRT] =3D GICV5_PPI_CNTHVS, + }; + + gicv5_update_ppi_state(env, timeridx_to_ppi[timeridx], level); +} + static void gt_update_irq(ARMCPU *cpu, int timeridx) { CPUARMState *env =3D &cpu->env; @@ -1361,6 +1376,11 @@ static void gt_update_irq(ARMCPU *cpu, int timeridx) irqstate =3D 0; } =20 + /* + * We update both the GICv5 PPI and the external-GIC irq line + * (whichever of the two mechanisms is unused will do nothing) + */ + gt_update_gicv5_ppi(env, timeridx, irqstate); qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); trace_arm_gt_update_irq(timeridx, irqstate); } diff --git a/target/arm/internals.h b/target/arm/internals.h index 9bde58cf00..afe893f49d 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1800,6 +1800,12 @@ void define_gcs_cpregs(ARMCPU *cpu); /* Add the cpreg definitions for the GICv5 CPU interface */ void define_gicv5_cpuif_regs(ARMCPU *cpu); =20 +/* + * Update the state of the given GICv5 PPI for this CPU. Does nothing + * if the GICv5 is not present. + */ +void gicv5_update_ppi_state(CPUARMState *env, int ppi, bool level); + /* Effective value of MDCR_EL2 */ static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env) { diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 7caf2102a9..44b52a4013 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -309,6 +309,34 @@ void gicv5_forward_interrupt(ARMCPU *cpu, GICv5Domain = domain) gicv5_update_irq_fiq(&cpu->env); } =20 +void gicv5_update_ppi_state(CPUARMState *env, int ppi, bool level) +{ + /* + * Update the state of the given PPI (which is connected to some + * CPU-internal source of interrupts, like the timers). We can + * assume that the PPI is fixed as level-triggered, which means + * that its pending state exactly tracks the input (and the guest + * cannot separately change the pending state, because the pending + * bits are RO). + */ + int oldlevel; + + if (!cpu_isar_feature(aa64_gcie, env_archcpu(env))) { + return; + } + + /* The architected PPIs are 0..63, so in the first PPI register. */ + assert(ppi >=3D 0 && ppi < 64); + oldlevel =3D extract64(env->gicv5_cpuif.ppi_pend[0], ppi, 1); + if (oldlevel !=3D level) { + trace_gicv5_update_ppi_state(ppi, level); + + env->gicv5_cpuif.ppi_pend[0] =3D + deposit64(env->gicv5_cpuif.ppi_pend[0], ppi, 1, level); + gic_recalc_ppi_hppi(env); + } +} + static void gic_cddis_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { diff --git a/target/arm/tcg/trace-events b/target/arm/tcg/trace-events index 2bfa8fc552..bf1803c872 100644 --- a/target/arm/tcg/trace-events +++ b/target/arm/tcg/trace-events @@ -8,3 +8,4 @@ gicv5_gicr_cdia(int domain, uint32_t id) "domain %d CDIA ac= knowledge of interrup gicv5_cdeoi(int domain) "domain %d CDEOI performing priority drop" gicv5_cddi(int domain, uint32_t id) "domain %d CDDI deactivating interrupt= ID 0x%x" gicv5_update_irq_fiq(bool irq, bool fiq, bool nmi) "now IRQ %d FIQ %d NMI = %d" +gicv5_update_ppi_state(int ppi, bool level) "PPI %d source level now %d" --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610564; cv=none; d=zohomail.com; s=zohoarc; b=CrY3JzUYC7yVajnNGtJvtr1tZK3HNAXVi6mfX+MLpFijTtai2TiVTh6hYUt6wyC2Dg7jLNWRwMOTR1VKMm+6dvNveAN5r5sePTe5Dvob+rF4cpmmCNSZ2ZGVOI05iAm5tX8IQnpMQWYznyu+K0kQDhWUX+YPY+sCLcu1wu0Zxvc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610564; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=RE5bgzAjVOacUgbbD9Z/UDipABb/jWxn6hy30QQZTF0=; b=ZrMjWvf8fFwQeQ2SrM4sTFUcULcQEQLhl1QYV7i9T2cxrB+SadagHbUdDkN2oXP0N+cadG7o8N10bm5TzVgCrT9SGRYnamTKoQz2pf+l3M5bJVvx+GW99bFrxM83tn1OO889v05eOQkO0nXDOKQP0h7TLL5cElEu5dYCLSnkl6Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610564969120.76372371365369; Fri, 27 Mar 2026 04:22:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65Dk-0001AX-Gd; Fri, 27 Mar 2026 07:19:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65CT-0007RY-Oy for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:18:02 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65CN-0008VI-Ag for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:59 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-43b5bded412so1432756f8f.0 for ; Fri, 27 Mar 2026 04:17:54 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610273; x=1775215073; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RE5bgzAjVOacUgbbD9Z/UDipABb/jWxn6hy30QQZTF0=; b=RFBJH/+D0U6+/9cyZYFrC/4PcQVnTSGJ4DaD2l5O4o2am4oix/9QNyzLDOAqQ5fymm Q9qb9rrQaPHkNkwXoJFvjPAptfECYHEANrlgyzKeNjGPIPl1N08D6dRprC/mAAfDkHzy BNDZzMdebW9k5EnZBTNLXRhwkUvHNFa/qIc0KcUKAxQawNjz1z0zWZh+A2qq3qvlRLsa m5LeipLXe+ZmGKsp33w8XmqzbE83a+7Qk8pyCCNSbv+DLDEN3djig0Fffe91V14tiYzE QUsRQj/PMD0tWPm6SeKk4wWIX12xYPJoVeI7cFfIasPUOAHFp74Oq2xZ4fLIEHUNefjq 6E2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610273; x=1775215073; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=RE5bgzAjVOacUgbbD9Z/UDipABb/jWxn6hy30QQZTF0=; b=RBv6wH2nrurtIECK2O6NkhwWA2FnbI9vPn7BLy3v0uDwa3/F1HMs0278tgz38cYi0b zE7RnYebCWXFB5+vDf5gcAcv7kSlVKyt+b0f2BX1G56MKI4x/bKghrXDSfS2EQzAjraH 7kAy/yh/Emc+6qh1Ls1iY2oRfYOX/FhW6hsXwNyzi3dpSHM/lga8h5OLQ7qM+tFNbiOq SxH5nUGFlEfBFAqLnyY1It2qop7nopQ0M/VRELCwiucAJTuF2Acj55FNs7GLUXZ6NnXm tbzq71v/58DFZniGOxU0rKAtWZo5cFAShj4mxUn+vEWTZ465Pk4JZQ/2mNnZxflpcwhH soTA== X-Forwarded-Encrypted: i=1; AJvYcCX76+dJvWFsPYymrnwS1SCH4VR7uFPui/n2SLSihybJL1L9SEyTsCP1MjUj6TSqN2rTAHvkE4WWsCwT@nongnu.org X-Gm-Message-State: AOJu0Yy3I8PF5a441G153LijPvmyTyFcRk8tyFUx/P7QVO5aCaxFKH2P mhNJb0Jw+0v6dlNeYq5dkLxETfCNEIJobHCtrIHsvS9Mhqxva0Eu2dY0j9LOZg98suI= X-Gm-Gg: ATEYQzxWyRaJb+h2sAULKehHbi/lqk/rysryyVUOlnRsEzbdYpIsvwhOblmRlQz0NIN TxNMarwHwnRb5cRauhugG9boSd3Y6QO165Bdqb86AXJtb4U1aqVyO6ITHk0EKaTt87bPQR6hrYf +WNVeuh3Pa7ZEPFMgm8GdHxg/e5qWvQL64vnfi/Wzzl0liiXsAsqw+/7CAW0ddpcDlFUsK7gMgc 5wK2J5weHRkXo7e7CYISTHLUQ44lIDMc4XlcJg0V2DWs64ODF2BZzxOCRnuKG7ou6sS8rJ8sH9Q IHBslQ5YUnGBonCSm/qdjoIo2iDauqhG2QA3YQNxhzdodBQO/N6MWhOWBK6gF1yfhV2OV0BD198 SN0zDrDay/ut7bMdCmP5hhbJ5M2vKr3zJFnY3oODjabKrKRbiyhiMlzCCmnGFy2OUw9D81TgDrA gm5awl1OEppuY0qAoSuh/6sYDvrlxkYCJk85/v90Cnp5aGDc06S5pnI46UCxhWNSPds69yy5COR tT3yx2wAeEVB7qBBOHz0OW7ZAq95Tk= X-Received: by 2002:a05:6000:4027:b0:43a:580:f60d with SMTP id ffacd0b85a97d-43b9ea4a5b4mr3266355f8f.35.1774610273421; Fri, 27 Mar 2026 04:17:53 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 54/65] target/arm: Add has_gcie property to enable FEAT_GCIE Date: Fri, 27 Mar 2026 11:16:49 +0000 Message-ID: <20260327111700.795099-55-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610566925154100 Content-Type: text/plain; charset="utf-8" Add a has_gcie QOM property to the CPU which allows the board code to enable FEAT_GCIE, the GICv5 CPU interface. Enabling the GICv5 CPU interface comes with a significant restriction: because the GICv5 architecture is Armv9, it assumes the Armv9 requirement that only EL0 (userspace) may be in AArch32. So there are no GIC control system registers defined for AArch32. We force AArch32 at ELs 1, 2 and 3 to disabled, to avoid a guest being able to get into an EL where interrupts are completely broken. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- target/arm/cpu-features.h | 5 +++++ target/arm/cpu.c | 45 +++++++++++++++++++++++++++++++++++++++ target/arm/cpu.h | 2 ++ 3 files changed, 52 insertions(+) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index e391b394ba..c0ba56f244 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1072,6 +1072,11 @@ static inline bool isar_feature_aa64_aa32_el2(const = ARMISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL2) >=3D 2; } =20 +static inline bool isar_feature_aa64_aa32_el3(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL3) >=3D 2; +} + static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64PFR0, RAS) !=3D 0; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ceb303a55a..21c2953501 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1197,6 +1197,9 @@ static const Property arm_cpu_has_el2_property =3D =20 static const Property arm_cpu_has_el3_property =3D DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); + +static const Property arm_cpu_has_gcie_property =3D + DEFINE_PROP_BOOL("has_gcie", ARMCPU, has_gcie, false); #endif =20 static const Property arm_cpu_cfgend_property =3D @@ -1425,6 +1428,11 @@ static void arm_cpu_post_init(Object *obj) object_property_add_uint64_ptr(obj, "rvbar", &cpu->rvbar_prop, OBJ_PROP_FLAG_READWRITE); + + /* We only allow GICv5 on a 64-bit v8 CPU */ + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + qdev_property_add_static(DEVICE(obj), &arm_cpu_has_gcie_proper= ty); + } } =20 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { @@ -1699,6 +1707,12 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) current_accel_name()); return; } + if (cpu->has_gcie) { + error_setg(errp, + "Cannot enable %s when guest CPU has GICv5 enabled", + current_accel_name()); + return; + } } #endif =20 @@ -2022,6 +2036,37 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) FIELD_DP32_IDREG(isar, ID_PFR1, VIRTUALIZATION, 0); } =20 + /* Report FEAT_GCIE in our ID registers if property was set */ + FIELD_DP64_IDREG(isar, ID_AA64PFR2, GCIE, cpu->has_gcie); + if (cpu_isar_feature(aa64_gcie, cpu)) { + if (!arm_feature(env, ARM_FEATURE_AARCH64)) { + /* + * We only create the have_gcie property for AArch64 CPUs, + * but the user might have tried aarch64=3Doff with has_gcie= =3Don. + */ + error_setg(errp, "Cannot both enable has_gcie and disable aarc= h64"); + return; + } + + /* + * FEAT_GCIE implies Armv9, which implies no AArch32 above EL0. + * Usually we don't strictly insist on this kind of feature + * dependency, but in this case we enforce it, because the + * GICv5 CPU interface has no AArch32 versions of its system + * registers, so interrupts wouldn't work if we allowed AArch32 + * in EL1 or above. Downgrade "AArch32 and AArch64" to "AArch64". + */ + if (cpu_isar_feature(aa64_aa32_el3, cpu)) { + FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL3, 1); + } + if (cpu_isar_feature(aa64_aa32_el2, cpu)) { + FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL2, 1); + } + if (cpu_isar_feature(aa64_aa32_el1, cpu)) { + FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL1, 1); + } + } + if (cpu_isar_feature(aa64_mte, cpu)) { /* * The architectural range of GM blocksize is 2-6, however qemu diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 651fccd59b..a5f27dfe0f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1032,6 +1032,8 @@ struct ArchCPU { bool has_neon; /* CPU has M-profile DSP extension */ bool has_dsp; + /* CPU has FEAT_GCIE GICv5 CPU interface */ + bool has_gcie; =20 /* CPU has memory protection unit */ bool has_mpu; --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610565; cv=none; d=zohomail.com; s=zohoarc; b=MHjmrRWuuOt9pHmzmyuo0TW27i+Ti8ht8aK9LijnfPaXin5nHG6ld5fukdpYITpPBAt6HevMPFGq95kwhpZJAz27rKhQPsAiRzXMkiIoQuGHVedOlt5J5yBr4bhDKHcJbjxZhOVmnv33fA6hgICwwcq+L5223tYMd0O4JzzVKMs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610565; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=1a+4VgJGkwP3gKjTiIhrHr9y9Q94+K/thWEGPABWjoI=; b=A2Uc+orNn7TUJ2cn/EnYLJ/zOnKV9rlhQmagSZWERA5FUcQwUttnVIuQHmsmVs+5Dfcu6hHKmFeM7SB6a7hUZgJvuJrwIbcBHmAh0QdQKpDiqC20USkNoGd8Jcaah1wSAOeOUucdDWw1H+LtC0n8AQSXq45qn9OXEI1YwoBvZLw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610565511226.39527735544823; Fri, 27 Mar 2026 04:22:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65DJ-0000Cr-2O; Fri, 27 Mar 2026 07:18:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65CT-0007RZ-P7 for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:18:03 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65CO-00005M-CM for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:58 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-439bcec8613so1482460f8f.3 for ; Fri, 27 Mar 2026 04:17:55 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610274; x=1775215074; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1a+4VgJGkwP3gKjTiIhrHr9y9Q94+K/thWEGPABWjoI=; b=tQ0U+vZkkrdFzQFVLB0RMBI1PpqQvChnbYcyX5ug+8eeaJqUuMwgI+meUH+ZNMa0f0 IKlHVJfLYTC0J9AIIpMYp2YS+JMdBAOIbAOgTXUtkgTMHS+QzCw/iqfdGCWiJGebZgJi uUTE3LK9IIk/2s/nuo3EQ5zPiyhsRNtv3MnzEeQ2XEb+987HvtpJNFDkT+oLCc7sDie5 fWk4q2mYnkMsvSWcM43COkWqQqq+I59twTkrrv4wGw3ivfnGgFJxIyhcn944FP6GFm3J QL/VvpeHTkR4IRfr4Z+gzXnUO2Av3oefjkbJizPTz63juh0P9Pbhaq1CsRDlDr1YkLTl UUZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610274; x=1775215074; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=1a+4VgJGkwP3gKjTiIhrHr9y9Q94+K/thWEGPABWjoI=; b=bKLCCbVELZ19q5yidrEKxoM52gxc7rWLc4vsP0KUokQR3VlRnYb3Jqg3dmXrgFy4io e0plBR8L1bwXQ1o/ilY6bARVtRhlriaNvtSzke3/CA9LqzAX9jyJb5YnqVpc0av1XSNn ZK8IuB9qulkWTPVuND+9tfou+in9gW7zEY8SftSXcr7L+7SW2dcwE876ruUc0W6+LZI1 ULXMUi4jnMUjvNJ4R3EZkoIBjiC7GvLLb1a07GTksQLBHPHibn17sTOAfkitGVdZ/9X/ fVWvMppasXaRFrcXSQmtqtZYpU+vTCf9u/TehozaU3zANT5oY71KaSm1OaVTR/0ysWuv cLUg== X-Forwarded-Encrypted: i=1; AJvYcCWIScXu2phII1Dl4Rl7NVHEEZaz4FASGSgb+pv3qmDK+vmmEWCfBREqfSxZ801AioPotuqgdrdaS8KN@nongnu.org X-Gm-Message-State: AOJu0YxY/ButYJ5LxEGVgFTxofGa764ZiLjnS3C72hzio+tlH81t/M2a S9SQvPASqe9QcTRpPn09Y9AzRVj7Q9hutHU8kkTofCfveOYoT8dvHdH3da6ZHuWfdII= X-Gm-Gg: ATEYQzzON+N4Leg3YVLmTZAUX1qJNBTG4wtx5IekE+Z9f758h/hNxT2Ylb2fYvNvsHA LDb/z58Czmbssf9EMtuFBOYKJXuM064P422XXBh46objq1dXxBvCykImwnc9EyV4V4l1m6Xjd93 puoDBeqcn4hdpx1sr/HQvquV5pWLFBx/5nd5Zc5PGAYvRjU4U/n1f+5bNKuiQRJD79Z4BVYH7Fv aLb+e1scj7b4c5dKMOBEqOxkq+/piVycobungaQGS90wpmxdiiZaGxA9Oy58MxJ5mYruISG63zr lyVGiPG4CLKTACcFfseIpv8ZnZ/PMdj2G793EBjxKotOpwHhfSdXcnQ8H+0VNxj81UQAcm7SqbS cD4Uuf2umb/bvc9oKq/tVsGiZQAPdL/grLzP3TxweomNIuTcnDDgZs9mwvh+CzIFTmcDjUZ2srC sPStwtWyXDE1IInW2H+b8XmX4CNVHayVLfioM+15eJGMMaA8bPC3gXtidup7firjc5AnNcelDLv xU7mZKA9BDSK1GlPq/XIikjl/FJecI= X-Received: by 2002:a05:6000:2dc3:b0:43b:9986:2fbe with SMTP id ffacd0b85a97d-43b9ea76342mr2999444f8f.49.1774610274349; Fri, 27 Mar 2026 04:17:54 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 55/65] hw/intc/arm_gicv3_cpuif: Don't allow GICv3 if CPU has GICv5 cpuif Date: Fri, 27 Mar 2026 11:16:50 +0000 Message-ID: <20260327111700.795099-56-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610567304158500 Content-Type: text/plain; charset="utf-8" The GICv3 and GICv5 CPU interfaces are not compatible, and a CPU will only implement either one or the other. If we find that we're trying to connect a GICv3 to a CPU that implements FEAT_GCIE, fail. This will only happen if the board code has a bug and doesn't configure its CPUs and its GIC consistently. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv3.c | 2 +- hw/intc/arm_gicv3_cpuif.c | 14 +++++++++++++- hw/intc/gicv3_internal.h | 2 +- 3 files changed, 15 insertions(+), 3 deletions(-) diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c index 542f81ea49..e93c1df5b4 100644 --- a/hw/intc/arm_gicv3.c +++ b/hw/intc/arm_gicv3.c @@ -449,7 +449,7 @@ static void arm_gic_realize(DeviceState *dev, Error **e= rrp) =20 gicv3_init_irqs_and_mmio(s, gicv3_set_irq, gic_ops); =20 - gicv3_init_cpuif(s); + gicv3_init_cpuif(s, errp); } =20 static void arm_gicv3_class_init(ObjectClass *klass, const void *data) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index eaf1e512ed..73e06f87d4 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -16,6 +16,7 @@ #include "qemu/bitops.h" #include "qemu/log.h" #include "qemu/main-loop.h" +#include "qapi/error.h" #include "trace.h" #include "gicv3_internal.h" #include "hw/core/irq.h" @@ -3016,7 +3017,7 @@ static void gicv3_cpuif_el_change_hook(ARMCPU *cpu, v= oid *opaque) gicv3_cpuif_virt_irq_fiq_update(cs); } =20 -void gicv3_init_cpuif(GICv3State *s) +void gicv3_init_cpuif(GICv3State *s, Error **errp) { /* Called from the GICv3 realize function; register our system * registers with the CPU @@ -3027,6 +3028,17 @@ void gicv3_init_cpuif(GICv3State *s) ARMCPU *cpu =3D ARM_CPU(qemu_get_cpu(s->first_cpu_idx + i)); GICv3CPUState *cs =3D &s->cpu[i]; =20 + if (cpu_isar_feature(aa64_gcie, cpu)) { + /* + * Attempt to connect GICv3 to a CPU with GICv5 cpuif + * (almost certainly a bug in the board code) + */ + error_setg(errp, + "Cannot connect GICv3 to CPU %d which has GICv5 cpu= if", + i); + return; + } + /* * If the CPU doesn't define a GICv3 configuration, probably becau= se * in real hardware it doesn't have one, then we use default values diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 880dbe52d8..c01be70464 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -722,7 +722,7 @@ void gicv3_redist_mov_vlpi(GICv3CPUState *src, uint64_t= src_vptaddr, void gicv3_redist_vinvall(GICv3CPUState *cs, uint64_t vptaddr); =20 void gicv3_redist_send_sgi(GICv3CPUState *cs, int grp, int irq, bool ns); -void gicv3_init_cpuif(GICv3State *s); +void gicv3_init_cpuif(GICv3State *s, Error **errp); =20 /** * gicv3_cpuif_update: --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610686; cv=none; d=zohomail.com; s=zohoarc; b=YCuR4rV9M20DExKSxZ+sjaKA0d99lfZOLS8QlrwMKz372pktGvtblYJpkoLiBc6FUj6dvQnynSVn5XBxagjuiKFCzs4bfzNBgZ0hhTK7dffjb1U+Zq2i1p2CZP4EKl3j/ZPDI2xVQ/LteNYpTxmugWQG4S14qMkYTbywJEJnqrU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610686; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=zg0JdMYpNPucplnhgObUVKgc6cBxcpxKCbSlMlmDTlo=; b=U8zC/TMboK2UnV/c8bdR4oNm89FdtaigrBlCmkeIyyZEWOgwECVAnmQ4h63IibrqeCnXbSg4lB3OmLdAVEwURYcGrizoksDdOCejq9qm2z2AgLS/B1+ofdyiwKgxEgdxe4cvbvV9BtlVo6j7RNzDO5BHGI24zzFrzwAS7Qys88Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610686648509.5764681683013; Fri, 27 Mar 2026 04:24:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65DS-0000NR-PZ; Fri, 27 Mar 2026 07:19:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65CT-0007Rf-SU for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:18:03 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65CO-00006q-PL for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:59 -0400 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-439b2965d4bso1507057f8f.2 for ; Fri, 27 Mar 2026 04:17:56 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610275; x=1775215075; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zg0JdMYpNPucplnhgObUVKgc6cBxcpxKCbSlMlmDTlo=; b=j8D3pVma0SwUF2JB7puMBVFO4rnfV3/MHoBIKmRxA9YRvvMIjkKNAebiQ5mB2e9CCz FhOcMTUzURNtOmik5aZa/4opeWlB1htRHTszYds4XYJLaIvYiO/CHqkV5uA90hWDnusw Wq6z3tWAj+etEiFgxMGKYI4ZhgKSzEdef4NlH+hgb/SjfTMfXydJCyvPZWaeltbss28O wl55mvKW/og1Yi58/1vJWv3/7L7nOyp9jZO/mVuINd3UY8fUL4aHyW57/nrjmglKqAIA i79/5mykcFqcBfXWiS93nqRdhaC0MaQ9aA4+nQUHcZnMwPEEt/KuFIZDR19xKqKGpD8Q Toqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610275; x=1775215075; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=zg0JdMYpNPucplnhgObUVKgc6cBxcpxKCbSlMlmDTlo=; b=fhp0mRFxQs3wCRXGBzAgQV2j/It6/Fs8ppF+BUOnbG7AoH5Rw1toQvqYDc5xcplz/9 yCM50O5rjxW3ObHAzIWC+EoqJh6xKG+1kVrXGQzzhz7pj7mBKNrpEOlxNMqO8X3llmbK rtgf5wqYmDHeaIVAmBcZld8gKq19AVLeXck9aXFKnYKD7O2SpBes9+1F83yhJv41wwpn wcvS3wHZJpdL5a5y33aafUj/a3cAc6wvj+tLd7s+UOTbYhz+AuHPdYztr29N8glXJqmb AH3j2bWPSjD33lcZwrydNjINJV1J2ioQFB8uR94WanDi2g6oMpPwFsHDcSufmJQiBZmW 02XA== X-Forwarded-Encrypted: i=1; AJvYcCWX0D8Z/ALpQO3RZVN/FLpX/SwkpyF97POfH+TZdXQD3xmqyUPijX7yPYmOFTbM6Qfm76DF5BZf36z0@nongnu.org X-Gm-Message-State: AOJu0YzHoSEjsTaNyE7QedW5QsV9cICOahKTliAjqT73H5EJOTz1Hr/b LiVnLfFcLYIC8rSRbiojIndq+PN7VD6pMpO8i3QZJCsvHgLFssn9OqKs9m8vLkfULpM= X-Gm-Gg: ATEYQzzywLwMpBexc8FWlCAIBHMXS1CxYvBCOO0vTpQ77gkBXVp3wNGZ8ICGvG3C46v 3+GPbmeG72fUhJlQDyio0UZ9XRoGJOBcYoMBBAt2L4mZDP7E9rN+B5IdQ6aVm4EJ8LObT3tboMh dkBjd9j8d62VWF5YaNXZPf7o3zyTJnw5G9X1796uqQ19WcyQqA4quXG7MZfS4hFniLTPYQvlCZH 4ZC9dPrN5r3h1SSEyrcGOZCSOyAMnyrVwNHlbrgyHYkTTfy1m8y0YQpht/dwBzbdsJjOTvHFbJ2 QS9AlmBj2kDKi675QNnhHWbHrkatj3EIF/UbhMIdYiP8ogQTsrtPROiYTRhmmvwmC7ZQam5CMJ/ wkMIMRKhct8JTxpVuSQmLlm7yyLLg6FDf/yPjtSTWC0+BU5tUh56FjUPSQQTAb6w3qKWxfuolax d/C+9xmGmS27qP5dg1y1aNCgzuSIZ/l303HEQXvnq6Soc5X7wIfItBPZdt9pL7b449equpPH9sE yrywbi0OwyDNUvIQmsOmk7rEt43Uk0= X-Received: by 2002:a5d:64e6:0:b0:43b:5037:7ef3 with SMTP id ffacd0b85a97d-43b9e9e8bdamr3113357f8f.20.1774610275201; Fri, 27 Mar 2026 04:17:55 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 56/65] hw/arm/virt: Remember CPU phandles rather than looking them up by name Date: Fri, 27 Mar 2026 11:16:51 +0000 Message-ID: <20260327111700.795099-57-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610688913154100 In fdt_add_cpu_nodes(), we currently add phandles for each CPU node if we are going to add a topology description, and when we do, we re-look-up the phandle by node name when creating the topology description. For GICv5 we will also want to refer to the CPU phandles; so always add a phandle, and keep track of those phandles in the VirtMachineState so we don't have to look them up by name in the dtb every time. The phandle property is extra data in the final DTB, but only a tiny amount, so it's not worth trying to carefully track the conditions when we're going to need them so we only emit them when required. (We need to change the smp_cpus variable to unsigned because otherwise gcc thinks that we might be passing a negative number to g_new0() and produces an error: /usr/include/glib-2.0/glib/gmem.h:270:19: error: argument 1 range [18446744= 071562067968, 18446744073709551615] exceeds maximum object size 92233720368= 54775807 [-Werror=3Dalloc-size-larger-than=3D] 270 | __p =3D g_##func##_n (__n, __s); \ | ^~~~~~~~~~~~~~~~~~~~~~~ /usr/include/glib-2.0/glib/gmem.h:332:57: note: in expansion of macro =E2= =80=98_G_NEW=E2=80=99 332 | #define g_new0(struct_type, n_structs) _G_NEW (str= uct_type, n_structs, malloc0) | ^~~~~~ ../../hw/arm/virt.c:469:25: note: in expansion of macro =E2=80=98g_new0=E2= =80=99 469 | vms->cpu_phandles =3D g_new0(uint32_t, smp_cpus); | ^~~~~~ ) Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/arm/virt.c | 19 ++++++++++--------- include/hw/arm/virt.h | 1 + 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ec0d8475ca..91097e25ec 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -431,13 +431,13 @@ static void fdt_add_timer_nodes(const VirtMachineStat= e *vms) } } =20 -static void fdt_add_cpu_nodes(const VirtMachineState *vms) +static void fdt_add_cpu_nodes(VirtMachineState *vms) { int cpu; int addr_cells =3D 1; const MachineState *ms =3D MACHINE(vms); const VirtMachineClass *vmc =3D VIRT_MACHINE_GET_CLASS(vms); - int smp_cpus =3D ms->smp.cpus; + unsigned int smp_cpus =3D ms->smp.cpus; =20 /* * See Linux Documentation/devicetree/bindings/arm/cpus.yaml @@ -465,10 +465,13 @@ static void fdt_add_cpu_nodes(const VirtMachineState = *vms) qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells); qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); =20 + vms->cpu_phandles =3D g_new0(uint32_t, smp_cpus); + for (cpu =3D smp_cpus - 1; cpu >=3D 0; cpu--) { char *nodename =3D g_strdup_printf("/cpus/cpu@%d", cpu); ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(cpu)); CPUState *cs =3D CPU(armcpu); + uint32_t phandle; =20 qemu_fdt_add_subnode(ms->fdt, nodename); qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); @@ -493,10 +496,9 @@ static void fdt_add_cpu_nodes(const VirtMachineState *= vms) ms->possible_cpus->cpus[cs->cpu_index].props.node_id); } =20 - if (!vmc->no_cpu_topology) { - qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", - qemu_fdt_alloc_phandle(ms->fdt)); - } + phandle =3D qemu_fdt_alloc_phandle(ms->fdt); + qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle); + vms->cpu_phandles[cpu] =3D phandle; =20 g_free(nodename); } @@ -521,7 +523,6 @@ static void fdt_add_cpu_nodes(const VirtMachineState *v= ms) qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); =20 for (cpu =3D smp_cpus - 1; cpu >=3D 0; cpu--) { - char *cpu_path =3D g_strdup_printf("/cpus/cpu@%d", cpu); char *map_path; =20 if (ms->smp.threads > 1) { @@ -539,10 +540,10 @@ static void fdt_add_cpu_nodes(const VirtMachineState = *vms) cpu % ms->smp.cores); } qemu_fdt_add_path(ms->fdt, map_path); - qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); + qemu_fdt_setprop_cell(ms->fdt, map_path, "cpu", + vms->cpu_phandles[cpu]); =20 g_free(map_path); - g_free(cpu_path); } } } diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 5fcbd1c76f..22bbc34ca8 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -171,6 +171,7 @@ struct VirtMachineState { uint32_t gic_phandle; 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Move it to a new create_msi_controller() function. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/arm/virt.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 91097e25ec..544605244b 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -958,11 +958,21 @@ static void create_gic(VirtMachineState *vms, MemoryR= egion *mem) } =20 fdt_add_gic_node(vms); +} =20 - if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_ITS) { +static void create_msi_controller(VirtMachineState *vms) +{ + switch (vms->msi_controller) { + case VIRT_MSI_CTRL_ITS: create_its(vms); - } else if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_GICV2M) { + break; + case VIRT_MSI_CTRL_GICV2M: create_v2m(vms); + break; + case VIRT_MSI_CTRL_NONE: + break; + default: + g_assert_not_reached(); } } =20 @@ -2514,6 +2524,7 @@ static void machvirt_init(MachineState *machine) virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); =20 create_gic(vms, sysmem); + create_msi_controller(vms); =20 virt_post_cpus_gic_realized(vms, sysmem); =20 --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610750; cv=none; d=zohomail.com; s=zohoarc; b=RLtuWOK4Cf+s56cIerX8mUqrJ3Z9byPDkJRDZJIKzCGvETOiRMjY399QFwK9EqR7D8KrA1r2b61IYXM0ocOw7eJknmCpzxmkuO2D+bd4UvkjDptPD8T+46lvWVUVWj1hnT1LZv3NeTmKbX6DR/ZQNvx6kv++zImVeqRsjt5Uwbg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610750; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=NrTKpprv3zreT1hOn+OhcK5Z8pr1JULBMiSX0Lhf8qo=; b=O/vVjUxUh92wsB0xU0CDMlxeyhX/h7SbmyN2MwE+IvcekDpw6rvDWIYDDyLyIAOUddQFjDmQYAwGfNtfCop3hSnYhZTDxW0wAOO9HnKSdZcnJ1CWzkno+hNzFpxyqkhalk2Bjk/vy3NSyjuvbc/Lf4dRQJlR2Q/ryMSQsky6Ubw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610750910799.2526592806034; Fri, 27 Mar 2026 04:25:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65Dp-0001hC-1W; Fri, 27 Mar 2026 07:19:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65CV-0007Tr-Jf for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:18:05 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65CT-00008s-9g for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:18:02 -0400 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-43b5bded412so1432804f8f.0 for ; Fri, 27 Mar 2026 04:17:58 -0700 (PDT) Received: from lanath.. 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As a preliminary to splitting it up, pull out the "wire the CPU interrupts to the GIC PPI inputs" code out into its own function. This is a long and self-contained piece of code that is the main thing that we need to do basically the same way for GICv2 and GICv3. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/arm/virt.c | 126 +++++++++++++++++++++++++++----------------------- 1 file changed, 68 insertions(+), 58 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 544605244b..5a2cb81919 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -794,13 +794,79 @@ static bool gicv3_nmi_present(VirtMachineState *vms) (vms->gic_version !=3D VIRT_GIC_VERSION_2); } =20 +static void gic_connect_ppis(VirtMachineState *vms) +{ + /* + * Wire the outputs from each CPU's generic timer and the GICv3 + * maintenance interrupt signal to the appropriate GIC PPI inputs, + * and the GIC's IRQ/FIQ/VIRQ/VFIQ/NMI/VINMI interrupt outputs to the + * CPU's inputs. + */ + MachineState *ms =3D MACHINE(vms); + unsigned int smp_cpus =3D ms->smp.cpus; + SysBusDevice *gicbusdev =3D SYS_BUS_DEVICE(vms->gic); + + for (int i =3D 0; i < smp_cpus; i++) { + DeviceState *cpudev =3D DEVICE(qemu_get_cpu(i)); + int intidbase =3D NUM_IRQS + i * GIC_INTERNAL; + /* + * Mapping from the output timer irq lines from the CPU to the + * GIC PPI inputs we use for the virt board. + */ + const int timer_irq[] =3D { + [GTIMER_PHYS] =3D ARCH_TIMER_NS_EL1_IRQ, + [GTIMER_VIRT] =3D ARCH_TIMER_VIRT_IRQ, + [GTIMER_HYP] =3D ARCH_TIMER_NS_EL2_IRQ, + [GTIMER_SEC] =3D ARCH_TIMER_S_EL1_IRQ, + [GTIMER_HYPVIRT] =3D ARCH_TIMER_NS_EL2_VIRT_IRQ, + [GTIMER_S_EL2_PHYS] =3D ARCH_TIMER_S_EL2_IRQ, + [GTIMER_S_EL2_VIRT] =3D ARCH_TIMER_S_EL2_VIRT_IRQ, + }; + + for (unsigned irq =3D 0; irq < ARRAY_SIZE(timer_irq); irq++) { + qdev_connect_gpio_out(cpudev, irq, + qdev_get_gpio_in(vms->gic, + intidbase + timer_irq[i= rq])); + } + + if (vms->gic_version !=3D VIRT_GIC_VERSION_2) { + qemu_irq irq =3D qdev_get_gpio_in(vms->gic, + intidbase + ARCH_GIC_MAINT_IRQ= ); + qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interru= pt", + 0, irq); + } else if (vms->virt) { + qemu_irq irq =3D qdev_get_gpio_in(vms->gic, + intidbase + ARCH_GIC_MAINT_IRQ= ); + sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); + } + + qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, + qdev_get_gpio_in(vms->gic, intidbase + + VIRTUAL_PMU_IRQ)); + + sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_= IRQ)); + sysbus_connect_irq(gicbusdev, i + smp_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); + sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); + sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); + + if (vms->gic_version !=3D VIRT_GIC_VERSION_2) { + sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_NMI)); + sysbus_connect_irq(gicbusdev, i + 5 * smp_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_VINMI)); + } + } +} + static void create_gic(VirtMachineState *vms, MemoryRegion *mem) { MachineState *ms =3D MACHINE(vms); /* We create a standalone GIC */ SysBusDevice *gicbusdev; const char *gictype; - int i; unsigned int smp_cpus =3D ms->smp.cpus; uint32_t nb_redist_regions =3D 0; int revision; @@ -899,63 +965,7 @@ static void create_gic(VirtMachineState *vms, MemoryRe= gion *mem) } } =20 - /* Wire the outputs from each CPU's generic timer and the GICv3 - * maintenance interrupt signal to the appropriate GIC PPI inputs, - * and the GIC's IRQ/FIQ/VIRQ/VFIQ/NMI/VINMI interrupt outputs to the - * CPU's inputs. - */ - for (i =3D 0; i < smp_cpus; i++) { - DeviceState *cpudev =3D DEVICE(qemu_get_cpu(i)); - int intidbase =3D NUM_IRQS + i * GIC_INTERNAL; - /* Mapping from the output timer irq lines from the CPU to the - * GIC PPI inputs we use for the virt board. - */ - const int timer_irq[] =3D { - [GTIMER_PHYS] =3D ARCH_TIMER_NS_EL1_IRQ, - [GTIMER_VIRT] =3D ARCH_TIMER_VIRT_IRQ, - [GTIMER_HYP] =3D ARCH_TIMER_NS_EL2_IRQ, - [GTIMER_SEC] =3D ARCH_TIMER_S_EL1_IRQ, - [GTIMER_HYPVIRT] =3D ARCH_TIMER_NS_EL2_VIRT_IRQ, - [GTIMER_S_EL2_PHYS] =3D ARCH_TIMER_S_EL2_IRQ, - [GTIMER_S_EL2_VIRT] =3D ARCH_TIMER_S_EL2_VIRT_IRQ, - }; - - for (unsigned irq =3D 0; irq < ARRAY_SIZE(timer_irq); irq++) { - qdev_connect_gpio_out(cpudev, irq, - qdev_get_gpio_in(vms->gic, - intidbase + timer_irq[i= rq])); - } - - if (vms->gic_version !=3D VIRT_GIC_VERSION_2) { - qemu_irq irq =3D qdev_get_gpio_in(vms->gic, - intidbase + ARCH_GIC_MAINT_IRQ= ); - qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interru= pt", - 0, irq); - } else if (vms->virt) { - qemu_irq irq =3D qdev_get_gpio_in(vms->gic, - intidbase + ARCH_GIC_MAINT_IRQ= ); - sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); - } - - qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, - qdev_get_gpio_in(vms->gic, intidbase - + VIRTUAL_PMU_IRQ)); - - sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_= IRQ)); - sysbus_connect_irq(gicbusdev, i + smp_cpus, - qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); - sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, - qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); - sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, - qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); - - if (vms->gic_version !=3D VIRT_GIC_VERSION_2) { - sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, - qdev_get_gpio_in(cpudev, ARM_CPU_NMI)); - sysbus_connect_irq(gicbusdev, i + 5 * smp_cpus, - qdev_get_gpio_in(cpudev, ARM_CPU_VINMI)); - } - } + gic_connect_ppis(vms); =20 fdt_add_gic_node(vms); } --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610738; cv=none; d=zohomail.com; s=zohoarc; b=a01kdfbjtY6Vxw0mXbm9yZK0sccspSlnbcxBo4nIdKCz38+YoVPgtwNrabJ0XQOA7JQrn2a2UKVW2M41Ue6f0AyBP9DFlXESC77ereGUsOucbb88yo2J62eDUHg9Vj5TK2jtQqzT/TzhRPiQ9EEwF34ayfMXC3M6qgksgDt9bYo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610738; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610278; x=1775215078; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CReBByvpzpB+DOsYFrY4nglOIG+4SryQVlLfXuYbQ0g=; b=jZ7by7kJ8hX3IEPTeLgmw5+0iyVNOLMunl6XZfylrLinzr9j2N/lZpOeYyWfoM+YNr dk0NL0jZBFc9fablhI/99a4iWTB3av9c+ywDQvI0+3PSM8rbpV62LdH5HVRnCgWrWBav bN+dI7BEh0gxvU/ZkBr256BeS0iN8CQinwpBfCLuO5+f6e73Etg/z4zAXnaNyhUC1Ma+ ZwylSKf3YkUW0TX0CSWtcetcdCOgo6kHcrHZTE4J8rrca7r8FO/lsxJsQSxBqG4BlYVK vEZYfjJddRuWQwLCtsaPKkD0mPcpUq+qsMo2nE9Fm1xfyo3xilzrYO/mCnp8E5CwJO+6 0Pkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610278; x=1775215078; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=CReBByvpzpB+DOsYFrY4nglOIG+4SryQVlLfXuYbQ0g=; b=RknIOKoq8WER3vnxIOXrZT4gb3DE24+6x2NS4z+8aqSW2+pgtyaugeLA7Wt0+OA8am Y3OMLYFqh2NcWLcKekLnW0KZCjdSg5QIWAN7TwhEVn66D83NtO3QWikn1wriyblOIgPH q6iTIhEgXegbAgLukjtqIxpWSGyXwsDk2Nd1Rw8RKJFfKjpGV/OqzptjbiLEK//+06R1 r3teWeI5zEVT/oG03XS9OPEiYzCMWPFGGWCKM4RCg+k83wIgSY42mz2N8niThpNUrfrA XSER8CzX8fKHAt5GLuxxGyG/mGzMfW6oj3Oh49jGaSoqIn8ubu846nDG29YeIG/vVw8g ZVew== X-Forwarded-Encrypted: i=1; AJvYcCWzcIeD8SswEudh2CJKzkQF4DPbeH0ZUqqbE2GGISHoYtYXbdcslvzUJqm05iv42KJ0DZB8V9Wt/jMV@nongnu.org X-Gm-Message-State: AOJu0YxOtBTJe0i38jgRTsV52Qr6kTt6oxAgFbCSh6cGX+PoG3nxsrns bF0K2/zOdth4RJnYbaXw9sA0TsyAHVB8qvz6o4oSNk0yvS7sqcThwWlLaFpjMl6nHgE= X-Gm-Gg: ATEYQzwNfVdJ1wTpQpnyUfy/CEglbs+V7Yv+9lxCTcqNr1D7pBM8yJSMzJwl+VP6NF2 6Dz4urx/Qqhc1Fy4/0C/NlG63/gaA8kzGOl84yn8m5nh2oIpeDpQIiCoK7bziKJoU5ZUfbyf//a Wyz7ME/GVWkywWFaot56DRJ2h3Hkq5MJ0s7Drkhac5t43InxcVdbHHHCvn/r9nwmQj27Z0wp0p4 Lio4xO6mLWmxy8VsTuL1csE997aMBlnoGBAxdmY1vGV0c9XAycPEuqKZdXQ08q3Q4fKUqORx8c5 vzwnniGjds+h2zjMwoC1WeKZgH4VjBS1LR5Z7qVGat57Cn8KcIjAHKNRyftzXymcYO8Hf1V6FvN 8EjVD5SYHkAX6GSoIcspY0nXRUKYLnePhjDor38dUrTPHJ9KjGm2g13cniL4LRgiWiSjFwo9B63 ewiIhyb1E3J3XdS67hErlV8HkzSJxFb8NyIv/kXz0nA0EoU2X7KBOlHiEmTjDKKpzQUSrTijRzH jz4nUOhMaEGOoQ2QeZPvI51rrIUdW0= X-Received: by 2002:a05:6000:2884:b0:43b:54c9:85f4 with SMTP id ffacd0b85a97d-43b9eaad5e6mr3657995f8f.39.1774610277750; Fri, 27 Mar 2026 04:17:57 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 59/65] hw/arm/virt: Split GICv2 and GICv3/4 creation Date: Fri, 27 Mar 2026 11:16:54 +0000 Message-ID: <20260327111700.795099-60-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610740220158500 Content-Type: text/plain; charset="utf-8" Currently create_gic() handles GICv2 and GICv3/4 in a single function, with large sections that are conditional on the vms->gic_version. GICv5 will be different to both. Refactor into create_gicv2() and create_gicv3(). Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/arm/virt.c | 137 ++++++++++++++++++++++++++++++-------------------- 1 file changed, 82 insertions(+), 55 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 5a2cb81919..8c383d7e40 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -861,26 +861,58 @@ static void gic_connect_ppis(VirtMachineState *vms) } } =20 -static void create_gic(VirtMachineState *vms, MemoryRegion *mem) +static void create_gicv2(VirtMachineState *vms, MemoryRegion *mem) { MachineState *ms =3D MACHINE(vms); /* We create a standalone GIC */ SysBusDevice *gicbusdev; - const char *gictype; unsigned int smp_cpus =3D ms->smp.cpus; - uint32_t nb_redist_regions =3D 0; - int revision; =20 - if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) { - gictype =3D gic_class_name(); - } else { - gictype =3D gicv3_class_name(); + if (kvm_enabled() && vms->virt) { + error_report("KVM EL2 is only supported with in-kernel GICv3"); + exit(1); } =20 + vms->gic =3D qdev_new(gic_class_name()); + qdev_prop_set_uint32(vms->gic, "revision", 2); + qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); + /* + * Note that the num-irq property counts both internal and external + * interrupts; there are always 32 of the former (mandated by GIC spec= ). + */ + qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); + if (!kvm_irqchip_in_kernel()) { + qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure= ); + qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", vms->= virt); + } + + gicbusdev =3D SYS_BUS_DEVICE(vms->gic); + sysbus_realize_and_unref(gicbusdev, &error_fatal); + sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); + sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); + if (vms->virt) { + sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); + sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); + } + + gic_connect_ppis(vms); + + fdt_add_gic_node(vms); +} + +static void create_gicv3(VirtMachineState *vms, MemoryRegion *mem) +{ + MachineState *ms =3D MACHINE(vms); + /* We create a standalone GIC */ + SysBusDevice *gicbusdev; + unsigned int smp_cpus =3D ms->smp.cpus; + uint32_t nb_redist_regions; + int revision; + QList *redist_region_count; + uint32_t redist0_capacity =3D virt_redist_capacity(vms, VIRT_GIC_REDIS= T); + uint32_t redist0_count =3D MIN(smp_cpus, redist0_capacity); + switch (vms->gic_version) { - case VIRT_GIC_VERSION_2: - revision =3D 2; - break; case VIRT_GIC_VERSION_3: revision =3D 3; break; @@ -897,10 +929,11 @@ static void create_gic(VirtMachineState *vms, MemoryR= egion *mem) exit(1); } =20 - vms->gic =3D qdev_new(gictype); + vms->gic =3D qdev_new(gicv3_class_name()); qdev_prop_set_uint32(vms->gic, "revision", revision); qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); - /* Note that the num-irq property counts both internal and external + /* + * Note that the num-irq property counts both internal and external * interrupts; there are always 32 of the former (mandated by GIC spec= ). */ qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); @@ -908,40 +941,28 @@ static void create_gic(VirtMachineState *vms, MemoryR= egion *mem) qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure= ); } =20 - if (vms->gic_version !=3D VIRT_GIC_VERSION_2) { - QList *redist_region_count; - uint32_t redist0_capacity =3D virt_redist_capacity(vms, VIRT_GIC_R= EDIST); - uint32_t redist0_count =3D MIN(smp_cpus, redist0_capacity); + nb_redist_regions =3D virt_gicv3_redist_region_count(vms); =20 - nb_redist_regions =3D virt_gicv3_redist_region_count(vms); + redist_region_count =3D qlist_new(); + qlist_append_int(redist_region_count, redist0_count); + if (nb_redist_regions =3D=3D 2) { + uint32_t redist1_capacity =3D + virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); =20 - redist_region_count =3D qlist_new(); - qlist_append_int(redist_region_count, redist0_count); - if (nb_redist_regions =3D=3D 2) { - uint32_t redist1_capacity =3D - virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); + qlist_append_int(redist_region_count, + MIN(smp_cpus - redist0_count, redist1_capacity)); + } + qdev_prop_set_array(vms->gic, "redist-region-count", redist_region_cou= nt); =20 - qlist_append_int(redist_region_count, - MIN(smp_cpus - redist0_count, redist1_capacity)); - } - qdev_prop_set_array(vms->gic, "redist-region-count", - redist_region_count); - - if (!kvm_irqchip_in_kernel()) { - if (vms->tcg_its) { - object_property_set_link(OBJECT(vms->gic), "sysmem", - OBJECT(mem), &error_fatal); - qdev_prop_set_bit(vms->gic, "has-lpi", true); - } - } else if (vms->virt) { - qdev_prop_set_uint32(vms->gic, "maintenance-interrupt-id", - ARCH_GIC_MAINT_IRQ); - } - } else { - if (!kvm_irqchip_in_kernel()) { - qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", - vms->virt); + if (!kvm_irqchip_in_kernel()) { + if (vms->tcg_its) { + object_property_set_link(OBJECT(vms->gic), "sysmem", OBJECT(me= m), + &error_fatal); + qdev_prop_set_bit(vms->gic, "has-lpi", true); } + } else if (vms->virt) { + qdev_prop_set_uint32(vms->gic, "maintenance-interrupt-id", + ARCH_GIC_MAINT_IRQ); } =20 if (gicv3_nmi_present(vms)) { @@ -951,18 +972,9 @@ static void create_gic(VirtMachineState *vms, MemoryRe= gion *mem) gicbusdev =3D SYS_BUS_DEVICE(vms->gic); sysbus_realize_and_unref(gicbusdev, &error_fatal); sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); - if (vms->gic_version !=3D VIRT_GIC_VERSION_2) { - sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); - if (nb_redist_regions =3D=3D 2) { - sysbus_mmio_map(gicbusdev, 2, - vms->memmap[VIRT_HIGH_GIC_REDIST2].base); - } - } else { - sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); - if (vms->virt) { - sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); - sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); - } + sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); + if (nb_redist_regions =3D=3D 2) { + sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].b= ase); } =20 gic_connect_ppis(vms); @@ -970,6 +982,21 @@ static void create_gic(VirtMachineState *vms, MemoryRe= gion *mem) fdt_add_gic_node(vms); } =20 +static void create_gic(VirtMachineState *vms, MemoryRegion *mem) +{ + switch (vms->gic_version) { + case VIRT_GIC_VERSION_2: + create_gicv2(vms, mem); + break; + case VIRT_GIC_VERSION_3: + case VIRT_GIC_VERSION_4: + create_gicv3(vms, mem); + break; + default: + g_assert_not_reached(); + } +} + static void create_msi_controller(VirtMachineState *vms) { switch (vms->msi_controller) { --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610758; cv=none; d=zohomail.com; s=zohoarc; b=WyFvrJFgeyu25d9+f0yo1ud9kzIJbf15RUg9EC23ekIXaHps5FSTGMdh0QRtA1LY/qy/ktHpkeYw7KVW6I+xIrqAqvR1SJbpowtYmOeRoZLW6RuYbGFlCDWLl+iNwvgNofDo/f54NNMME1b9mVaZpVZc7SwIdSQgPyYJ9wCrgU0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610758; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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We do not advertise it in the ACPI tables or DTB; that will be done in a following commit. The user-facing gic-version property still only documents and permits in its setter function the existing set of possible values; we won't permit the user to select a GICv5 until all the code to handle it is in place. Although we currently implement only the IRS, and only for EL1, we reserve space in the virt board's memory map now for all the register frames that the GICv5 may use. Each interrupt domain has: * one IRS config register frame * one ITS config register frame * one ITS translate register frame and each of these frames is 64K in size and 64K aligned and must be at a unique address (that is, it is not permitted to have all the IRS config register frames at the same physical address in the different S/NS/etc physical address spaces). The addresses and layout of these frames are entirely up to the implementation: software will be passed their addresses via firmware data structures (ACPI or DTB). Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/arm/virt.c | 101 ++++++++++++++++++++++++++++++++++++++++++ include/hw/arm/virt.h | 14 ++++++ 2 files changed, 115 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 8c383d7e40..b6a04f868b 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -69,6 +69,7 @@ #include "hw/intc/arm_gic.h" #include "hw/intc/arm_gicv3_common.h" #include "hw/intc/arm_gicv3_its_common.h" +#include "hw/intc/arm_gicv5_common.h" #include "hw/core/irq.h" #include "kvm_arm.h" #include "whpx_arm.h" @@ -184,6 +185,19 @@ static const MemMapEntry base_memmap[] =3D { [VIRT_GIC_ITS] =3D { 0x08080000, 0x00020000 }, /* This redistributor space allows up to 2*64kB*123 CPUs */ [VIRT_GIC_REDIST] =3D { 0x080A0000, 0x00F60000 }, + /* The GICv5 uses this address range differently from GICv2/v3/v4 */ + [VIRT_GICV5_IRS_S] =3D { 0x08000000, 0x00010000 }, + [VIRT_GICV5_IRS_NS] =3D { 0x08010000, 0x00010000 }, + [VIRT_GICV5_IRS_EL3] =3D { 0x08020000, 0x00010000 }, + [VIRT_GICV5_IRS_REALM] =3D { 0x08030000, 0x00010000 }, + [VIRT_GICV5_ITS_S] =3D { 0x08040000, 0x00010000 }, + [VIRT_GICV5_ITS_NS] =3D { 0x08050000, 0x00010000 }, + [VIRT_GICV5_ITS_EL3] =3D { 0x08060000, 0x00010000 }, + [VIRT_GICV5_ITS_REALM] =3D { 0x08070000, 0x00010000 }, + [VIRT_GICV5_ITS_TR_S] =3D { 0x08080000, 0x00010000 }, + [VIRT_GICV5_ITS_TR_NS] =3D { 0x08090000, 0x00010000 }, + [VIRT_GICV5_ITS_TR_EL3] =3D { 0x080A0000, 0x00010000 }, + [VIRT_GICV5_ITS_TR_REALM] =3D { 0x080B0000, 0x00010000 }, [VIRT_UART0] =3D { 0x09000000, 0x00001000 }, [VIRT_RTC] =3D { 0x09010000, 0x00001000 }, [VIRT_FW_CFG] =3D { 0x09020000, 0x00000018 }, @@ -780,6 +794,49 @@ static void create_v2m(VirtMachineState *vms) vms->msi_controller =3D VIRT_MSI_CTRL_GICV2M; } =20 +static void create_gicv5(VirtMachineState *vms, MemoryRegion *mem) +{ + MachineState *ms =3D MACHINE(vms); + SysBusDevice *gicbusdev; + const char *gictype =3D gicv5_class_name(); + QList *cpulist =3D qlist_new(), *iaffidlist =3D qlist_new(); + + vms->gic =3D qdev_new(gictype); + qdev_prop_set_uint32(vms->gic, "spi-range", NUM_IRQS); + + object_property_set_link(OBJECT(vms->gic), "sysmem", OBJECT(mem), + &error_fatal); + + for (int i =3D 0; i < ms->smp.cpus; i++) { + qlist_append_link(cpulist, OBJECT(qemu_get_cpu(i))); + /* + * GICv5 IAFFIDs must be system-wide unique across all GICs. + * For virt we make them the same as the CPU index. + */ + qlist_append_int(iaffidlist, i); + } + qdev_prop_set_array(vms->gic, "cpus", cpulist); + qdev_prop_set_array(vms->gic, "cpu-iaffids", iaffidlist); + + gicbusdev =3D SYS_BUS_DEVICE(vms->gic); + sysbus_realize_and_unref(gicbusdev, &error_fatal); + + /* + * Map the IRS config frames for the interrupt domains. + * At the moment we implement only the NS domain, so this is simple. + */ + sysbus_mmio_map(gicbusdev, GICV5_ID_NS, + vms->memmap[VIRT_GICV5_IRS_NS].base); + + /* + * The GICv5 does not need to wire up CPU timer IRQ outputs to the GIC + * because for the GICv5 those PPIs are entirely internal to the CPU. + * Nor do we need to wire up GIC IRQ/FIQ signals to the CPUs, because + * that information is communicated directly between a GICv5 IRS and + * the GICv5 CPU interface via our equivalent of the stream protocol. + */ +} + /* * If the CPU has FEAT_NMI, then turn on the NMI support in the GICv3 too. * It's permitted to have a configuration with NMI in the CPU (and thus the @@ -992,6 +1049,9 @@ static void create_gic(VirtMachineState *vms, MemoryRe= gion *mem) case VIRT_GIC_VERSION_4: create_gicv3(vms, mem); break; + case VIRT_GIC_VERSION_5: + create_gicv5(vms, mem); + break; default: g_assert_not_reached(); } @@ -1927,6 +1987,11 @@ static uint64_t virt_cpu_mp_affinity(VirtMachineStat= e *vms, int idx) /* * Adjust MPIDR to make TCG consistent (with 64-bit KVM hosts) * and to improve SGI efficiency. + * - GICv2 only supports 8 CPUs anyway + * - GICv3 wants 16 CPUs per Aff0 because of an ICC_SGIxR + * register limitation + * - GICv5 has no restrictions, so we retain the GICv3 16-per-Aff0 + * layout because that's what KVM does */ if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) { clustersz =3D GIC_TARGETLIST_BITS; @@ -2072,6 +2137,11 @@ static VirtGICType finalize_gic_version_do(const cha= r *accel_name, return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX, gics_supported, max_cpus); case VIRT_GIC_VERSION_MAX: + /* + * We don't (currently) make 'max' select GICv5 as it is not + * backwards compatible for system software with GICv3/v4 and + * at time of writing not widely supported in guest kernels. + */ if (gics_supported & VIRT_GIC_VERSION_4_MASK) { gic_version =3D VIRT_GIC_VERSION_4; } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { @@ -2100,6 +2170,7 @@ static VirtGICType finalize_gic_version_do(const char= *accel_name, case VIRT_GIC_VERSION_2: case VIRT_GIC_VERSION_3: case VIRT_GIC_VERSION_4: + case VIRT_GIC_VERSION_5: break; } =20 @@ -2124,6 +2195,12 @@ static VirtGICType finalize_gic_version_do(const cha= r *accel_name, exit(1); } break; + case VIRT_GIC_VERSION_5: + if (!(gics_supported & VIRT_GIC_VERSION_5_MASK)) { + error_report("%s does not support GICv5 emulation", accel_name= ); + exit(1); + } + break; default: error_report("logic error in finalize_gic_version"); exit(1); @@ -2175,6 +2252,10 @@ static void finalize_gic_version(VirtMachineState *v= ms) gics_supported |=3D VIRT_GIC_VERSION_4_MASK; } } + if (!hvf_enabled() && module_object_class_by_name("arm-gicv5")) { + /* HVF doesn't have GICv5 support */ + gics_supported |=3D VIRT_GIC_VERSION_5_MASK; + } } else { error_report("Unsupported accelerator, can not determine GIC suppo= rt"); exit(1); @@ -2208,6 +2289,9 @@ static void finalize_msi_controller(VirtMachineState = *vms) vms->msi_controller =3D VIRT_MSI_CTRL_GICV2M; } else if (whpx_enabled()) { vms->msi_controller =3D VIRT_MSI_CTRL_GICV2M; + } else if (vms->gic_version =3D=3D VIRT_GIC_VERSION_5) { + /* GICv5 ITS is not yet implemented */ + vms->msi_controller =3D VIRT_MSI_CTRL_NONE; } else { vms->msi_controller =3D VIRT_MSI_CTRL_ITS; } @@ -2223,6 +2307,10 @@ static void finalize_msi_controller(VirtMachineState= *vms) error_report("GICv2 + ITS is an invalid configuration."); exit(1); } + if (vms->gic_version =3D=3D VIRT_GIC_VERSION_5) { + error_report("GICv5 + ITS is not yet implemented."); + exit(1); + } if (whpx_enabled()) { error_report("ITS not supported on WHPX."); exit(1); @@ -2395,6 +2483,13 @@ static void machvirt_init(MachineState *machine) */ if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) { virt_max_cpus =3D GIC_NCPU; + } else if (vms->gic_version =3D=3D VIRT_GIC_VERSION_5) { + /* + * GICv5 imposes no CPU limit beyond the 16-bit IAFFID field. + * The maximum number of CPUs will be limited not by this, but + * by the MachineClass::max_cpus value we set earlier. + */ + virt_max_cpus =3D 1 << QEMU_GICV5_IAFFID_BITS; } else { virt_max_cpus =3D virt_redist_capacity(vms, VIRT_GIC_REDIST); if (vms->highmem_redists) { @@ -2440,6 +2535,12 @@ static void machvirt_init(MachineState *machine) exit(1); } =20 + if ((vms->virt || vms->secure) && + vms->gic_version =3D=3D VIRT_GIC_VERSION_5) { + error_report("mach-virt: GICv5 currently supports EL1 only\n"); + exit(1); + } + create_fdt(vms); =20 assert(possible_cpus->len =3D=3D max_cpus); diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 22bbc34ca8..0a804ddad4 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -63,6 +63,18 @@ enum { VIRT_GIC_VCPU, VIRT_GIC_ITS, VIRT_GIC_REDIST, + VIRT_GICV5_IRS_S, + VIRT_GICV5_IRS_NS, + VIRT_GICV5_IRS_EL3, + VIRT_GICV5_IRS_REALM, + VIRT_GICV5_ITS_S, + VIRT_GICV5_ITS_NS, + VIRT_GICV5_ITS_EL3, + VIRT_GICV5_ITS_REALM, + VIRT_GICV5_ITS_TR_S, + VIRT_GICV5_ITS_TR_NS, + VIRT_GICV5_ITS_TR_EL3, + VIRT_GICV5_ITS_TR_REALM, VIRT_SMMU, VIRT_UART0, VIRT_MMIO, @@ -116,12 +128,14 @@ typedef enum VirtGICType { VIRT_GIC_VERSION_2 =3D 2, VIRT_GIC_VERSION_3 =3D 3, VIRT_GIC_VERSION_4 =3D 4, + VIRT_GIC_VERSION_5 =3D 5, VIRT_GIC_VERSION_NOSEL, } VirtGICType; =20 #define VIRT_GIC_VERSION_2_MASK BIT(VIRT_GIC_VERSION_2) #define VIRT_GIC_VERSION_3_MASK BIT(VIRT_GIC_VERSION_3) #define VIRT_GIC_VERSION_4_MASK BIT(VIRT_GIC_VERSION_4) +#define VIRT_GIC_VERSION_5_MASK BIT(VIRT_GIC_VERSION_5) =20 struct VirtMachineClass { MachineClass parent; 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:17:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610280; x=1775215080; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1bFuTPS3UTloN9GePWn+4uta9cNIKepddcVURPyhzcE=; b=g9HJU6ypSgFWlnmGM2ZZPHM/GqKKagifzBykiBZP2fBtXpWDnsDc9FDvEn13QTaozP OKckfMzX3uIyQLh9fs7r1nKEKxmUs4089DQ3YFyIPjfylId/srojm9YBgVUys0Cb8gAG U2UDqxW+kmCFyGypKexteakJsY2EsaIdfgdMid9NS4LYnbbd1SkyGQskeVdzSGmd13iH KbIgcq+wPlZB6RzrpAFseYf/58diqmCcoPFb81uR6t3hk19BqmivgwzV+RsFYpQ1k5s+ AgoKtBJNnwfBiC0lHpCb7JE1BPlVWCS59pXOW2FyUcwntNSg3BHyiBFsi2Q9Naug5lZj NTLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610280; x=1775215080; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=1bFuTPS3UTloN9GePWn+4uta9cNIKepddcVURPyhzcE=; b=d2TAnxx2pdRak1V2anibO57snzvhfhc8Dt9Y/KJZfNcyl19jx+L8mFz5Pnd+Lnp9D0 8/bjZ8uQzeoqMyGEskdOmuNmmjUAlqhgmyKlRvh+uJldGipiixNdH4v97K7bvpuu7VE7 A1qYnkxvxlync2Ms1abjiFvroD/g+kmvmfzbyOwqR5CaFQ5BYBqMoayAYNQIdOuaU76h +E4ykdMTOxHiZX21m1rKNQOGxp9i5oCSjLDfAE2X875bwnaRb8biimKwLvBxGx6NIb4U lfVvtfEStv9Uxf4keG6JnEMFrgjkn2/LVyDSd3k6zZE1Wyq/jinxL/2Zet3WD2lgd2ws eehw== X-Forwarded-Encrypted: i=1; AJvYcCXnSpt8CbKm8D+taz399PJ0wSz7e5vsseFGvapLDPAmYIPcVYyKu/zRStFZOn1YPKLknk5mYdlJhiDU@nongnu.org X-Gm-Message-State: AOJu0YwUWRwPx2veAecUFIweTsx9a93nsk9OcEbIe13lgyC3s7Ls0nAH kSgaWh/7HFdFE5WyodPOZB2M/mhG94HgpSmqCREBZbP8kqOqs1/sH8KGIbgl5fq+mcA= X-Gm-Gg: ATEYQzzvEWXr6YOwfjwZAkVIzHxF5KlmyRSPcBlk0SKLU4hjWAX7KNo4F2sHwTFe7q9 eMoxd3X01zQPLaHlsPCtGyLK41cs7eZpdOsdGz6pg3Lqggzs5piUfWX5iZsPMgcD0IQYbuPHTHn /zU6YVO/sw3xojQ2cr0vYYuMKPYvaYAyh7Zqnm/NT6iejZbMhdcrJYO/qFM8hTFli7RcVetYLmo nnp71MmLK9iFYMQzgLXMiFmimQYfK8VC4McldtoHDotDMQHERfuaVYVVO3KR/eBxIGIDUbUxNje Ta2rBNyzZ/5vFFcKuVRAE+lifajbf9GLIrRPuixNc/Mi/jjjjNNf9JBxpFC7MOwFgPAGMTjsyaV aH5sbjDzVTEdf+eA8fVpZWyYdB9TlMcMJOM8CBIiT5fMti+GhQ+yX6JeIPRlO19v8StHYgwEYbD PKdJsKc5xxTRawEZ2vCiJznpTf4+svu69KjMyiaterZ1WU8oJySV/hKHle7q1DTj7c9kWiXBlVT c1p/EZ3PuDlL1q0Il8Knj4ieana8yI= X-Received: by 2002:a5d:64e4:0:b0:43a:16aa:1448 with SMTP id ffacd0b85a97d-43b9e9e8f13mr3404046f8f.22.1774610280282; Fri, 27 Mar 2026 04:18:00 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 61/65] hw/arm/virt: Advertise GICv5 in the DTB Date: Fri, 27 Mar 2026 11:16:56 +0000 Message-ID: <20260327111700.795099-62-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610615555158500 Content-Type: text/plain; charset="utf-8" Advertise the GICv5 in the DTB. This binding is final as it is in the upstream Linux kernel as: Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/arm/virt.c | 68 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index b6a04f868b..7a34af766a 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -794,6 +794,72 @@ static void create_v2m(VirtMachineState *vms) vms->msi_controller =3D VIRT_MSI_CTRL_GICV2M; } =20 +static void fdt_add_gicv5_node(VirtMachineState *vms) +{ + MachineState *ms =3D MACHINE(vms); + const char *nodename =3D "/intc"; + g_autofree char *irsnodename =3D NULL; + g_autofree uint32_t *cpu_phandles =3D g_new(uint32_t, ms->smp.cpus); + g_autofree uint16_t *iaffids =3D g_new(uint16_t, ms->smp.cpus); + + vms->gic_phandle =3D qemu_fdt_alloc_phandle(ms->fdt); + qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phand= le); + + qemu_fdt_add_subnode(ms->fdt, nodename); + qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle); + qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "arm,gic-v5"); + qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); + qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); + qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); + qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); + + /* The IRS node is a child of the top level /intc node */ + irsnodename =3D g_strdup_printf("%s/irs@%" PRIx64, + nodename, + vms->memmap[VIRT_GICV5_IRS_NS].base); + qemu_fdt_add_subnode(ms->fdt, irsnodename); + qemu_fdt_setprop_string(ms->fdt, irsnodename, "compatible", + "arm,gic-v5-irs"); + /* + * "reg-names" describes the frames whose address/size is in "reg"; + * at the moment we have only the NS config register frame. + */ + qemu_fdt_setprop_string(ms->fdt, irsnodename, "reg-names", "ns-config"= ); + qemu_fdt_setprop_sized_cells(ms->fdt, irsnodename, "reg", + 2, vms->memmap[VIRT_GICV5_IRS_NS].base, + 2, vms->memmap[VIRT_GICV5_IRS_NS].size); + qemu_fdt_setprop_cell(ms->fdt, irsnodename, "#address-cells", 0x2); + qemu_fdt_setprop_cell(ms->fdt, irsnodename, "#size-cells", 0x2); + qemu_fdt_setprop(ms->fdt, irsnodename, "ranges", NULL, 0); + + /* + * The "cpus" property is an array of phandles to the CPUs, and + * "iaffids" is an array of uint16 IAFFIDs. For virt, our IAFFIDs + * are the CPU indexes. This function is called after + * fdt_add_cpu_nodes(), which allocates the cpu_phandles array. + */ + assert(vms->cpu_phandles); + for (int i =3D 0; i < ms->smp.cpus; i++) { + /* + * We have to byteswap each element here because we're setting the + * whole property value at once as a lump of raw data, not via a + * helper like qemu_fdt_setprop_cell() that does the swapping for = us. + */ + cpu_phandles[i] =3D cpu_to_be32(vms->cpu_phandles[i]); + iaffids[i] =3D cpu_to_be16(i); + } + qemu_fdt_setprop(ms->fdt, irsnodename, "cpus", cpu_phandles, + ms->smp.cpus * sizeof(*cpu_phandles)); + qemu_fdt_setprop(ms->fdt, irsnodename, "arm,iaffids", iaffids, + ms->smp.cpus * sizeof(*iaffids)); + + /* + * When we implement the GICv5 IRS, it gets a DTB node which is a + * child of the IRS node. + */ +} + static void create_gicv5(VirtMachineState *vms, MemoryRegion *mem) { MachineState *ms =3D MACHINE(vms); @@ -835,6 +901,8 @@ static void create_gicv5(VirtMachineState *vms, MemoryR= egion *mem) * that information is communicated directly between a GICv5 IRS and * the GICv5 CPU interface via our equivalent of the stream protocol. */ + + fdt_add_gicv5_node(vms); } =20 /* --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610630; cv=none; d=zohomail.com; s=zohoarc; b=O83UM2po2i9tEJFKPMA9muHP7iehRnrP9X2BSatipkhVjKBVHV5CDQptWncCEh2IpW86Bne2vQ5RvvwBRjhZdRuTc0QwCUAwO95ZJOZAB1dklyYXQFEjWjm9jB4TSzvn9Vdmxa29H0VXy2IHad3tsZWwtxumS/tfzSg20/L1SGk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610630; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ji4M7/zlXLPLxa6vnn4WlUzf8phK32eQHNKPiB6p3iM=; b=KooNsDt+RX2CxAntSi8NuSpUD5Qu4dJ3+iigBnhVD3UKYLdXSOqx1E7G86HtHtV0EVAdgyDAfUEjdToXfFLg9x2JQt67X40t68nYHFSBTDJMVVDCqlWEylBV8NW/OMupSYUu9eSwhmI4dQSFiDAbmoe0LItCfbQjmzTh0cDXMPY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610630426838.1408273244595; Fri, 27 Mar 2026 04:23:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65Du-0002HY-Mr; Fri, 27 Mar 2026 07:19:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65CY-0007aI-R6 for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:18:07 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65CV-0000HU-9Q for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:18:06 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-43b3d9d0695so1384743f8f.0 for ; Fri, 27 Mar 2026 04:18:02 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.18.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:18:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610281; x=1775215081; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ji4M7/zlXLPLxa6vnn4WlUzf8phK32eQHNKPiB6p3iM=; b=Gzb8LvQskAVU9rQmNYqnAXX/hHYLAYqNSyrzPD6LhpQtjEBpW6CHVe9kpSuwM4HZpl PFf1kRukH+Id/DH2OyG30Cz4z/xV5M/rZgjnw9LZEUM06IWbcEryLW3Ge6ztfAdvt4fv o0HmPSlAqExPpfx5Be1EPKKcerzKtg3p1AlwTBnw/eRJQ1sPpdRJJAtMiw0pbSF3D7oO AByXvaiEVKR7VkX9WZtudqxbFf6VksxYeBGt8gT7ddnQWhp7QGg6djN1eBKzVkn9I6D8 ck1m3ew7vJXauJQXD5wFJfPgEeIaGlBJ56stjysvNb0BCbr+6iKOM0ks2ACKB9zB/QdH KsVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610281; x=1775215081; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=ji4M7/zlXLPLxa6vnn4WlUzf8phK32eQHNKPiB6p3iM=; b=bS0Tk61Pw4DQWC4cst5aTCGs0jwP5ow5+GQcDkc58GKVp8WmEIvGg4dtVXSB8MCmtj 9Q6Din7kTSgoGAJO9q3s2EDIHcUVnu0rt7k8+2M+tX3hilVJLB6hi9Ca+9p0cpnVvzK1 p0HW3Ta4iMM++fU1S27Y5C8zuF1evjRFUbPOicmvNCrMvUjjUgTsbWElCBi/k6kcxWNX VpAKJcCiKD59dSGkXL7psViUsrrUa6TuyYVfQ+SMHkh2fqWR599ORxIP1+0/V+C9vF08 lzOAikNyYWN1WmehJM0T4s4Qxg9QS2y8NXxFsYDtMEXd4zkYNsEuCy0HCREasHguYxpk gACQ== X-Forwarded-Encrypted: i=1; AJvYcCUfW9MXZzTPgJbrdBuS3c3dp1l3HUkGcizO2rfr7ggRKu/6irAm19jr3Op28tuy5T7t1/AN508kNuyZ@nongnu.org X-Gm-Message-State: AOJu0YzXRMUKZjSdr8DEF5F9TXF92haESV5pSU/GII8dZAmmQnrivYEV NNm8m25ZlmshqjAWSjm7dLDz5HYJOQGkEFcraKS7FRLsycuO7Yn6f49a41r89eAlZKM= X-Gm-Gg: ATEYQzw9T2J9u4co30sejut47H4XeO0lJQyrP/THz3AuHY7Qe+Ism1uAx8CuRNRLjv4 rPYwHwDebGHJJaYJFjv3M+bmQzaTl8dlPIytFBeTemltEOcV4XYrUxjdl4SYJGOBX6gJqw/H+Ad ns+vrdOidOKrZWnGApdideKExty2bB9sT33W9vUJe4o7HKTNGyKvCRQtovCRINy91vlYTa622ak KVIZRLRXOSmMHTDCyIieqDbUJ5tR7W7wWLCyTn/wGORpWS3GEBmJeK7SME+8YImt6Gk2Ibf/MNY GB4BLjMMo3BwNobfat/dmA9gtOfTyCH7Csikv2OauTjoAcnoeJMT6EaGHUAZHTmoauaJsbQHJhs CCChrJr/6K+97JvK2j0t/zBoGeRbAU0jtZyKUjPStqtrz/X0iiXYslnbyUVGyeBSuR9x7EnoG/Q B96BnLamAEyoqH9pwnKBi2dhrdaLrC7ISfu9y5vN8e7vfnu+Lfjn7PITD/HL4hs9PN0+w88I3kD McqdubIVmPR0DKwfkQVw5MvtmaUET/nmKC/sMeMPQ== X-Received: by 2002:a05:6000:410b:b0:439:cc5e:a6d5 with SMTP id ffacd0b85a97d-43b97a62151mr5327271f8f.23.1774610281203; Fri, 27 Mar 2026 04:18:01 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 62/65] hw/arm/virt: Handle GICv5 in interrupt bindings for PPIs Date: Fri, 27 Mar 2026 11:16:57 +0000 Message-ID: <20260327111700.795099-63-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610631612158500 Content-Type: text/plain; charset="utf-8" The GICv5 devicetree binding specifies the "interrupts" property differently to GICv2 and GICv3 for PPIs: the first field is the architectural INTID.TYPE, and the second is the architectural INTID.ID. (The third field defining the level/edge trigger mode has the same values for GICv5 as it did for the older GICs.) In the places in the virt board where we wire up PPIs (the timer and the PMU), handle the GICv5: * use the architectural constant GICV5_PPI for the type * use the architected GICv5 PPI numbers for the interrupt sources (which differ from the old ones and don't need to be adjusted via INTID_TO_PPI()) * leave the irqflags as-is Add some commentary in our include/hw/arm/fdt.h file about what the the constants defined there are valid for. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/arm/virt.c | 23 +++++++++++++++++++---- include/hw/arm/fdt.h | 10 ++++++++++ 2 files changed, 29 insertions(+), 4 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 7a34af766a..bc49cf244f 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -420,7 +420,15 @@ static void fdt_add_timer_nodes(const VirtMachineState= *vms) "arm,armv7-timer"); } qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0); - if (vms->ns_el2_virt_timer_irq) { + if (vms->gic_version =3D=3D VIRT_GIC_VERSION_5) { + /* The GICv5 architects the PPI numbers differently */ + qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", + GICV5_PPI, GICV5_PPI_CNTPS, irqflags, + GICV5_PPI, GICV5_PPI_CNTP, irqflags, + GICV5_PPI, GICV5_PPI_CNTV, irqflags, + GICV5_PPI, GICV5_PPI_CNTHP, irqflags, + GICV5_PPI, GICV5_PPI_CNTHV, irqflags); + } else if (vms->ns_el2_virt_timer_irq) { qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", GIC_FDT_IRQ_TYPE_PPI, INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflag= s, @@ -699,11 +707,18 @@ static void fdt_add_pmu_nodes(const VirtMachineState = *vms) qemu_fdt_add_subnode(ms->fdt, "/pmu"); if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { const char compat[] =3D "arm,armv8-pmuv3"; + qemu_fdt_setprop(ms->fdt, "/pmu", "compatible", compat, sizeof(compat)); - qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts", - GIC_FDT_IRQ_TYPE_PPI, - INTID_TO_PPI(VIRTUAL_PMU_IRQ), irqflags); + if (vms->gic_version =3D=3D VIRT_GIC_VERSION_5) { + qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts", + GICV5_PPI, GICV5_PPI_PMUIRQ, irqflags); + } else { + qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts", + GIC_FDT_IRQ_TYPE_PPI, + INTID_TO_PPI(VIRTUAL_PMU_IRQ), + irqflags); + } } } =20 diff --git a/include/hw/arm/fdt.h b/include/hw/arm/fdt.h index c3d5015013..995652c27a 100644 --- a/include/hw/arm/fdt.h +++ b/include/hw/arm/fdt.h @@ -20,9 +20,19 @@ #ifndef QEMU_ARM_FDT_H #define QEMU_ARM_FDT_H =20 +/* + * These are for GICv2/v3/v4 only; GICv5 encodes the interrupt type in + * the DTB "interrupts" properties differently, using constants that + * match the architectural INTID.Type. In QEMU those are available as + * the GICV5_PPI and GICV5_SPI enum values in arm_gicv5_types.h. + */ #define GIC_FDT_IRQ_TYPE_SPI 0 #define GIC_FDT_IRQ_TYPE_PPI 1 =20 +/* + * The trigger type/level field in the DTB "interrupts" property has + * the same encoding for GICv2/v3/v4 and v5. + */ #define GIC_FDT_IRQ_FLAGS_EDGE_LO_HI 1 #define GIC_FDT_IRQ_FLAGS_EDGE_HI_LO 2 #define GIC_FDT_IRQ_FLAGS_LEVEL_HI 4 --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610431; cv=none; d=zohomail.com; s=zohoarc; b=R04TLmgzXYuImJ2PXZDKVUaRYlKcmkxy1LZgWYN8p7aOf3sYJhy6KuNOQcDQd1g0p1Ft7/73CNuQI5TlOPugF6cGUotMEvW0Urv3jZ/WMnbdITXFavQP7SQhi3DR2cuhLo7XbWTbSGDcBIxL+Fq0smslHkU/McVY5aeNAfPLJw4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610431; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qVpl4q4Ew+AJPdH2wb74AVCkix8tQh3kXY3l2KghFQY=; b=k/beo5oDkdHczTc1Gt+zlyfhK4SM3f2+JbgsxmFfCw/fL+IWyHeZS61zLYN1HAiUa4m8kNPQqumW2hTZR3Tbot1fVlL/XULHvbYwfo8njd6R4+kELZfCvwUordUiG7JhgtEgH6Rli2sbSfHNvWEsBv5Gc8fpk+JgEFlhBJfdGQs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610431554969.9346638384465; Fri, 27 Mar 2026 04:20:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65EB-0003Ed-Ii; Fri, 27 Mar 2026 07:19:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65Cb-0007qY-TD for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:18:09 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65CX-0000Hh-Sf for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:18:09 -0400 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-439b7c2788dso1186502f8f.1 for ; Fri, 27 Mar 2026 04:18:03 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.18.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 04:18:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774610282; x=1775215082; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qVpl4q4Ew+AJPdH2wb74AVCkix8tQh3kXY3l2KghFQY=; b=W1BOGURdIr9YoqmLB/mtIQnBr9YBAhED60FgNcYiV/83dGa6RPMDRmFZcAKVrK9cDK F8v9HQAIpTt0B8qembESSDYFMGjpNdNkFyWRrmRoyNePXAX1ofc621IleNfke8sv7QfC BDq4cqmZpdxhOZhTXJ9BY6U627G1St0sZBPkSO8LAxIPj6bf9SbQislI7BV3SjXGQROq CImRCxhKcts1H7pV9BYowadPxq9NDMY3oQUzK+6bUGlANN/GUQ9oQqfxxTw0V4+6JBcI EbnPjHID0Fl8YdD9LSopYb/V99T9U4GfmBoF3C2ye/HBiYBgmh4DS6jkA/A7JC1WZmEh +LXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774610282; x=1775215082; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=qVpl4q4Ew+AJPdH2wb74AVCkix8tQh3kXY3l2KghFQY=; b=Bz+oHJztTZl9Y2sVIVpcH0TPN6qBas/N/v8MhdweQFm3QKAoWIFeIdVwjMAAsoj7+2 uGuq/bTeP8O558C2rGa7dbnSbAnJnz7ZWEpwqz3Pw+euYR8xBbMQmZ9pU2qmSKhExha6 vyt3BL9WN0JlrvwHu279QhESzYCiTBbdBOIMG1wETfNh2BMTK5vDULbVYySxM3cHkrFJ ctzJqaKD2/n200toO8486SDGOuB1q00oZQm2eCYRK0BrU7kAfzg13qfHD39wWPZgJPix O3XbO/kMQTmjEyWi2eCDwKdLY7rwUndNCdPVUM1K1VbD/StZbo/g+gRZsNobPXDKf9Pv 7TQQ== X-Forwarded-Encrypted: i=1; AJvYcCXkYg11bX7DEYDoc6x4W/RBGRoXLZVu5jRio4SIO8beF2qc/fbgowbAGA8Ke/h9opRAuDLxTk+HDZ/h@nongnu.org X-Gm-Message-State: AOJu0YznaO0u8sovkZkVgXWJ6FB1n3Ww6Ac94L3Sh3GFQ0HDsVs09IQK TbzK4Y+7TkXRiNfxXtIt9mtCsOtBvgFwJuUGD+vn1QHc9McOpIuL/jhLIA1a+bKFr5nIQYWmPrB ytZ7D7FE= X-Gm-Gg: ATEYQzwe/jFuK+PK/Umb9tsjoB5jVDvkspOS4P82MMcVscm2uoCtqLIGHLzY/KNFye9 gPhkZbAZv7M7a6grneBJ1E6OvPPMlNueq1sZPrWZxLv233OGhyPxeHNSlSMFgubhrlqVB4dYqi6 xZsVI/91RtxF1Z0ojmi/06CKL3X5R9MXma/XJsRxKuSU9p97yA5gMLqq8RpXJJNoHJtsoLZjNxR u/dO8FzHPAYTpjL0iBcRLuMyhWnFhmqDglodgD06e+4jyPgMMjM9cwP7W3RDwPRegyFf5bMP8ep cmAtbC/fvHhDihhapo0agIb1x0eGThpxATvWzBEz0vyX+7LnNS9iw4eARTDGPk3U0DFNhw0qEEw gdioTbbGhYUTkaeOznpYJZpSa8X75zmn9Jhw2XeSG9HraqZIr3xinJh8SLmXOR10dD0c8QAwXUm 785MJfgXY6JxSDfPlnQA683X4PzCpbPAu22Uy0yFrOoddaefGJxy3H7ezBMrlpSVVyhj5kMFEdr 4rbhjaxOCqjdRMeKZzP8nTjLJVsQqQ= X-Received: by 2002:a05:6000:4212:b0:439:cb10:dfcd with SMTP id ffacd0b85a97d-43b9ea623eamr3195847f8f.39.1774610282128; Fri, 27 Mar 2026 04:18:02 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jonathan Cameron Subject: [PATCH v2 63/65] hw/arm/virt: Use correct interrupt type for GICv5 SPIs in the DTB Date: Fri, 27 Mar 2026 11:16:58 +0000 Message-ID: <20260327111700.795099-64-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260327111700.795099-1-peter.maydell@linaro.org> References: <20260327111700.795099-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774610435055158500 Content-Type: text/plain; charset="utf-8" The GICv5 devicetree binding specifies that the "interrupts" property for devices connected to it should use the architectural INTID.TYPE values to specify whether the interrupt is an SPI, LPI or PPI. This is different to the GICv2 and GICv3, so instead of hardcoding the GIC_FDT_IRQ_TYPE_SPI constant when we create "interrupts" bindings, create a new function gic_fdt_irq_type_spi() that returns the right value for the interrupt controller in use. For SPIs, the INTID.ID and the trigger-mode fields of the "interrupts" property remain the same for GICv5 and the older GIC versions. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/arm/virt.c | 29 ++++++++++++++++++++--------- 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index bc49cf244f..15d833ad8f 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -295,6 +295,16 @@ static bool ns_el2_virt_timer_present(void) arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= ); } =20 +/* + * The correct value to use in a DTB "interrupts" property for an SPI + * depends on the GIC version. + */ +static int gic_fdt_irq_type_spi(const VirtMachineState *vms) +{ + return vms->gic_version =3D=3D VIRT_GIC_VERSION_5 ? + GICV5_SPI : GIC_FDT_IRQ_TYPE_SPI; +} + static void create_fdt(VirtMachineState *vms) { MachineState *ms =3D MACHINE(vms); @@ -1183,7 +1193,7 @@ static void create_uart(const VirtMachineState *vms, = int uart, qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", - GIC_FDT_IRQ_TYPE_SPI, irq, + gic_fdt_irq_type_spi(vms), irq, GIC_FDT_IRQ_FLAGS_LEVEL_HI); qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks", vms->clock_phandle, vms->clock_phandle); @@ -1225,7 +1235,7 @@ static void create_rtc(const VirtMachineState *vms) qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", - GIC_FDT_IRQ_TYPE_SPI, irq, + gic_fdt_irq_type_spi(vms), irq, GIC_FDT_IRQ_FLAGS_LEVEL_HI); qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); @@ -1344,7 +1354,7 @@ static void create_gpio_devices(const VirtMachineStat= e *vms, int gpio, qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2); qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0); qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", - GIC_FDT_IRQ_TYPE_SPI, irq, + gic_fdt_irq_type_spi(vms), irq, GIC_FDT_IRQ_FLAGS_LEVEL_HI); qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); @@ -1425,7 +1435,7 @@ static void create_virtio_devices(const VirtMachineSt= ate *vms) qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", - GIC_FDT_IRQ_TYPE_SPI, irq, + gic_fdt_irq_type_spi(vms), irq, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); g_free(nodename); @@ -1625,10 +1635,11 @@ static void create_pcie_irq_map(const MachineState = *ms, int devfn, pin; uint32_t full_irq_map[4 * 4 * 10] =3D { 0 }; uint32_t *irq_map =3D full_irq_map; + const VirtMachineState *vms =3D VIRT_MACHINE(ms); =20 for (devfn =3D 0; devfn <=3D 0x18; devfn +=3D 0x8) { for (pin =3D 0; pin < 4; pin++) { - int irq_type =3D GIC_FDT_IRQ_TYPE_SPI; + int irq_type =3D gic_fdt_irq_type_spi(vms); int irq_nr =3D first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_= PINS); int irq_level =3D GIC_FDT_IRQ_FLAGS_LEVEL_HI; int i; @@ -1669,10 +1680,10 @@ static void create_smmuv3_dt_bindings(const VirtMac= hineState *vms, hwaddr base, qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); =20 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", - GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, - GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, - GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, - GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); + gic_fdt_irq_type_spi(vms), irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_= HI, + gic_fdt_irq_type_spi(vms), irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_= HI, + gic_fdt_irq_type_spi(vms), irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_= HI, + gic_fdt_irq_type_spi(vms), irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_= HI); =20 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, sizeof(irq_names)); --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/arm/virt.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 15d833ad8f..0aff58bc3c 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2675,6 +2675,14 @@ static void machvirt_init(MachineState *machine) object_property_set_bool(cpuobj, "lpa2", false, NULL); } =20 + if (vms->gic_version =3D=3D VIRT_GIC_VERSION_5) { + if (!object_property_find(cpuobj, "has_gcie")) { + error_report("Using GICv5 but guest CPU does not support i= t"); + exit(1); + } + object_property_set_bool(cpuobj, "has_gcie", true, NULL); + } + if (object_property_find(cpuobj, "reset-cbar")) { object_property_set_int(cpuobj, "reset-cbar", vms->memmap[VIRT_CPUPERIPHS].base, --=20 2.43.0 From nobody Thu Apr 2 17:18:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774610731; cv=none; d=zohomail.com; s=zohoarc; b=IJHCMlMXOLzWKZvd85fwkDK2WKla9oYzFdqnVTzGzqawIt5Iluzg7tc31U5+4REgj5OQEVkPKmWJEkk4jM00vb3KLLq6D8RCJSGTQALcUZoxOMv1mcNx0xc9pDW6D61biQz5pApaowvO587Izg7yioUdQy4sD5jebdmbMzmpiA0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774610731; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=9Sc6A8mUH5H33CEhbJhf4m2nOob0B+CIV382Sacc+zU=; b=ijIkZEsXpU3Tw4SxtZ/oOygbTOEBEQ+Am248WNfcJ9upNIAO34CNxK/9oDOmLYaVHrJmrUyNa5gEYCOONXlqUTdnFI5IefnZpjftxmIkIWEL18evndEktPSpIxESAYn1AgG/C1Wg8c6M5EK/tvun9dQYpweLTkNyaTs3sGK/Pvo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774610731397261.1214338297191; Fri, 27 Mar 2026 04:25:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65Dq-0001v1-Q7; Fri, 27 Mar 2026 07:19:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65Cb-0007qV-Q1 for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:18:09 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w65CX-0000JY-Re for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:18:09 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-43b7481f9d3so1157578f8f.3 for ; Fri, 27 Mar 2026 04:18:04 -0700 (PDT) Received: from lanath.. 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The 'x-' prefix indicates that the emulation is still in an "experimental" state as far as QEMU is concerned; the documentation describes what "experimental" means for the user and what parts are not yet implemented. We do not make 'gic-version=3Dmax' enable GICv5 here because: * the GICv5 architectural spec is still at the EAC level and could have minor changes between now and its final version; only users who specifically want to start working with the GICv5 should select it * QEMU's implementation here is still not fully featured, and selecting it instead of GICv3 will mean losing functionality such as MSIs * the GICv5 is not backwards compatible with the GICv3/GICv4 for system software, so silently "upgrading" an existing command line to GICv5 is just going to break existing guest kernels The last one in particular suggests that even when the emulation moves out of "experimental" status we will probably not want to change "max". Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- docs/system/arm/virt.rst | 19 +++++++++++++++++++ hw/arm/virt.c | 11 ++++++++--- 2 files changed, 27 insertions(+), 3 deletions(-) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index fbe3ca9e12..f811e662d6 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -161,6 +161,25 @@ gic-version GICv3. This allows up to 512 CPUs. ``4`` GICv4. Requires ``virtualization`` to be ``on``; allows up to 317 CPUs. + ``x-5`` + GICv5 (experimental). This is an experimental emulation of the GICv5, + based on the EAC release of the GICv5 architecture specification. + Experimental means: + + - guest-visible behaviour may change when the final version of + the specification is released and QEMU implements it + - migration support is not yet implemented + - the GICv5 is not exposed to the guest via ACPI tables, only via DTB + - the way the interrupt controller is exposed to the guest and the + command line syntax for enabling it may change + + The current implementation supports only an EL1 guest (no EL2 or + EL3 and no Realm support), and does not implement the ITS (no + MSI support). + + Note that as the GICv5 is an Armv9 feature, enabling it will + automatically disable support for AArch32 at all exception levels + except for EL0 (userspace). ``host`` Use the same GIC version the host provides, when using KVM ``max`` diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 0aff58bc3c..0064491063 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3223,6 +3223,9 @@ static char *virt_get_gic_version(Object *obj, Error = **errp) const char *val; =20 switch (vms->gic_version) { + case VIRT_GIC_VERSION_5: + val =3D "x-5"; + break; case VIRT_GIC_VERSION_4: val =3D "4"; break; @@ -3240,7 +3243,9 @@ static void virt_set_gic_version(Object *obj, const c= har *value, Error **errp) { VirtMachineState *vms =3D VIRT_MACHINE(obj); =20 - if (!strcmp(value, "4")) { + if (!strcmp(value, "x-5")) { + vms->gic_version =3D VIRT_GIC_VERSION_5; + } else if (!strcmp(value, "4")) { vms->gic_version =3D VIRT_GIC_VERSION_4; } else if (!strcmp(value, "3")) { vms->gic_version =3D VIRT_GIC_VERSION_3; @@ -3252,7 +3257,7 @@ static void virt_set_gic_version(Object *obj, const c= har *value, Error **errp) vms->gic_version =3D VIRT_GIC_VERSION_MAX; /* Will probe later */ } else { error_setg(errp, "Invalid gic-version value"); - error_append_hint(errp, "Valid values are 2, 3, 4, host, and max.\= n"); + error_append_hint(errp, "Valid values are 2, 3, 4, x-5, host, and = max.\n"); } } =20 @@ -3827,7 +3832,7 @@ static void virt_machine_class_init(ObjectClass *oc, = const void *data) virt_set_gic_version); object_class_property_set_description(oc, "gic-version", "Set GIC version. " - "Valid values are 2, 3, 4, host = and max"); + "Valid values are 2, 3, 4, x-5, = host and max"); =20 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_io= mmu); object_class_property_set_description(oc, "iommu", --=20 2.43.0