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a="75719908" X-IronPort-AV: E=Sophos;i="6.23,143,1770624000"; d="scan'208";a="75719908" X-CSE-ConnectionGUID: AWgkCBLDTRubp9msX1uCow== X-CSE-MsgGUID: FCal3sZ8QWKziI/LNLR9+A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,143,1770624000"; d="scan'208";a="221874391" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [PATCH 4/5] intel_iommu_accel: Accept PRQ response for passthrough device Date: Thu, 26 Mar 2026 22:52:26 -0400 Message-ID: <20260327025228.474257-5-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260327025228.474257-1-zhenzhong.duan@intel.com> References: <20260327025228.474257-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1774580020098158500 Content-Type: text/plain; charset="utf-8" Propagate guest's PRQ response to host by writing to fault_fd. Create a new VTDPRQEntry to cache cookie for each fault group, this cookie is used to mark the fault group on host side. Signed-off-by: Zhenzhong Duan Reviewed-by: Clement Mathieu--Drif --- hw/i386/intel_iommu_accel.h | 14 ++++++++ include/hw/i386/intel_iommu.h | 6 ++++ hw/i386/intel_iommu.c | 4 +++ hw/i386/intel_iommu_accel.c | 65 +++++++++++++++++++++++++++++++++++ hw/i386/trace-events | 1 + 5 files changed, 90 insertions(+) diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h index 10e6ee5722..b46c7126f7 100644 --- a/hw/i386/intel_iommu_accel.h +++ b/hw/i386/intel_iommu_accel.h @@ -19,6 +19,9 @@ typedef struct VTDAccelPASIDCacheEntry { uint32_t fs_hwpt_id; uint32_t fault_id; int fault_fd; + QLIST_HEAD(, VTDPRQEntry) vtd_prq_list; + IOMMUPRINotifier pri_notifier_entry; + IOMMUPRINotifier *pri_notifier; QLIST_ENTRY(VTDAccelPASIDCacheEntry) next; } VTDAccelPASIDCacheEntry; =20 @@ -31,6 +34,9 @@ void vtd_flush_host_piotlb_all_accel(IntelIOMMUState *s, = uint16_t domain_id, uint64_t npages, bool ih); void vtd_pasid_cache_sync_accel(IntelIOMMUState *s, VTDPASIDCacheInfo *pc_= info); void vtd_pasid_cache_reset_accel(IntelIOMMUState *s); +bool vtd_propagate_page_group_response_accel(IntelIOMMUState *s, + uint16_t rid, uint32_t pasid, + IOMMUPRIResponse *response); void vtd_iommu_ops_update_accel(PCIIOMMUOps *ops); #else static inline bool vtd_check_hiod_accel(IntelIOMMUState *s, @@ -69,6 +75,14 @@ static inline void vtd_pasid_cache_reset_accel(IntelIOMM= UState *s) { } =20 +static inline +bool vtd_propagate_page_group_response_accel(IntelIOMMUState *s, + uint16_t rid, uint32_t pasid, + IOMMUPRIResponse *response) +{ + return false; +} + static inline void vtd_iommu_ops_update_accel(PCIIOMMUOps *ops) { } diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 1842ba5840..5d44eac0ed 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -100,6 +100,12 @@ typedef struct VTDPASIDCacheEntry { bool valid; } VTDPASIDCacheEntry; =20 +typedef struct VTDPRQEntry { + uint32_t grpid; + uint32_t cookie; + QLIST_ENTRY(VTDPRQEntry) next; +} VTDPRQEntry; + struct VTDAddressSpace { PCIBus *bus; uint8_t devfn; diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 96b4102ab9..d670a0377b 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3390,6 +3390,10 @@ static bool vtd_process_page_group_response_desc(Int= elIOMMUState *s, response.response_code =3D IOMMU_PRI_RESP_FAILURE; } =20 + if (vtd_propagate_page_group_response_accel(s, rid, pasid, &response))= { + return true; + } + if (vtd_dev_as->pri_notifier) { vtd_dev_as->pri_notifier->notify(vtd_dev_as->pri_notifier, &respon= se); } diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index 0fce62ff75..44af534c55 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -102,6 +102,30 @@ VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSp= ace *as) return NULL; } =20 +bool vtd_propagate_page_group_response_accel(IntelIOMMUState *s, + uint16_t rid, uint32_t pasid, + IOMMUPRIResponse *response) +{ + VTDAddressSpace *vtd_as =3D vtd_get_as_by_sid(s, rid); + VTDAccelPASIDCacheEntry *vtd_pce; + VTDHostIOMMUDevice *vtd_hiod =3D vtd_find_hiod_iommufd(vtd_as); + + if (!vtd_hiod) { + return false; + } + + QLIST_FOREACH(vtd_pce, &vtd_hiod->pasid_cache_list, next) { + if (vtd_pce->pasid =3D=3D pasid) { + if (vtd_pce->pri_notifier) { + vtd_pce->pri_notifier->notify(vtd_pce->pri_notifier, respo= nse); + } + return true; + } + } + + return false; +} + static void vtd_prq_report_fault(VTDAccelPASIDCacheEntry *vtd_pce, struct iommu_hwpt_pgfault *fault, int cnt) { @@ -117,6 +141,13 @@ static void vtd_prq_report_fault(VTDAccelPASIDCacheEnt= ry *vtd_pce, fault->addr, last_page, fault->grpid, fault->perm & IOMMU_PGFAULT_PERM_READ, fault->perm & IOMMU_PGFAULT_PERM_WRITE= ); + if (last_page) { + VTDPRQEntry *prqe =3D g_malloc0(sizeof(*prqe)); + + prqe->grpid =3D fault->grpid; + prqe->cookie =3D fault->cookie; + QLIST_INSERT_HEAD(&vtd_pce->vtd_prq_list, prqe, next); + } } } =20 @@ -150,6 +181,36 @@ static void vtd_prq_read_fault(void *opaque) vtd_prq_report_fault(vtd_pce, fault, bytes / sizeof(fault[0])); } =20 +static void vtd_prq_response_notify(struct IOMMUPRINotifier *notifier, + IOMMUPRIResponse *response) +{ + VTDAccelPASIDCacheEntry *vtd_pce =3D + container_of(notifier, VTDAccelPASIDCacheEntry, pri_notifier_entry= ); + uint32_t id =3D vtd_pce->fault_id, fd =3D vtd_pce->fault_fd; + struct iommu_hwpt_page_response resp; + VTDPRQEntry *prqe, *tmp; + ssize_t bytes; + + QLIST_FOREACH_SAFE(prqe, &vtd_pce->vtd_prq_list, next, tmp) { + if (prqe->grpid !=3D response->prgi) { + continue; + } + + resp.cookie =3D prqe->cookie; + resp.code =3D response->response_code; + bytes =3D write(fd, &resp, sizeof(resp)); + trace_vtd_prq_response_notify(id, fd, resp.cookie, resp.code, byte= s); + if (bytes < 0) { + error_report_once("FAULTQ(id %u): write failed " + "[cookie 0x%x code 0x%x] (%m)", + id, resp.cookie, resp.code); + } + + QLIST_REMOVE(prqe, next); + g_free(prqe); + } +} + static void vtd_destroy_fs_faultq(VTDHostIOMMUDevice *vtd_hiod, uint32_t fault_id, uint32_t fault_fd) { @@ -213,6 +274,7 @@ static void vtd_destroy_old_fs_faultq(VTDHostIOMMUDevic= e *vtd_hiod, return; } =20 + vtd_pce->pri_notifier =3D NULL; qemu_set_fd_handler(vtd_pce->fault_fd, NULL, NULL, NULL); vtd_destroy_fs_faultq(vtd_hiod, vtd_pce->fault_id, vtd_pce->fault_fd); vtd_pce->fault_id =3D 0; @@ -228,6 +290,8 @@ static void vtd_setup_fs_faultq(VTDAccelPASIDCacheEntry= *vtd_pce, =20 vtd_pce->fault_id =3D fault_id; vtd_pce->fault_fd =3D fault_fd; + vtd_pce->pri_notifier_entry.notify =3D vtd_prq_response_notify; + vtd_pce->pri_notifier =3D &vtd_pce->pri_notifier_entry; qemu_set_fd_handler(fault_fd, vtd_prq_read_fault, NULL, vtd_pce); } =20 @@ -492,6 +556,7 @@ static void vtd_accel_fill_pc(VTDHostIOMMUDevice *vtd_h= iod, uint32_t pasid, vtd_pce->vtd_hiod =3D vtd_hiod; vtd_pce->pasid =3D pasid; vtd_pce->pasid_entry =3D *pe; + QLIST_INIT(&vtd_pce->vtd_prq_list); QLIST_INSERT_HEAD(&vtd_hiod->pasid_cache_list, vtd_pce, next); =20 if (!vtd_device_attach_iommufd(vtd_pce, &local_err)) { diff --git a/hw/i386/trace-events b/hw/i386/trace-events index bf139338f7..52dab0b508 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -78,6 +78,7 @@ vtd_device_attach_hwpt(uint32_t dev_id, uint32_t pasid, u= int32_t hwpt_id, int re vtd_device_detach_hwpt(uint32_t dev_id, uint32_t pasid, int ret) "dev_id %= d pasid %d ret: %d" vtd_device_reattach_def_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwp= t_id, int ret) "dev_id %d pasid %d hwpt_id %d, ret: %d" vtd_prq_read_fault(uint32_t fault_id, uint32_t fault_fd, ssize_t bytes) "f= ault_id %d fault_fd %d ret: %zd" +vtd_prq_response_notify(uint32_t fault_id, uint32_t fault_fd, uint32_t coo= kie, uint32_t code, ssize_t bytes) "fault_id %d fault_fd %d cookie %d code = %d ret: %zd" =20 # amd_iommu.c amdvi_evntlog_fail(uint64_t addr, uint32_t head) "error: fail to write at = addr 0x%"PRIx64" + offset 0x%"PRIx32 --=20 2.47.3