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Thu, 26 Mar 2026 22:52:44 -0400 Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2026 19:52:42 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2026 19:52:38 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1774579963; x=1806115963; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=w5vSF8KYox0CHnA35X/HlNBRury1CbOEj6ktSvWYxDg=; b=M1paV1vQkF+G/CDgyTbT1vn/NSBmRnQc8lAnTnYaqQLXEyHsFByWo0UH 2oDGqIb+PuOoGEt7BPibqb/WIUpKxK4NvJFnGjIrSiDfmReVF4qgZSMlF k0KhR0ct1/4s0YISoXaIhmcXpKFN0DBnsNcbQqnj8sqw41EzPX5nsD07z udJQSeZbr6iQoQ7NM5yziGWSQItXnF/RkNNZDyZdZvwFxxp+ccNgEHV7W 22SoxOVzzlUn+9Re0aL8ko3SJwKnsOvbidoUWp3RYsrZ/PxxLVMEyg8Mn vvAF3WTOMl13mOCW1We2jZkldAWhWpVJWFnqZ3NqOcKcOP0M1KxK9gfMF Q==; X-CSE-ConnectionGUID: FZ0KGynHSdmlRgIdzW0NbA== X-CSE-MsgGUID: /jCtXBf2SfCaTvyZi6X92g== X-IronPort-AV: E=McAfee;i="6800,10657,11741"; a="75719878" X-IronPort-AV: E=Sophos;i="6.23,143,1770624000"; d="scan'208";a="75719878" X-CSE-ConnectionGUID: KyFET4/UQgmFgo1t+CeniA== X-CSE-MsgGUID: hJ5UlfSaQ/Kwxe02QtYgjg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,143,1770624000"; d="scan'208";a="221874380" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [PATCH 1/5] backends/iommufd: Introduce iommufd_backend_alloc_faultq Date: Thu, 26 Mar 2026 22:52:23 -0400 Message-ID: <20260327025228.474257-2-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260327025228.474257-1-zhenzhong.duan@intel.com> References: <20260327025228.474257-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1774580037871154100 Content-Type: text/plain; charset="utf-8" Add a new helper for IOMMU_FAULT_QUEUE_ALLOC ioctl to allocate a fault handling object which will be used in hwpt allocation. Signed-off-by: Zhenzhong Duan Tested-by: Xudong Hao --- include/system/iommufd.h | 3 +++ backends/iommufd.c | 21 +++++++++++++++++++++ backends/trace-events | 1 + 3 files changed, 25 insertions(+) diff --git a/include/system/iommufd.h b/include/system/iommufd.h index 45a9e87cb0..d4ba8434a5 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -100,6 +100,9 @@ bool iommufd_backend_alloc_veventq(IOMMUFDBackend *be, = uint32_t viommu_id, uint32_t *out_veventq_id, uint32_t *out_veventq_fd, Error **errp); =20 +bool iommufd_backend_alloc_faultq(IOMMUFDBackend *be, uint32_t *fault_id, + uint32_t *fault_fd, Error **errp); + bool iommufd_backend_set_dirty_tracking(IOMMUFDBackend *be, uint32_t hwpt_= id, bool start, Error **errp); bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *be, uint32_t hwpt_id, diff --git a/backends/iommufd.c b/backends/iommufd.c index ab612e4874..9496377a25 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -337,6 +337,27 @@ bool iommufd_backend_alloc_hwpt(IOMMUFDBackend *be, ui= nt32_t dev_id, return true; } =20 +bool iommufd_backend_alloc_faultq(IOMMUFDBackend *be, uint32_t *fault_id, + uint32_t *fault_fd, Error **errp) +{ + int ret, fd =3D be->fd; + struct iommu_fault_alloc cmd =3D { + .size =3D sizeof(cmd), + }; + + ret =3D ioctl(fd, IOMMU_FAULT_QUEUE_ALLOC, &cmd); + trace_iommufd_backend_alloc_faultq(fd, cmd.out_fault_id, cmd.out_fault= _fd, + ret); + if (ret) { + error_setg_errno(errp, errno, "Failed to allocate fault queue"); + return false; + } + + *fault_id =3D cmd.out_fault_id; + *fault_fd =3D cmd.out_fault_fd; + return true; +} + bool iommufd_backend_set_dirty_tracking(IOMMUFDBackend *be, uint32_t hwpt_id, bool start, Error **errp) diff --git a/backends/trace-events b/backends/trace-events index b9365113e7..6820a9939e 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -17,6 +17,7 @@ iommufd_backend_unmap_dma_non_exist(int iommufd, uint32_t= ioas, uint64_t iova, u iommufd_backend_unmap_dma(int iommufd, uint32_t ioas, uint64_t iova, uint6= 4_t size, int ret) " iommufd=3D%d ioas=3D%d iova=3D0x%"PRIx64" size=3D0x%"P= RIx64" (%d)" iommufd_backend_alloc_ioas(int iommufd, uint32_t ioas) " iommufd=3D%d ioas= =3D%d" iommufd_backend_alloc_hwpt(int iommufd, uint32_t dev_id, uint32_t pt_id, u= int32_t flags, uint32_t hwpt_type, uint32_t len, uint64_t data_ptr, uint32_= t out_hwpt_id, int ret) " iommufd=3D%d dev_id=3D%u pt_id=3D%u flags=3D0x%x = hwpt_type=3D%u len=3D%u data_ptr=3D0x%"PRIx64" out_hwpt=3D%u (%d)" +iommufd_backend_alloc_faultq(int iommufd, uint32_t fault_id, uint32_t faul= t_fd, int ret) " iommufd=3D%d fault_id=3D%d fault_fd=3D%d (%d)" iommufd_backend_free_id(int iommufd, uint32_t id, int ret) " iommufd=3D%d = id=3D%d (%d)" iommufd_backend_set_dirty(int iommufd, uint32_t hwpt_id, bool start, int r= et) " iommufd=3D%d hwpt=3D%u enable=3D%d (%d)" iommufd_backend_get_dirty_bitmap(int iommufd, uint32_t hwpt_id, uint64_t i= ova, uint64_t size, uint64_t flags, uint64_t page_size, int ret) " iommufd= =3D%d hwpt=3D%u iova=3D0x%"PRIx64" size=3D0x%"PRIx64" flags=3D0x%"PRIx64" p= age_size=3D0x%"PRIx64" (%d)" --=20 2.47.3 From nobody Thu Apr 2 18:50:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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26 Mar 2026 19:52:45 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2026 19:52:42 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1774579968; x=1806115968; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9of5pivnPhQUXMSB+06b0S6dhtFK7zmVDYOCgP/18KA=; b=RXHcKMo5KoMDqLTPjzQZTqNtdNjfPjFMfzwuoubwLXeS1IdcEdOQEtsi etuz3kobSKXifO8fLwyplB859MQ1R3vc9t4Y0AklOCGxJ51rBkM9EsI1O 3kn8WOtr1Oh2m61zCe0GEaBfr215V+YmQN4KaJNOdnzGTDy4+j4gp63s6 vKkGDTwdl2o0mb8RK6DPALfWL2SIrNKXu5Vjcj8iMhTma5FzyOD6eA3rM FCDkQ9BVxhpiRCc6vJ6v2m9Fa3JUu+qXdZajizYMLLv6mqMOZQnJzxptI 7mNrZAKUiB5q77OwzkbFhNUour+7sT4FGHl6Q+YTptnvcQptzqGt4ODb6 A==; X-CSE-ConnectionGUID: lAqDTJLIQI+MKZjBxHPnLQ== X-CSE-MsgGUID: MjayH4rXTi+CA7C3vg1MKQ== X-IronPort-AV: E=McAfee;i="6800,10657,11741"; a="75719887" X-IronPort-AV: E=Sophos;i="6.23,143,1770624000"; d="scan'208";a="75719887" X-CSE-ConnectionGUID: 1T5l6teDQhOXaTgXMGB6xQ== X-CSE-MsgGUID: 1aLT35MvQT+jNqkaSBk2Yg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,143,1770624000"; d="scan'208";a="221874383" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan , qemu-arm@nongnu.org Subject: [PATCH 2/5] backends/iommufd: Extend iommufd_backend_alloc_hwpt() with fault_id Date: Thu, 26 Mar 2026 22:52:24 -0400 Message-ID: <20260327025228.474257-3-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260327025228.474257-1-zhenzhong.duan@intel.com> References: <20260327025228.474257-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1774580020103158500 Content-Type: text/plain; charset="utf-8" No need to force caller to set IOMMU_HWPT_FAULT_ID_VALID, we take it by checking fault_id nonzero. Signed-off-by: Zhenzhong Duan Tested-by: Xudong Hao --- include/system/iommufd.h | 4 ++-- backends/iommufd.c | 13 +++++++++---- hw/arm/smmuv3-accel.c | 6 +++--- hw/i386/intel_iommu_accel.c | 2 +- hw/vfio/iommufd.c | 2 +- backends/trace-events | 2 +- 6 files changed, 17 insertions(+), 12 deletions(-) diff --git a/include/system/iommufd.h b/include/system/iommufd.h index d4ba8434a5..f753bfaf69 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -85,8 +85,8 @@ bool iommufd_backend_get_device_info(IOMMUFDBackend *be, = uint32_t devid, bool iommufd_backend_alloc_hwpt(IOMMUFDBackend *be, uint32_t dev_id, uint32_t pt_id, uint32_t flags, uint32_t data_type, uint32_t data_len, - void *data_ptr, uint32_t *out_hwpt, - Error **errp); + void *data_ptr, uint32_t fault_id, + uint32_t *out_hwpt, Error **errp); bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, uint32_t dev_id, uint32_t viommu_type, uint32_t hwpt_id, uint32_t *out_hwpt, Error **errp); diff --git a/backends/iommufd.c b/backends/iommufd.c index 9496377a25..fe64badea0 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -310,23 +310,28 @@ int iommufd_backend_unmap_dma(IOMMUFDBackend *be, uin= t32_t ioas_id, bool iommufd_backend_alloc_hwpt(IOMMUFDBackend *be, uint32_t dev_id, uint32_t pt_id, uint32_t flags, uint32_t data_type, uint32_t data_len, - void *data_ptr, uint32_t *out_hwpt, - Error **errp) + void *data_ptr, uint32_t fault_id, + uint32_t *out_hwpt, Error **errp) { int ret, fd =3D be->fd; struct iommu_hwpt_alloc alloc_hwpt =3D { .size =3D sizeof(struct iommu_hwpt_alloc), - .flags =3D flags, .dev_id =3D dev_id, .pt_id =3D pt_id, .data_type =3D data_type, .data_len =3D data_len, .data_uptr =3D (uintptr_t)data_ptr, + .fault_id =3D fault_id, }; =20 + if (fault_id) { + flags |=3D IOMMU_HWPT_FAULT_ID_VALID; + } + alloc_hwpt.flags =3D flags; + ret =3D ioctl(fd, IOMMU_HWPT_ALLOC, &alloc_hwpt); trace_iommufd_backend_alloc_hwpt(fd, dev_id, pt_id, flags, data_type, - data_len, (uintptr_t)data_ptr, + data_len, (uintptr_t)data_ptr, fault_= id, alloc_hwpt.out_hwpt_id, ret); if (ret) { error_setg_errno(errp, errno, "Failed to allocate hwpt"); diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 0af6b3296d..1e2fb1e748 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -224,7 +224,7 @@ smmuv3_accel_dev_alloc_translate(SMMUv3AccelDevice *acc= el_dev, STE *ste, accel->viommu->viommu_id, flags, IOMMU_HWPT_DATA_ARM_SMMUV3, sizeof(nested_data), &nested_data, - &hwpt_id, errp)) { + 0, &hwpt_id, errp)) { return NULL; } =20 @@ -558,14 +558,14 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDe= viceIOMMUFD *idev, if (!iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, viommu_id, 0, IOMMU_HWPT_DATA_ARM_SMMUV3, sizeof(abort_data), &abort_data, - &accel->abort_hwpt_id, errp)) { + 0, &accel->abort_hwpt_id, errp)) { goto free_viommu; } =20 if (!iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, viommu_id, 0, IOMMU_HWPT_DATA_ARM_SMMUV3, sizeof(bypass_data), &bypass_data, - &accel->bypass_hwpt_id, errp)) { + 0, &accel->bypass_hwpt_id, errp)) { goto free_abort_hwpt; } =20 diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index e73695ff83..32cca7672a 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -115,7 +115,7 @@ static bool vtd_create_fs_hwpt(VTDHostIOMMUDevice *vtd_= hiod, =20 return iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, idev->hw= pt_id, flags, IOMMU_HWPT_DATA_VTD_S1, - sizeof(vtd), &vtd, fs_hwpt_id, errp); + sizeof(vtd), &vtd, 0, fs_hwpt_id, er= rp); } =20 static void vtd_destroy_old_fs_hwpt(VTDHostIOMMUDevice *vtd_hiod, diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index dce4e4ce72..e4e8b266ab 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -444,7 +444,7 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *vb= asedev, if (!iommufd_backend_alloc_hwpt(iommufd, vbasedev->devid, container->ioas_id, flags, IOMMU_HWPT_DATA_NONE, 0, NULL, - &hwpt_id, errp)) { + 0, &hwpt_id, errp)) { return false; } =20 diff --git a/backends/trace-events b/backends/trace-events index 6820a9939e..8a204fcb73 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -16,7 +16,7 @@ iommufd_backend_map_file_dma(int iommufd, uint32_t ioas, = uint64_t iova, uint64_t iommufd_backend_unmap_dma_non_exist(int iommufd, uint32_t ioas, uint64_t i= ova, uint64_t size, int ret) " Unmap nonexistent mapping: iommufd=3D%d ioas= =3D%d iova=3D0x%"PRIx64" size=3D0x%"PRIx64" (%d)" iommufd_backend_unmap_dma(int iommufd, uint32_t ioas, uint64_t iova, uint6= 4_t size, int ret) " iommufd=3D%d ioas=3D%d iova=3D0x%"PRIx64" size=3D0x%"P= RIx64" (%d)" iommufd_backend_alloc_ioas(int iommufd, uint32_t ioas) " iommufd=3D%d ioas= =3D%d" -iommufd_backend_alloc_hwpt(int iommufd, uint32_t dev_id, uint32_t pt_id, u= int32_t flags, uint32_t hwpt_type, uint32_t len, uint64_t data_ptr, uint32_= t out_hwpt_id, int ret) " iommufd=3D%d dev_id=3D%u pt_id=3D%u flags=3D0x%x = hwpt_type=3D%u len=3D%u data_ptr=3D0x%"PRIx64" out_hwpt=3D%u (%d)" +iommufd_backend_alloc_hwpt(int iommufd, uint32_t dev_id, uint32_t pt_id, u= int32_t flags, uint32_t hwpt_type, uint32_t len, uint64_t data_ptr, uint32_= t fault_id, uint32_t out_hwpt_id, int ret) " iommufd=3D%d dev_id=3D%u pt_id= =3D%u flags=3D0x%x hwpt_type=3D%u len=3D%u data_ptr=3D0x%"PRIx64" fault_id= =3D%u out_hwpt=3D%u (%d)" iommufd_backend_alloc_faultq(int iommufd, uint32_t fault_id, uint32_t faul= t_fd, int ret) " iommufd=3D%d fault_id=3D%d fault_fd=3D%d (%d)" iommufd_backend_free_id(int iommufd, uint32_t id, int ret) " iommufd=3D%d = id=3D%d (%d)" iommufd_backend_set_dirty(int iommufd, uint32_t hwpt_id, bool start, int r= et) " iommufd=3D%d hwpt=3D%u enable=3D%d (%d)" --=20 2.47.3 From nobody Thu Apr 2 18:50:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="75719900" X-IronPort-AV: E=Sophos;i="6.23,143,1770624000"; d="scan'208";a="75719900" X-CSE-ConnectionGUID: v8u9LllDT4+5BHkm1Z2odQ== X-CSE-MsgGUID: RPBLwyPuQbyKxSdBf4Zt0w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,143,1770624000"; d="scan'208";a="221874388" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [PATCH 3/5] intel_iommu_accel: Add PRQ injection for passthrough device Date: Thu, 26 Mar 2026 22:52:25 -0400 Message-ID: <20260327025228.474257-4-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260327025228.474257-1-zhenzhong.duan@intel.com> References: <20260327025228.474257-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1774580021525154100 Content-Type: text/plain; charset="utf-8" When the guest enables the PRQ in vIOMMU, allocate a FAULTQ object so that host-side recoverable fault events can be received and propagated back to the guest. Install an event handler on the FAULTQ fd to read and propagate host generated recoverable fault events to the guest. The handler runs in QEMU's main loop, using a non-blocking fd registered via qemu_set_fd_handler(). Signed-off-by: Zhenzhong Duan Tested-by: Xudong Hao --- hw/i386/intel_iommu_accel.h | 2 + hw/i386/intel_iommu_accel.c | 151 +++++++++++++++++++++++++++++++++++- hw/i386/trace-events | 1 + 3 files changed, 150 insertions(+), 4 deletions(-) diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h index 45a12e0292..10e6ee5722 100644 --- a/hw/i386/intel_iommu_accel.h +++ b/hw/i386/intel_iommu_accel.h @@ -17,6 +17,8 @@ typedef struct VTDAccelPASIDCacheEntry { VTDPASIDEntry pasid_entry; uint32_t pasid; uint32_t fs_hwpt_id; + uint32_t fault_id; + int fault_fd; QLIST_ENTRY(VTDAccelPASIDCacheEntry) next; } VTDAccelPASIDCacheEntry; =20 diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index 32cca7672a..0fce62ff75 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -9,6 +9,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/error-report.h" #include "system/iommufd.h" #include "intel_iommu_internal.h" #include "intel_iommu_accel.h" @@ -38,6 +39,8 @@ static inline int vtd_hiod_get_pe_from_pasid(VTDAccelPASI= DCacheEntry *vtd_pce, return vtd_ce_get_pasid_entry(s, &ce, pe, pasid); } =20 +static PCIIOMMUOps *accel_ops; + bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, Error **errp) { @@ -99,8 +102,137 @@ VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSp= ace *as) return NULL; } =20 -static bool vtd_create_fs_hwpt(VTDHostIOMMUDevice *vtd_hiod, - VTDPASIDEntry *pe, uint32_t *fs_hwpt_id, +static void vtd_prq_report_fault(VTDAccelPASIDCacheEntry *vtd_pce, + struct iommu_hwpt_pgfault *fault, int cnt) +{ + VTDHostIOMMUDevice *vtd_hiod =3D vtd_pce->vtd_hiod; + + for (; cnt--; fault++) { + bool last_page =3D fault->flags & IOMMU_PGFAULT_FLAGS_LAST_PAGE; + + accel_ops->pri_request_page(vtd_hiod->bus, vtd_hiod->iommu_state, + vtd_hiod->devfn, vtd_pce->pasid, + fault->perm & IOMMU_PGFAULT_PERM_PRIV, + fault->perm & IOMMU_PGFAULT_PERM_EXEC, + fault->addr, last_page, fault->grpid, + fault->perm & IOMMU_PGFAULT_PERM_READ, + fault->perm & IOMMU_PGFAULT_PERM_WRITE= ); + } +} + +#define FAULTQ_BUF_SIZE 100 /* Large enough in regular test */ + +static void vtd_prq_read_fault(void *opaque) +{ + VTDAccelPASIDCacheEntry *vtd_pce =3D opaque; + struct iommu_hwpt_pgfault fault[FAULTQ_BUF_SIZE]; + uint32_t id =3D vtd_pce->fault_id, fd =3D vtd_pce->fault_fd; + ssize_t bytes, last_bytes; + + bytes =3D read(fd, fault, sizeof(fault)); + trace_vtd_prq_read_fault(id, fd, bytes); + if (bytes < 0) { + if (errno !=3D EAGAIN && errno !=3D EINTR) { + error_report_once("FAULTQ(id %u): read failed (%m)", id); + } + return; + } else if (!bytes) { + error_report_once("FAULTQ(id %u): fault group too big", id); + return; + } + + last_bytes =3D bytes % sizeof(fault[0]); + if (last_bytes) { + error_report_once("FAULTQ(id %u): discard partial fault data: %zd/= %zu", + id, last_bytes, sizeof(fault)); + } + + vtd_prq_report_fault(vtd_pce, fault, bytes / sizeof(fault[0])); +} + +static void vtd_destroy_fs_faultq(VTDHostIOMMUDevice *vtd_hiod, + uint32_t fault_id, uint32_t fault_fd) +{ + HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->h= iod); + + if (!fault_id) { + return; + } + + close(fault_fd); + iommufd_backend_free_id(idev->iommufd, fault_id); +} + +static bool vtd_create_fs_faultq(VTDHostIOMMUDevice *vtd_hiod, + uint32_t *fault_id_p, uint32_t *fault_fd_= p, + Error **errp) +{ + HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->h= iod); + IntelIOMMUState *s =3D vtd_hiod->iommu_state; + uint8_t bus_n =3D pci_bus_num(vtd_hiod->bus); + uint32_t fault_id, fault_fd; + VTDContextEntry ce; + int flags; + + if (!s->svm || + vtd_dev_to_context_entry(s, bus_n, vtd_hiod->devfn, &ce) || + !VTD_CE_GET_PRE(&ce)) { + *fault_id_p =3D 0; + return true; + } + + if (!iommufd_backend_alloc_faultq(idev->iommufd, &fault_id, &fault_fd, + errp)) { + return false; + } + + flags =3D fcntl(fault_fd, F_GETFL); + if (flags < 0) { + error_setg_errno(errp, errno, "Failed to get flags for FAULTQ fd"); + goto free_faultq; + } + + if (fcntl(fault_fd, F_SETFL, flags | O_NONBLOCK) < 0) { + error_setg_errno(errp, errno, "Failed to set O_NONBLOCK on FAULTQ = fd"); + goto free_faultq; + } + + *fault_id_p =3D fault_id; + *fault_fd_p =3D fault_fd; + return true; + +free_faultq: + vtd_destroy_fs_faultq(vtd_hiod, fault_id, fault_fd); + return false; +} + +static void vtd_destroy_old_fs_faultq(VTDHostIOMMUDevice *vtd_hiod, + VTDAccelPASIDCacheEntry *vtd_pce) +{ + if (!vtd_pce->fault_id) { + return; + } + + qemu_set_fd_handler(vtd_pce->fault_fd, NULL, NULL, NULL); + vtd_destroy_fs_faultq(vtd_hiod, vtd_pce->fault_id, vtd_pce->fault_fd); + vtd_pce->fault_id =3D 0; + vtd_pce->fault_fd =3D -1; +} + +static void vtd_setup_fs_faultq(VTDAccelPASIDCacheEntry *vtd_pce, + uint32_t fault_id, uint32_t fault_fd) +{ + if (!fault_id) { + return; + } + + vtd_pce->fault_id =3D fault_id; + vtd_pce->fault_fd =3D fault_fd; + qemu_set_fd_handler(fault_fd, vtd_prq_read_fault, NULL, vtd_pce); +} + +static bool vtd_create_fs_hwpt(VTDHostIOMMUDevice *vtd_hiod, VTDPASIDEntry= *pe, + uint32_t fault_id, uint32_t *fs_hwpt_id, Error **errp) { HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->h= iod); @@ -115,7 +247,8 @@ static bool vtd_create_fs_hwpt(VTDHostIOMMUDevice *vtd_= hiod, =20 return iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, idev->hw= pt_id, flags, IOMMU_HWPT_DATA_VTD_S1, - sizeof(vtd), &vtd, 0, fs_hwpt_id, er= rp); + sizeof(vtd), &vtd, fault_id, fs_hwpt= _id, + errp); } =20 static void vtd_destroy_old_fs_hwpt(VTDHostIOMMUDevice *vtd_hiod, @@ -137,6 +270,7 @@ static bool vtd_device_attach_iommufd(VTDAccelPASIDCach= eEntry *vtd_pce, HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->h= iod); VTDPASIDEntry *pe =3D &vtd_pce->pasid_entry; uint32_t hwpt_id =3D idev->hwpt_id, pasid =3D vtd_pce->pasid; + uint32_t fault_id =3D 0, fault_fd; bool ret; =20 /* @@ -151,7 +285,11 @@ static bool vtd_device_attach_iommufd(VTDAccelPASIDCac= heEntry *vtd_pce, } =20 if (vtd_pe_pgtt_is_fst(pe)) { - if (!vtd_create_fs_hwpt(vtd_hiod, pe, &hwpt_id, errp)) { + if (!vtd_create_fs_faultq(vtd_hiod, &fault_id, &fault_fd, errp)) { + return false; + } + if (!vtd_create_fs_hwpt(vtd_hiod, pe, fault_id, &hwpt_id, errp)) { + vtd_destroy_fs_faultq(vtd_hiod, fault_id, fault_fd); return false; } } @@ -161,11 +299,14 @@ static bool vtd_device_attach_iommufd(VTDAccelPASIDCa= cheEntry *vtd_pce, if (ret) { /* Destroy old fs_hwpt if it's a replacement */ vtd_destroy_old_fs_hwpt(vtd_hiod, vtd_pce); + vtd_destroy_old_fs_faultq(vtd_hiod, vtd_pce); if (vtd_pe_pgtt_is_fst(pe)) { vtd_pce->fs_hwpt_id =3D hwpt_id; + vtd_setup_fs_faultq(vtd_pce, fault_id, fault_fd); } } else if (vtd_pe_pgtt_is_fst(pe)) { iommufd_backend_free_id(idev->iommufd, hwpt_id); + vtd_destroy_fs_faultq(vtd_hiod, fault_id, fault_fd); } =20 return ret; @@ -197,6 +338,7 @@ static bool vtd_device_detach_iommufd(VTDAccelPASIDCach= eEntry *vtd_pce, =20 if (ret) { vtd_destroy_old_fs_hwpt(vtd_hiod, vtd_pce); + vtd_destroy_old_fs_faultq(vtd_hiod, vtd_pce); } =20 return ret; @@ -549,4 +691,5 @@ static uint64_t vtd_get_host_iommu_quirks(uint32_t type, void vtd_iommu_ops_update_accel(PCIIOMMUOps *ops) { ops->get_host_iommu_quirks =3D vtd_get_host_iommu_quirks; + accel_ops =3D ops; } diff --git a/hw/i386/trace-events b/hw/i386/trace-events index 5fa5e93b68..bf139338f7 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -77,6 +77,7 @@ vtd_reset_exit(void) "" vtd_device_attach_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwpt_id, = int ret) "dev_id %d pasid %d hwpt_id %d, ret: %d" vtd_device_detach_hwpt(uint32_t dev_id, uint32_t pasid, int ret) "dev_id %= d pasid %d ret: %d" vtd_device_reattach_def_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwp= t_id, int ret) "dev_id %d pasid %d hwpt_id %d, ret: %d" +vtd_prq_read_fault(uint32_t fault_id, uint32_t fault_fd, ssize_t bytes) "f= ault_id %d fault_fd %d ret: %zd" =20 # amd_iommu.c amdvi_evntlog_fail(uint64_t addr, uint32_t head) "error: fail to write at = addr 0x%"PRIx64" + offset 0x%"PRIx32 --=20 2.47.3 From nobody Thu Apr 2 18:50:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="75719908" X-IronPort-AV: E=Sophos;i="6.23,143,1770624000"; d="scan'208";a="75719908" X-CSE-ConnectionGUID: AWgkCBLDTRubp9msX1uCow== X-CSE-MsgGUID: FCal3sZ8QWKziI/LNLR9+A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,143,1770624000"; d="scan'208";a="221874391" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [PATCH 4/5] intel_iommu_accel: Accept PRQ response for passthrough device Date: Thu, 26 Mar 2026 22:52:26 -0400 Message-ID: <20260327025228.474257-5-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260327025228.474257-1-zhenzhong.duan@intel.com> References: <20260327025228.474257-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1774580020098158500 Content-Type: text/plain; charset="utf-8" Propagate guest's PRQ response to host by writing to fault_fd. Create a new VTDPRQEntry to cache cookie for each fault group, this cookie is used to mark the fault group on host side. Signed-off-by: Zhenzhong Duan Reviewed-by: Clement Mathieu--Drif Tested-by: Xudong Hao --- hw/i386/intel_iommu_accel.h | 14 ++++++++ include/hw/i386/intel_iommu.h | 6 ++++ hw/i386/intel_iommu.c | 4 +++ hw/i386/intel_iommu_accel.c | 65 +++++++++++++++++++++++++++++++++++ hw/i386/trace-events | 1 + 5 files changed, 90 insertions(+) diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h index 10e6ee5722..b46c7126f7 100644 --- a/hw/i386/intel_iommu_accel.h +++ b/hw/i386/intel_iommu_accel.h @@ -19,6 +19,9 @@ typedef struct VTDAccelPASIDCacheEntry { uint32_t fs_hwpt_id; uint32_t fault_id; int fault_fd; + QLIST_HEAD(, VTDPRQEntry) vtd_prq_list; + IOMMUPRINotifier pri_notifier_entry; + IOMMUPRINotifier *pri_notifier; QLIST_ENTRY(VTDAccelPASIDCacheEntry) next; } VTDAccelPASIDCacheEntry; =20 @@ -31,6 +34,9 @@ void vtd_flush_host_piotlb_all_accel(IntelIOMMUState *s, = uint16_t domain_id, uint64_t npages, bool ih); void vtd_pasid_cache_sync_accel(IntelIOMMUState *s, VTDPASIDCacheInfo *pc_= info); void vtd_pasid_cache_reset_accel(IntelIOMMUState *s); +bool vtd_propagate_page_group_response_accel(IntelIOMMUState *s, + uint16_t rid, uint32_t pasid, + IOMMUPRIResponse *response); void vtd_iommu_ops_update_accel(PCIIOMMUOps *ops); #else static inline bool vtd_check_hiod_accel(IntelIOMMUState *s, @@ -69,6 +75,14 @@ static inline void vtd_pasid_cache_reset_accel(IntelIOMM= UState *s) { } =20 +static inline +bool vtd_propagate_page_group_response_accel(IntelIOMMUState *s, + uint16_t rid, uint32_t pasid, + IOMMUPRIResponse *response) +{ + return false; +} + static inline void vtd_iommu_ops_update_accel(PCIIOMMUOps *ops) { } diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 1842ba5840..5d44eac0ed 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -100,6 +100,12 @@ typedef struct VTDPASIDCacheEntry { bool valid; } VTDPASIDCacheEntry; =20 +typedef struct VTDPRQEntry { + uint32_t grpid; + uint32_t cookie; + QLIST_ENTRY(VTDPRQEntry) next; +} VTDPRQEntry; + struct VTDAddressSpace { PCIBus *bus; uint8_t devfn; diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 96b4102ab9..d670a0377b 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3390,6 +3390,10 @@ static bool vtd_process_page_group_response_desc(Int= elIOMMUState *s, response.response_code =3D IOMMU_PRI_RESP_FAILURE; } =20 + if (vtd_propagate_page_group_response_accel(s, rid, pasid, &response))= { + return true; + } + if (vtd_dev_as->pri_notifier) { vtd_dev_as->pri_notifier->notify(vtd_dev_as->pri_notifier, &respon= se); } diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index 0fce62ff75..44af534c55 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -102,6 +102,30 @@ VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSp= ace *as) return NULL; } =20 +bool vtd_propagate_page_group_response_accel(IntelIOMMUState *s, + uint16_t rid, uint32_t pasid, + IOMMUPRIResponse *response) +{ + VTDAddressSpace *vtd_as =3D vtd_get_as_by_sid(s, rid); + VTDAccelPASIDCacheEntry *vtd_pce; + VTDHostIOMMUDevice *vtd_hiod =3D vtd_find_hiod_iommufd(vtd_as); + + if (!vtd_hiod) { + return false; + } + + QLIST_FOREACH(vtd_pce, &vtd_hiod->pasid_cache_list, next) { + if (vtd_pce->pasid =3D=3D pasid) { + if (vtd_pce->pri_notifier) { + vtd_pce->pri_notifier->notify(vtd_pce->pri_notifier, respo= nse); + } + return true; + } + } + + return false; +} + static void vtd_prq_report_fault(VTDAccelPASIDCacheEntry *vtd_pce, struct iommu_hwpt_pgfault *fault, int cnt) { @@ -117,6 +141,13 @@ static void vtd_prq_report_fault(VTDAccelPASIDCacheEnt= ry *vtd_pce, fault->addr, last_page, fault->grpid, fault->perm & IOMMU_PGFAULT_PERM_READ, fault->perm & IOMMU_PGFAULT_PERM_WRITE= ); + if (last_page) { + VTDPRQEntry *prqe =3D g_malloc0(sizeof(*prqe)); + + prqe->grpid =3D fault->grpid; + prqe->cookie =3D fault->cookie; + QLIST_INSERT_HEAD(&vtd_pce->vtd_prq_list, prqe, next); + } } } =20 @@ -150,6 +181,36 @@ static void vtd_prq_read_fault(void *opaque) vtd_prq_report_fault(vtd_pce, fault, bytes / sizeof(fault[0])); } =20 +static void vtd_prq_response_notify(struct IOMMUPRINotifier *notifier, + IOMMUPRIResponse *response) +{ + VTDAccelPASIDCacheEntry *vtd_pce =3D + container_of(notifier, VTDAccelPASIDCacheEntry, pri_notifier_entry= ); + uint32_t id =3D vtd_pce->fault_id, fd =3D vtd_pce->fault_fd; + struct iommu_hwpt_page_response resp; + VTDPRQEntry *prqe, *tmp; + ssize_t bytes; + + QLIST_FOREACH_SAFE(prqe, &vtd_pce->vtd_prq_list, next, tmp) { + if (prqe->grpid !=3D response->prgi) { + continue; + } + + resp.cookie =3D prqe->cookie; + resp.code =3D response->response_code; + bytes =3D write(fd, &resp, sizeof(resp)); + trace_vtd_prq_response_notify(id, fd, resp.cookie, resp.code, byte= s); + if (bytes < 0) { + error_report_once("FAULTQ(id %u): write failed " + "[cookie 0x%x code 0x%x] (%m)", + id, resp.cookie, resp.code); + } + + QLIST_REMOVE(prqe, next); + g_free(prqe); + } +} + static void vtd_destroy_fs_faultq(VTDHostIOMMUDevice *vtd_hiod, uint32_t fault_id, uint32_t fault_fd) { @@ -213,6 +274,7 @@ static void vtd_destroy_old_fs_faultq(VTDHostIOMMUDevic= e *vtd_hiod, return; } =20 + vtd_pce->pri_notifier =3D NULL; qemu_set_fd_handler(vtd_pce->fault_fd, NULL, NULL, NULL); vtd_destroy_fs_faultq(vtd_hiod, vtd_pce->fault_id, vtd_pce->fault_fd); vtd_pce->fault_id =3D 0; @@ -228,6 +290,8 @@ static void vtd_setup_fs_faultq(VTDAccelPASIDCacheEntry= *vtd_pce, =20 vtd_pce->fault_id =3D fault_id; vtd_pce->fault_fd =3D fault_fd; + vtd_pce->pri_notifier_entry.notify =3D vtd_prq_response_notify; + vtd_pce->pri_notifier =3D &vtd_pce->pri_notifier_entry; qemu_set_fd_handler(fault_fd, vtd_prq_read_fault, NULL, vtd_pce); } =20 @@ -492,6 +556,7 @@ static void vtd_accel_fill_pc(VTDHostIOMMUDevice *vtd_h= iod, uint32_t pasid, vtd_pce->vtd_hiod =3D vtd_hiod; vtd_pce->pasid =3D pasid; vtd_pce->pasid_entry =3D *pe; + QLIST_INIT(&vtd_pce->vtd_prq_list); QLIST_INSERT_HEAD(&vtd_hiod->pasid_cache_list, vtd_pce, next); =20 if (!vtd_device_attach_iommufd(vtd_pce, &local_err)) { diff --git a/hw/i386/trace-events b/hw/i386/trace-events index bf139338f7..52dab0b508 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -78,6 +78,7 @@ vtd_device_attach_hwpt(uint32_t dev_id, uint32_t pasid, u= int32_t hwpt_id, int re vtd_device_detach_hwpt(uint32_t dev_id, uint32_t pasid, int ret) "dev_id %= d pasid %d ret: %d" vtd_device_reattach_def_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwp= t_id, int ret) "dev_id %d pasid %d hwpt_id %d, ret: %d" vtd_prq_read_fault(uint32_t fault_id, uint32_t fault_fd, ssize_t bytes) "f= ault_id %d fault_fd %d ret: %zd" +vtd_prq_response_notify(uint32_t fault_id, uint32_t fault_fd, uint32_t coo= kie, uint32_t code, ssize_t bytes) "fault_id %d fault_fd %d cookie %d code = %d ret: %zd" =20 # amd_iommu.c amdvi_evntlog_fail(uint64_t addr, uint32_t head) "error: fail to write at = addr 0x%"PRIx64" + offset 0x%"PRIx32 --=20 2.47.3 From nobody Thu Apr 2 18:50:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="75719916" X-IronPort-AV: E=Sophos;i="6.23,143,1770624000"; d="scan'208";a="75719916" X-CSE-ConnectionGUID: I+Me9fTLR9aAjQ582pARFQ== X-CSE-MsgGUID: eLxTD4IHTxCeN0RKJXe8cQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,143,1770624000"; d="scan'208";a="221874395" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [PATCH 5/5] intel_iommu_accel: teardown FAULTQ resources in bottom half Date: Thu, 26 Mar 2026 22:52:27 -0400 Message-ID: <20260327025228.474257-6-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260327025228.474257-1-zhenzhong.duan@intel.com> References: <20260327025228.474257-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1774580023343158500 Content-Type: text/plain; charset="utf-8" When a pasid entry becomes invalid, we need to release all resources allocated for that entry including FAULTQ object and fault_fd. We call qemu_set_fd_handler() to detach fault_fd's io_read handler and wakes up main thread from poll(), but there could still be a small window we call iommufd_backend_free_id(fault_id) before poll() exit and release fault_id file reference. In this rare case, FAULTQ object free return -EBUSY because opened fault_id file keeps reference of FAULTQ object. Teardown FAULTQ resources in bottom half to ensure poll() has released fault_id file reference. Suggested-by: Shameer Kolothum Signed-off-by: Zhenzhong Duan Tested-by: Xudong Hao --- hw/i386/intel_iommu_accel.c | 31 +++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index 44af534c55..fdc376c070 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -267,16 +267,43 @@ free_faultq: return false; } =20 +typedef struct IOMMUFaultQueue { + IOMMUFDBackend *iommufd; + uint32_t id; + int fd; +} IOMMUFaultQueue; + +static void faultq_teardown_bh(void *opaque) +{ + IOMMUFaultQueue *fq =3D opaque; + + qemu_set_fd_handler(fq->fd, NULL, NULL, NULL); + close(fq->fd); + iommufd_backend_free_id(fq->iommufd, fq->id); + + g_free(fq); +} + + static void vtd_destroy_old_fs_faultq(VTDHostIOMMUDevice *vtd_hiod, VTDAccelPASIDCacheEntry *vtd_pce) { + HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->h= iod); + if (!vtd_pce->fault_id) { return; } =20 vtd_pce->pri_notifier =3D NULL; - qemu_set_fd_handler(vtd_pce->fault_fd, NULL, NULL, NULL); - vtd_destroy_fs_faultq(vtd_hiod, vtd_pce->fault_id, vtd_pce->fault_fd); + + IOMMUFaultQueue *fq =3D g_malloc(sizeof(IOMMUFaultQueue)); + fq->iommufd =3D idev->iommufd; + fq->fd =3D vtd_pce->fault_fd; + fq->id =3D vtd_pce->fault_id; + + aio_bh_schedule_oneshot(iohandler_get_aio_context(), + faultq_teardown_bh, fq); + vtd_pce->fault_id =3D 0; vtd_pce->fault_fd =3D -1; } --=20 2.47.3