From nobody Thu Apr 2 15:42:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1774612167; cv=none; d=zohomail.com; s=zohoarc; b=c8l/k5R2b4XxM2/gtcigc9NLm4k8uhMqGOwzwwv20D4dEL1CyhsiYsaoXKojLWmLulnNJo0Wp6zAtYS8kmMTUg16RLJk0nrL1fq4XPU/+PKF9qm34YBdI9u6fKdOIOHIEkfU0+qTHeNXrcLXZy++Sq9PcMtsT/+4QaMzQMarbrU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774612167; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=dvogLia3c1ViymgIXbXa1aDkmcVZpBH2hoZ4U3I42KI=; b=LseMmSnzcpQ8m2gztfrlUe49CslfK8SYiEM4PWOC08UkfR1gsqzU7PxJqdxloy2dMlD5NfldfmyTp6Jsplupebg0JGoQDlpWTPRZTE6G1a1bkRWU4dVwC47frwX7nkrlfloUuZdFNvcvvW5ed8RRYBOcxa8gtBiDPQBaLuf13TU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177461216700881.52201492073993; Fri, 27 Mar 2026 04:49:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65gU-0006w7-Ru; Fri, 27 Mar 2026 07:49:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65gJ-0006rI-DY for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:48:51 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65gH-0000N2-QW for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:48:51 -0400 Received: from mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-146-_wgW-klzPE-WOoRSNXGCug-1; Fri, 27 Mar 2026 07:48:47 -0400 Received: from mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 393ED18005BB; Fri, 27 Mar 2026 11:48:45 +0000 (UTC) Received: from mbawa-thinkpadt14gen5.bengluru.csb (unknown [10.74.88.10]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 2728D19560B1; Fri, 27 Mar 2026 11:48:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1774612129; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dvogLia3c1ViymgIXbXa1aDkmcVZpBH2hoZ4U3I42KI=; b=CtwBCzpl6bzxbxrH06bpmzrPcriaXVGgxos4lMGgqc8GLx7ByMeE7+fucxcbIf24sQGavv Nwd9QJpf/6mSi8ZzovYymPzAHhFZamqBLmCD/BAQ2ehNJ8HxnCz/sVbkWXvDUWwaPA2xdJ /XxlWjAyCqvQXGfl4KisGwujs6P+7t0= X-MC-Unique: _wgW-klzPE-WOoRSNXGCug-1 X-Mimecast-MFC-AGG-ID: _wgW-klzPE-WOoRSNXGCug_1774612125 From: Mohammadfaiz Bawa To: qemu-devel@nongnu.org Cc: stefanb@linux.vnet.ibm.com, pierrick.bouvier@linaro.org, "Michael S . Tsirkin" , imammedo@redhat.com, anisinha@redhat.com, peter.maydell@linaro.org, shannon.zhaosl@gmail.com, qemu-arm@nongnu.org, mohamed@unpredictable.fr, Mohammadfaiz Bawa , Stefan Berger Subject: [PATCH v2 1/3] docs/specs/tpm: document PPI support on ARM64 virt Date: Fri, 27 Mar 2026 17:18:22 +0530 Message-ID: <20260327-tpm-tis-sysbus-ppi-v2-1-d8ec84d25dbc@redhat.com> In-Reply-To: <20260327-tpm-tis-sysbus-ppi-v2-0-d8ec84d25dbc@redhat.com> References: <20260327-tpm-tis-sysbus-ppi-v2-0-d8ec84d25dbc@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mbawa@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1774612170128154100 Document that tpm-tis-device on the ARM virt machine supports PPI with dynamically allocated MMIO via the platform bus, unlike x86 where PPI is at the fixed address 0xFED45000. Also add hw/arm/virt-acpi-build.c and hw/acpi/tpm.c to the list of files related to TPM ACPI tables. Reviewed-by: Stefan Berger Signed-off-by: Mohammadfaiz Bawa --- docs/specs/tpm.rst | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/docs/specs/tpm.rst b/docs/specs/tpm.rst index b630a351b4f77a8d2512f22446d00a4d674c7777..ba2b0d726745fdf8ebc4c73c9c4= 2e1ff8047a9db 100644 --- a/docs/specs/tpm.rst +++ b/docs/specs/tpm.rst @@ -187,8 +187,32 @@ The location of the table is given by the fw_cfg ``tpm= ppi_address`` field. The PPI memory region size is 0x400 (``TPM_PPI_ADDR_SIZE``) to leave enough room for future updates. =20 +PPI on ARM64 virt +----------------- + +The ARM virt machine supports PPI for ``tpm-tis-device`` as defined +in the `PPI specification`_. + +Unlike the x86 TIS device where the PPI memory region is mapped at +the fixed address ``0xFED45000`` (within the TIS MMIO range), the +ARM64 sysbus device registers PPI memory as a second MMIO region +on the platform bus. The platform bus assigns the guest physical +address dynamically at device plug time. The ACPI ``_DSM`` method +and PPI operation regions reference this dynamically resolved +address. + +PPI is controlled by the ``ppi`` property (default ``on``):: + + -device tpm-tis-device,tpmdev=3Dtpm0,ppi=3Don + +Without PPI, guest operating systems such as Windows 11 +ARM64 will log errors when attempting to query TPM Physical +Presence capabilities via the ACPI ``_DSM`` method. + QEMU files related to TPM ACPI tables: - ``hw/i386/acpi-build.c`` + - ``hw/arm/virt-acpi-build.c`` + - ``hw/acpi/tpm.c`` - ``include/hw/acpi/tpm.h`` =20 TPM backend devices --=20 2.53.0 From nobody Thu Apr 2 15:42:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1774612146; cv=none; d=zohomail.com; s=zohoarc; b=knPCwBMlxJCeylY8xPqywxc5p351cNpw8UHMa3K4olFHJG0YtFX/fKQArxCGAr9BhjWMDVdC21acS9D0Zx8lj57GOTAKPe698BGOcpFM/fqPp39nLefYFuxSjbXgo0eBdWGzNSm6nmoD9TF3c2o8cW7hff0aa9w0sXBL6ypeMdo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774612146; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=vNfBpMAfcLKVWxGQFoc6sYSvJTCHtumHh8ghhvrEnQM=; b=YMH+hwEeYpiYW8ws1lncikeYUNJBkyNdvFBnYxCzpQ9Wi76HU5shcEQ4Qu0mWrA9wBq71j3zgTL6HuRdaGG0usSk5btXUksVvC1aAiqkXL4axw2JkW2d5NYd+iqJ6IJ3du/rhGFwxcRj9rjTqfEfUrQHf1gSz+beyfjXgfyxcIU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774612146234612.4908248278454; Fri, 27 Mar 2026 04:49:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w65gU-0006wQ-Tr; Fri, 27 Mar 2026 07:49:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65gR-0006u9-1m for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:48:59 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w65gP-0000R2-BX for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:48:58 -0400 Received: from mx-prod-mc-01.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-392-eZXR0pF_MKqnysy0nIhaYw-1; Fri, 27 Mar 2026 07:48:53 -0400 Received: from mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id E087E195608C; Fri, 27 Mar 2026 11:48:51 +0000 (UTC) Received: from mbawa-thinkpadt14gen5.bengluru.csb (unknown [10.74.88.10]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id E6BC219560B1; Fri, 27 Mar 2026 11:48:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1774612136; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vNfBpMAfcLKVWxGQFoc6sYSvJTCHtumHh8ghhvrEnQM=; b=IMbODeMzZYlkA8MKtRkfOKgC8m2DDb9l8iMSUYW8IUedB9LNLYT3NvX8RjyaF8AglCHMbd qapqJ6fSRx0Q6BpayAu7K/wDVwJHKUiEs5xyzBcybxnLLRMHnAEofkk3MsrXku551uiQTO PfvrT9S7dO6Tghr8xHxudZRYYjEf/Zs= X-MC-Unique: eZXR0pF_MKqnysy0nIhaYw-1 X-Mimecast-MFC-AGG-ID: eZXR0pF_MKqnysy0nIhaYw_1774612132 From: Mohammadfaiz Bawa To: qemu-devel@nongnu.org Cc: stefanb@linux.vnet.ibm.com, pierrick.bouvier@linaro.org, "Michael S . Tsirkin" , imammedo@redhat.com, anisinha@redhat.com, peter.maydell@linaro.org, shannon.zhaosl@gmail.com, qemu-arm@nongnu.org, mohamed@unpredictable.fr, Mohammadfaiz Bawa , Stefan Berger Subject: [PATCH v2 2/3] hw/acpi/tpm: parameterize PPI base address in tpm_build_ppi_acpi Date: Fri, 27 Mar 2026 17:18:23 +0530 Message-ID: <20260327-tpm-tis-sysbus-ppi-v2-2-d8ec84d25dbc@redhat.com> In-Reply-To: <20260327-tpm-tis-sysbus-ppi-v2-0-d8ec84d25dbc@redhat.com> References: <20260327-tpm-tis-sysbus-ppi-v2-0-d8ec84d25dbc@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mbawa@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1774612148113154100 Add a ppi_base parameter to tpm_build_ppi_acpi() instead of hardcoding TPM_PPI_ADDR_BASE. This prepares for ARM64 support where PPI memory is dynamically allocated by the platform bus and the address is not known at compile time. Update the x86 ISA TIS caller to pass TPM_PPI_ADDR_BASE explicitly. No behavioral change. Reviewed-by: Stefan Berger Signed-off-by: Mohammadfaiz Bawa --- hw/acpi/tpm.c | 8 ++++---- hw/tpm/tpm_tis_isa.c | 2 +- include/hw/acpi/tpm.h | 3 ++- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/hw/acpi/tpm.c b/hw/acpi/tpm.c index cdc022753659af102e56ea4148423b94de1531f6..c4ff2f8cb836c16b00f70865bf5= 5781d5c402aa2 100644 --- a/hw/acpi/tpm.c +++ b/hw/acpi/tpm.c @@ -20,7 +20,7 @@ #include "qapi/error.h" #include "hw/acpi/tpm.h" =20 -void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev) +void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev, hwaddr ppi_base) { Aml *method, *field, *ifctx, *ifctx2, *ifctx3, *func_mask, *not_implemented, *pak, *tpm2, *tpm3, *pprm, *pprq, *zero, *one; @@ -40,7 +40,7 @@ void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev) */ aml_append(dev, aml_operation_region("TPP2", AML_SYSTEM_MEMORY, - aml_int(TPM_PPI_ADDR_BASE + 0x100), + aml_int(ppi_base + 0x100), 0x5A)); field =3D aml_field("TPP2", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); aml_append(field, aml_named_field("PPIN", 8)); @@ -56,7 +56,7 @@ void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev) aml_append(dev, aml_operation_region( "TPP3", AML_SYSTEM_MEMORY, - aml_int(TPM_PPI_ADDR_BASE + + aml_int(ppi_base + 0x15a /* movv, docs/specs/tpm.rst */), 0x1)); field =3D aml_field("TPP3", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); @@ -78,7 +78,7 @@ void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev) =20 aml_append(method, aml_operation_region("TPP1", AML_SYSTEM_MEMORY, - aml_add(aml_int(TPM_PPI_ADDR_BASE), op, NULL), 0x1)); + aml_add(aml_int(ppi_base), op, NULL), 0x1)); field =3D aml_field("TPP1", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE= ); aml_append(field, aml_named_field("TPPF", 8)); aml_append(method, field); diff --git a/hw/tpm/tpm_tis_isa.c b/hw/tpm/tpm_tis_isa.c index 61e95434f5b824fa99f0a2aff7f151e87ea631ed..e30bef49558673f4c857c02dae0= 59ce3361a1bc7 100644 --- a/hw/tpm/tpm_tis_isa.c +++ b/hw/tpm/tpm_tis_isa.c @@ -162,7 +162,7 @@ static void build_tpm_tis_isa_aml(AcpiDevAmlIf *adev, A= ml *scope) */ /* aml_append(crs, aml_irq_no_flags(isadev->state.irq_num)); */ aml_append(dev, aml_name_decl("_CRS", crs)); - tpm_build_ppi_acpi(ti, dev); + tpm_build_ppi_acpi(ti, dev, TPM_PPI_ADDR_BASE); aml_append(scope, dev); } =20 diff --git a/include/hw/acpi/tpm.h b/include/hw/acpi/tpm.h index d2bf6637c5424b92ad99f5baa938fd6cea3520bf..2ab186a7455593df205a7ffecbe= a2abdfdbd11d5 100644 --- a/include/hw/acpi/tpm.h +++ b/include/hw/acpi/tpm.h @@ -20,6 +20,7 @@ #include "hw/core/registerfields.h" #include "hw/acpi/aml-build.h" #include "system/tpm.h" +#include "exec/hwaddr.h" =20 #ifdef CONFIG_TPM =20 @@ -250,7 +251,7 @@ REG32(CRB_DATA_BUFFER, 0x80) */ #define TPM_I2C_INT_ENABLE_MASK 0x0 =20 -void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev); +void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev, hwaddr ppi_base); =20 #endif /* CONFIG_TPM */ =20 --=20 2.53.0 From nobody Thu Apr 2 15:42:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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bh=Wj7VSdrmGeyQcqp1ipO/DIQIPTkNGA4voSl6q8ut08k=; b=ippvXZ2tH3opKo/lnHAPKTIIzjMcGkJsO7wPcV8C3T77iGMuTq9PVzRFmWpFBd8eWkYC+c d+cZ7BLhXCt9xahuj7mKDWB0czMXoutY6RX7Ih1wryWaz2ilkwFK189jL75cuvuJdpEfwI 5SVFVe+p5jxqhB1FlVvKNv5Rzd3q6Gg= X-MC-Unique: _znI0Om5NseDR4LLQLxjQw-1 X-Mimecast-MFC-AGG-ID: _znI0Om5NseDR4LLQLxjQw_1774612138 From: Mohammadfaiz Bawa To: qemu-devel@nongnu.org Cc: stefanb@linux.vnet.ibm.com, pierrick.bouvier@linaro.org, "Michael S . Tsirkin" , imammedo@redhat.com, anisinha@redhat.com, peter.maydell@linaro.org, shannon.zhaosl@gmail.com, qemu-arm@nongnu.org, mohamed@unpredictable.fr, Mohammadfaiz Bawa , Stefan Berger Subject: [PATCH v2 3/3] hw/tpm: add PPI support to tpm-tis-device for ARM64 virt Date: Fri, 27 Mar 2026 17:18:24 +0530 Message-ID: <20260327-tpm-tis-sysbus-ppi-v2-3-d8ec84d25dbc@redhat.com> In-Reply-To: <20260327-tpm-tis-sysbus-ppi-v2-0-d8ec84d25dbc@redhat.com> References: <20260327-tpm-tis-sysbus-ppi-v2-0-d8ec84d25dbc@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mbawa@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1774612172092158500 Add PPI memory region and ACPI _STA, _DSM to tpm-tis-sysbus so Windows 11 ARM64 guests no longer log Event ID 15 errors from tpm.sys on every boot. Reviewed-by: Stefan Berger Signed-off-by: Mohammadfaiz Bawa --- hw/arm/virt-acpi-build.c | 9 ++++++++- hw/tpm/tpm_tis_sysbus.c | 11 +++++++++++ 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 719d2f994e65f976f6e754259d0b4f1336f82f13..27a7389a33df221a9dfb0cde1bc= 35b3ab62e56be 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -240,7 +240,8 @@ static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineSt= ate *vms) Aml *dev =3D aml_device("TPM0"); aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device"))); - aml_append(dev, aml_name_decl("_UID", aml_int(0))); + aml_append(dev, aml_name_decl("_UID", aml_int(1))); + aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); =20 Aml *crs =3D aml_resource_template(); aml_append(crs, @@ -248,6 +249,12 @@ static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineS= tate *vms) (uint32_t)memory_region_size(sbdev_mr), AML_READ_WRITE)); aml_append(dev, aml_name_decl("_CRS", crs)); + + hwaddr ppi_base =3D platform_bus_get_mmio_addr(pbus, sbdev, 1); + if (ppi_base !=3D -1) { + ppi_base +=3D pbus_base; + tpm_build_ppi_acpi(TPM_IF(sbdev), dev, ppi_base); + } aml_append(scope, dev); } #endif diff --git a/hw/tpm/tpm_tis_sysbus.c b/hw/tpm/tpm_tis_sysbus.c index e9372e7316305fe1a4d415a712ab516e0fd5f073..f8b63dd4607cacb319e27ea83e4= 21ec5bdc1cb0f 100644 --- a/hw/tpm/tpm_tis_sysbus.c +++ b/hw/tpm/tpm_tis_sysbus.c @@ -30,6 +30,7 @@ #include "hw/core/sysbus.h" #include "tpm_tis.h" #include "qom/object.h" +#include "qemu/memalign.h" =20 struct TPMStateSysBus { /*< private >*/ @@ -93,12 +94,14 @@ static void tpm_tis_sysbus_reset(DeviceState *dev) static const Property tpm_tis_sysbus_properties[] =3D { DEFINE_PROP_UINT32("irq", TPMStateSysBus, state.irq_num, TPM_TIS_IRQ), DEFINE_PROP_TPMBE("tpmdev", TPMStateSysBus, state.be_driver), + DEFINE_PROP_BOOL("ppi", TPMStateSysBus, state.ppi_enabled, true), }; =20 static void tpm_tis_sysbus_initfn(Object *obj) { TPMStateSysBus *sbdev =3D TPM_TIS_SYSBUS(obj); TPMState *s =3D &sbdev->state; + size_t host_page_size =3D qemu_real_host_page_size(); =20 memory_region_init_io(&s->mmio, obj, &tpm_tis_memory_ops, s, "tpm-tis-mmio", @@ -106,6 +109,12 @@ static void tpm_tis_sysbus_initfn(Object *obj) =20 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); + + s->ppi.buf =3D qemu_memalign(host_page_size, + ROUND_UP(TPM_PPI_ADDR_SIZE, host_page_size= )); + memory_region_init_ram_device_ptr(&s->ppi.ram, obj, "tpm-ppi", + TPM_PPI_ADDR_SIZE, s->ppi.buf); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->ppi.ram); } =20 static void tpm_tis_sysbus_realizefn(DeviceState *dev, Error **errp) @@ -122,6 +131,8 @@ static void tpm_tis_sysbus_realizefn(DeviceState *dev, = Error **errp) error_setg(errp, "'tpmdev' property is required"); return; } + + vmstate_register_ram(&s->ppi.ram, dev); } =20 static void tpm_tis_sysbus_class_init(ObjectClass *klass, const void *data) --=20 2.53.0