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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1774440593; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=U2SkktuFniNpBHFMckJQz4idYM3YsD8QVsvB/+MsLBM=; b=Mbwaa65GSRkGe9uHVEaz/3KPTHSGl6mUzKILXIZwdDPK2fijkdVBoKOiWbZuiSf9hK/Yrg hyEAwv+Tq1pYRsbcKZKu+YCvp705d/VmFabT/sq0u5CHQOwTsD2WDwiuC2nIno0Nk9w6eS sgNmTdmro0litLhF5m+bh3f2nTwzF4Y= X-MC-Unique: xbaq4GiuMR-0xvz9je7mow-1 X-Mimecast-MFC-AGG-ID: xbaq4GiuMR-0xvz9je7mow_1774440591 From: Thomas Huth To: Paolo Bonzini , qemu-devel@nongnu.org Cc: Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PATCH 1/2] target/i386/tcg/sysemu: Move target specific SMM code to separate functions Date: Wed, 25 Mar 2026 13:09:43 +0100 Message-ID: <20260325120944.29391-2-thuth@redhat.com> In-Reply-To: <20260325120944.29391-1-thuth@redhat.com> References: <20260325120944.29391-1-thuth@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Thomas Huth This code movement will make the next patch easier to read. Signed-off-by: Thomas Huth --- target/i386/tcg/system/smm_helper.c | 47 ++++++++++++++++++----------- 1 file changed, 30 insertions(+), 17 deletions(-) diff --git a/target/i386/tcg/system/smm_helper.c b/target/i386/tcg/system/s= mm_helper.c index fb028a8272f..3be78cd53d3 100644 --- a/target/i386/tcg/system/smm_helper.c +++ b/target/i386/tcg/system/smm_helper.c @@ -32,26 +32,13 @@ #define SMM_REVISION_ID 0x00020000 #endif =20 -void do_smm_enter(X86CPU *cpu) +static void sm_state_init(X86CPU *cpu) { CPUX86State *env =3D &cpu->env; CPUState *cs =3D CPU(cpu); - target_ulong sm_state; SegmentCache *dt; int i, offset; - - qemu_log_mask(CPU_LOG_INT, "SMM: enter\n"); - log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP); - - env->msr_smi_count++; - env->hflags |=3D HF_SMM_MASK; - if (env->hflags2 & HF2_NMI_MASK) { - env->hflags2 |=3D HF2_SMM_INSIDE_NMI_MASK; - } else { - env->hflags2 |=3D HF2_NMI_MASK; - } - - sm_state =3D env->smbase + 0x8000; + target_ulong sm_state =3D env->smbase + 0x8000; =20 #ifdef TARGET_X86_64 for (i =3D 0; i < 6; i++) { @@ -156,6 +143,25 @@ void do_smm_enter(X86CPU *cpu) x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID); x86_stl_phys(cs, sm_state + 0x7ef8, env->smbase); #endif +} + +void do_smm_enter(X86CPU *cpu) +{ + CPUX86State *env =3D &cpu->env; + + qemu_log_mask(CPU_LOG_INT, "SMM: enter\n"); + log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP); + + env->msr_smi_count++; + env->hflags |=3D HF_SMM_MASK; + if (env->hflags2 & HF2_NMI_MASK) { + env->hflags2 |=3D HF2_SMM_INSIDE_NMI_MASK; + } else { + env->hflags2 |=3D HF2_NMI_MASK; + } + + sm_state_init(cpu); + /* init SMM cpu state */ =20 #ifdef TARGET_X86_64 @@ -191,9 +197,8 @@ void do_smm_enter(X86CPU *cpu) DESC_G_MASK | DESC_A_MASK); } =20 -void helper_rsm(CPUX86State *env) +static void rsm_load_regs(CPUX86State *env) { - X86CPU *cpu =3D env_archcpu(env); CPUState *cs =3D env_cpu(env); target_ulong sm_state; int i, offset; @@ -308,6 +313,14 @@ void helper_rsm(CPUX86State *env) env->smbase =3D x86_ldl_phys(cs, sm_state + 0x7ef8); } #endif +} + +void helper_rsm(CPUX86State *env) +{ + X86CPU *cpu =3D env_archcpu(env); + + rsm_load_regs(env); + if ((env->hflags2 & HF2_SMM_INSIDE_NMI_MASK) =3D=3D 0) { env->hflags2 &=3D ~HF2_NMI_MASK; } --=20 2.53.0 From nobody Fri Apr 3 01:24:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1774440661; cv=none; d=zohomail.com; s=zohoarc; b=gnz0aoWtAL0BwsI89tMorvPz7dbNy9RsZdDI73ULExa0okWXPWy8LnA051cXEIDHvViPm1+1ueKys8QSb3wEkw0x3KYBKmn21OE0eIBWDIDbgiUnaClxyIm49tof6nsTtU3cJOs6jMqdm8I1BJbXHOfkODn/vtRZHlYoZNk5q+4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774440661; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Wed, 25 Mar 2026 12:09:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1774440596; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SdGyZXxwTYuvuSTrhC9NuPS6j2R9Ll8NKs9BQm1mdDs=; b=VxvKfpVHCuXcLigkEhN4uuFb71ipC0ENmwXNPTuD5itQ0C7j6Rfqd4nH2dycpfOWR9LQg0 S7E4vrCXRwjmvsV8DkVEOw/UrjXK3cIRPPfgnrkkGca+E9FK1hUsauztCbnOyb6VKIQ5wb JxF6heasfhfacdcyWDeSawhxb8ssUJY= X-MC-Unique: ZODADJreNj2j6q6vA7L1Aw-1 X-Mimecast-MFC-AGG-ID: ZODADJreNj2j6q6vA7L1Aw_1774440593 From: Thomas Huth To: Paolo Bonzini , qemu-devel@nongnu.org Cc: Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PATCH 2/2] target/i386/tcg/sysemu: Allow 32-bit SMM code to be used in the 64-bit binary Date: Wed, 25 Mar 2026 13:09:44 +0100 Message-ID: <20260325120944.29391-3-thuth@redhat.com> In-Reply-To: <20260325120944.29391-1-thuth@redhat.com> References: <20260325120944.29391-1-thuth@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Thomas Huth This is a preparation for the QEMU universal binary where we might want to support both, the x86_64 and the i386 target, in one binary. Instead of using #ifdef TARGET_X86_64 here, check the LM bit to select the 32-bit or 64-bit code during runtime. Signed-off-by: Thomas Huth --- target/i386/tcg/system/smm_helper.c | 65 +++++++++++++++++++---------- 1 file changed, 43 insertions(+), 22 deletions(-) diff --git a/target/i386/tcg/system/smm_helper.c b/target/i386/tcg/system/s= mm_helper.c index 3be78cd53d3..4bbe18a86fb 100644 --- a/target/i386/tcg/system/smm_helper.c +++ b/target/i386/tcg/system/smm_helper.c @@ -23,24 +23,15 @@ #include "exec/log.h" #include "tcg/helper-tcg.h" =20 - -/* SMM support */ - -#ifdef TARGET_X86_64 -#define SMM_REVISION_ID 0x00020064 -#else -#define SMM_REVISION_ID 0x00020000 -#endif - -static void sm_state_init(X86CPU *cpu) +static void sm_state_init_64(X86CPU *cpu) { +#ifdef TARGET_X86_64 CPUX86State *env =3D &cpu->env; CPUState *cs =3D CPU(cpu); SegmentCache *dt; int i, offset; target_ulong sm_state =3D env->smbase + 0x8000; =20 -#ifdef TARGET_X86_64 for (i =3D 0; i < 6; i++) { dt =3D &env->segs[i]; offset =3D 0x7e00 + i * 16; @@ -92,9 +83,21 @@ static void sm_state_init(X86CPU *cpu) x86_stq_phys(cs, sm_state + 0x7f50, env->cr[3]); x86_stl_phys(cs, sm_state + 0x7f58, env->cr[0]); =20 - x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID); + x86_stl_phys(cs, sm_state + 0x7efc, 0x00020064); /* SMM revision ID= */ x86_stl_phys(cs, sm_state + 0x7f00, env->smbase); #else + g_assert_not_reached(); +#endif +} + +static void sm_state_init_32(X86CPU *cpu) +{ + CPUX86State *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); + SegmentCache *dt; + int i, offset; + target_ulong sm_state =3D env->smbase + 0x8000; + x86_stl_phys(cs, sm_state + 0x7ffc, env->cr[0]); x86_stl_phys(cs, sm_state + 0x7ff8, env->cr[3]); x86_stl_phys(cs, sm_state + 0x7ff4, cpu_compute_eflags(env)); @@ -140,9 +143,8 @@ static void sm_state_init(X86CPU *cpu) } x86_stl_phys(cs, sm_state + 0x7f14, env->cr[4]); =20 - x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID); + x86_stl_phys(cs, sm_state + 0x7efc, 0x00020000); /* SMM revision ID = */ x86_stl_phys(cs, sm_state + 0x7ef8, env->smbase); -#endif } =20 void do_smm_enter(X86CPU *cpu) @@ -160,13 +162,15 @@ void do_smm_enter(X86CPU *cpu) env->hflags2 |=3D HF2_NMI_MASK; } =20 - sm_state_init(cpu); + if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { + sm_state_init_64(cpu); + cpu_load_efer(env, 0); + } else { + sm_state_init_32(cpu); + } =20 /* init SMM cpu state */ =20 -#ifdef TARGET_X86_64 - cpu_load_efer(env, 0); -#endif cpu_load_eflags(env, 0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)); env->eip =3D 0x00008000; @@ -197,15 +201,16 @@ void do_smm_enter(X86CPU *cpu) DESC_G_MASK | DESC_A_MASK); } =20 -static void rsm_load_regs(CPUX86State *env) +static void rsm_load_regs_64(CPUX86State *env) { +#ifdef TARGET_X86_64 CPUState *cs =3D env_cpu(env); target_ulong sm_state; int i, offset; uint32_t val; =20 sm_state =3D env->smbase + 0x8000; -#ifdef TARGET_X86_64 + cpu_load_efer(env, x86_ldq_phys(cs, sm_state + 0x7ed0)); =20 env->gdt.base =3D x86_ldq_phys(cs, sm_state + 0x7e68); @@ -260,6 +265,19 @@ static void rsm_load_regs(CPUX86State *env) env->smbase =3D x86_ldl_phys(cs, sm_state + 0x7f00); } #else + g_assert_not_reached(); +#endif +} + +static void rsm_load_regs_32(CPUX86State *env) +{ + CPUState *cs =3D env_cpu(env); + target_ulong sm_state; + int i, offset; + uint32_t val; + + sm_state =3D env->smbase + 0x8000; + cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7ffc)); cpu_x86_update_cr3(env, x86_ldl_phys(cs, sm_state + 0x7ff8)); cpu_load_eflags(env, x86_ldl_phys(cs, sm_state + 0x7ff4), @@ -312,14 +330,17 @@ static void rsm_load_regs(CPUX86State *env) if (val & 0x20000) { env->smbase =3D x86_ldl_phys(cs, sm_state + 0x7ef8); } -#endif } =20 void helper_rsm(CPUX86State *env) { X86CPU *cpu =3D env_archcpu(env); =20 - rsm_load_regs(env); + if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { + rsm_load_regs_64(env); + } else { + rsm_load_regs_32(env); + } =20 if ((env->hflags2 & HF2_SMM_INSIDE_NMI_MASK) =3D=3D 0) { env->hflags2 &=3D ~HF2_NMI_MASK; --=20 2.53.0