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b=N3LqF6bcKAXiNmvS8ZXjxORJlyd8e2ipvMowzWlidJ0TlktYP/ONubpgv3N2CRshIK9ihIutCZjyaema0xdHJoPhIkGvdVinAzM8NvdTc/bT043uwJsH4T/66qpyR5/BcRT+yhhqhEkfh+hL7TrBWm6N2x5qnCKeWVqYoSzOdisY2dNC9x4cVcN0WScfF2NZB1ogOQHkl3A37jf2QPzkkWhMZ9hjCjvqETllK8dDSQyD52FFyG7vzHSn8svKSIRChc+EV6TT5RcYssCE7GZhtz3OpIPC/TSsWLnEpWdCkPwSsS0+eg5hSXL5j/zPollBiFAvazYDXasW8hG8prX9KQ== From: Djordje Todorovic To: "qemu-devel@nongnu.org" CC: "qemu-riscv@nongnu.org" , "cfu@mips.com" , "mst@redhat.com" , "marcel.apfelbaum@gmail.com" , "dbarboza@ventanamicro.com" , "philmd@linaro.org" , "alistair23@gmail.com" , "thuth@redhat.com" , Djordje Todorovic Subject: [PATCH v5 4/7] hw/riscv: Make boot code endianness-aware at runtime Thread-Topic: [PATCH v5 4/7] hw/riscv: Make boot code endianness-aware at runtime Thread-Index: AQHcu6zkp4dl2F3i9UaTc6hdecuzUQ== Date: Tue, 24 Mar 2026 16:40:16 +0000 Message-ID: <20260324164007.549397-5-djordje.todorovic@htecgroup.com> References: <20260324164007.549397-1-djordje.todorovic@htecgroup.com> In-Reply-To: <20260324164007.549397-1-djordje.todorovic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a01:111:f403:c200::1; envelope-from=Djordje.Todorovic@htecgroup.com; helo=DB3PR0202CU003.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @htecgroup.com) X-ZM-MESSAGEID: 1774370521172154100 Content-Type: text/plain; charset="utf-8" Add riscv_is_big_endian() helper that checks the hart's big-endian CPU property and use it throughout the boot code: - ELF loading: pass ELFDATA2MSB or ELFDATA2LSB based on endianness - Firmware dynamic info: use cpu_to_be* or cpu_to_le* based on endianness - Reset vector: instructions (entries 0-5) remain always little-endian, data words (entries 6-9) use target data endianness. For RV64 BE, the hi/lo word pairs within each dword are swapped since LD reads as BE. This is part of the runtime big-endian support series which avoids separate BE binaries by handling endianness as a CPU property. Signed-off-by: Djordje Todorovic --- hw/riscv/boot.c | 82 +++++++++++++++++++++++++++++++++++------ include/hw/riscv/boot.h | 2 + 2 files changed, 72 insertions(+), 12 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index e5490beda0..c7558b904f 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -40,6 +40,28 @@ bool riscv_is_32bit(RISCVHartArrayState *harts) return mcc->def->misa_mxl_max =3D=3D MXL_RV32; } =20 +bool riscv_is_big_endian(RISCVHartArrayState *harts) +{ + return harts->harts[0].cfg.big_endian; +} + +/* + * Convert a pair of 32-bit words forming a 64-bit dword to target data + * endianness. For big-endian, the hi/lo word order is swapped since LD + * interprets bytes as BE. + */ +static void riscv_boot_data_dword(uint32_t *data, bool big_endian) +{ + if (big_endian) { + uint32_t tmp =3D data[0]; + data[0] =3D cpu_to_be32(data[1]); + data[1] =3D cpu_to_be32(tmp); + } else { + data[0] =3D cpu_to_le32(data[0]); + data[1] =3D cpu_to_le32(data[1]); + } +} + /* * Return the per-socket PLIC hart topology configuration string * (caller must free with g_free()) @@ -72,6 +94,7 @@ void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartA= rrayState *harts) info->kernel_size =3D 0; info->initrd_size =3D 0; info->is_32bit =3D riscv_is_32bit(harts); + info->is_big_endian =3D riscv_is_big_endian(harts); } =20 vaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info, @@ -247,8 +270,9 @@ void riscv_load_kernel(MachineState *machine, */ kernel_size =3D load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, NU= LL, &info->image_low_addr, &info->image_hig= h_addr, - NULL, ELFDATA2LSB, EM_RISCV, - 1, 0, NULL, true, sym_cb); + NULL, + ELFDATA2LSB, + EM_RISCV, 1, 0, NULL, true, sym_cb); if (kernel_size > 0) { info->kernel_size =3D kernel_size; goto out; @@ -391,21 +415,32 @@ void riscv_rom_copy_firmware_info(MachineState *machi= ne, struct fw_dynamic_info64 dinfo64; void *dinfo_ptr =3D NULL; size_t dinfo_len; + bool big_endian =3D riscv_is_big_endian(harts); =20 if (riscv_is_32bit(harts)) { - dinfo32.magic =3D cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE); - dinfo32.version =3D cpu_to_le32(FW_DYNAMIC_INFO_VERSION); - dinfo32.next_mode =3D cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S); - dinfo32.next_addr =3D cpu_to_le32(kernel_entry); + dinfo32.magic =3D big_endian ? cpu_to_be32(FW_DYNAMIC_INFO_MAGIC_V= ALUE) + : cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VAL= UE); + dinfo32.version =3D big_endian ? cpu_to_be32(FW_DYNAMIC_INFO_VERSI= ON) + : cpu_to_le32(FW_DYNAMIC_INFO_VERSION= ); + dinfo32.next_mode =3D big_endian + ? cpu_to_be32(FW_DYNAMIC_INFO_NEXT_MODE_S) + : cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S); + dinfo32.next_addr =3D big_endian ? cpu_to_be32(kernel_entry) + : cpu_to_le32(kernel_entry); dinfo32.options =3D 0; dinfo32.boot_hart =3D 0; dinfo_ptr =3D &dinfo32; dinfo_len =3D sizeof(dinfo32); } else { - dinfo64.magic =3D cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE); - dinfo64.version =3D cpu_to_le64(FW_DYNAMIC_INFO_VERSION); - dinfo64.next_mode =3D cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S); - dinfo64.next_addr =3D cpu_to_le64(kernel_entry); + dinfo64.magic =3D big_endian ? cpu_to_be64(FW_DYNAMIC_INFO_MAGIC_V= ALUE) + : cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VAL= UE); + dinfo64.version =3D big_endian ? cpu_to_be64(FW_DYNAMIC_INFO_VERSI= ON) + : cpu_to_le64(FW_DYNAMIC_INFO_VERSION= ); + dinfo64.next_mode =3D big_endian + ? cpu_to_be64(FW_DYNAMIC_INFO_NEXT_MODE_S) + : cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S); + dinfo64.next_addr =3D big_endian ? cpu_to_be64(kernel_entry) + : cpu_to_le64(kernel_entry); dinfo64.options =3D 0; dinfo64.boot_hart =3D 0; dinfo_ptr =3D &dinfo64; @@ -474,10 +509,33 @@ void riscv_setup_rom_reset_vec(MachineState *machine,= RISCVHartArrayState *harts reset_vec[2] =3D 0x00000013; /* addi x0, x0, 0 */ } =20 - /* copy in the reset vector in little_endian byte order */ - for (i =3D 0; i < ARRAY_SIZE(reset_vec); i++) { + /* RISC-V instructions are always little-endian */ + for (i =3D 0; i < 6; i++) { reset_vec[i] =3D cpu_to_le32(reset_vec[i]); } + + /* + * Data words (addresses at entries 6-9) must match the firmware's data + * endianness. + */ + if (riscv_is_32bit(harts)) { + for (i =3D 6; i < ARRAY_SIZE(reset_vec); i++) { + if (riscv_is_big_endian(harts)) { + reset_vec[i] =3D cpu_to_be32(reset_vec[i]); + } else { + reset_vec[i] =3D cpu_to_le32(reset_vec[i]); + } + } + } else { + /* + * For RV64, each pair of 32-bit words forms a dword. For big-endi= an, + * the hi/lo word order within each dword must be swapped since LD + * interprets bytes as BE. + */ + for (i =3D 6; i < ARRAY_SIZE(reset_vec); i +=3D 2) { + riscv_boot_data_dword(reset_vec + i, riscv_is_big_endian(harts= )); + } + } rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), rom_base, &address_space_memory); riscv_rom_copy_firmware_info(machine, harts, diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index f00b3ca122..a54c2b397d 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -36,9 +36,11 @@ typedef struct RISCVBootInfo { ssize_t initrd_size; =20 bool is_32bit; + bool is_big_endian; } RISCVBootInfo; =20 bool riscv_is_32bit(RISCVHartArrayState *harts); +bool riscv_is_big_endian(RISCVHartArrayState *harts); =20 char *riscv_plic_hart_config_string(int hart_count); =20 --=20 2.34.1