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b=jHB9Wq2LZnkjaQdvMLqxgmCnNE1yoI0v45tq+eWseizOx+u9Mhqwi6uUgGatA7bTTTE7lbfmb75mEywWgJ5/TALbRXbcD3T4IEO3R2SfriAfY10qwqj1fZmeFry1fdheTFotJpkYmkY7FoOPax+l9zYUgmuJpPxr+7GMl0rr7SBV6B935xEEKca2PIB6qUCcTvKvrw0MkmXRLRXD5U30CMc9nkXUjbbnvnI+Ojna1TugMqEyYohWpyBQFuSnYgodQa+FNGKN2WXZzOb5B7UIBWEugmAtboI6XhU+Qn4q2r71DR9WaxSPi1Wzotk5umpHX4JFMm/lJwP1/VhPG6CTVA== From: Djordje Todorovic To: "qemu-devel@nongnu.org" CC: "qemu-riscv@nongnu.org" , "cfu@mips.com" , "mst@redhat.com" , "marcel.apfelbaum@gmail.com" , "dbarboza@ventanamicro.com" , "philmd@linaro.org" , "alistair23@gmail.com" , "thuth@redhat.com" , Djordje Todorovic Subject: [PATCH v5 3/7] target/riscv: Implement runtime data endianness via MSTATUS bits Thread-Topic: [PATCH v5 3/7] target/riscv: Implement runtime data endianness via MSTATUS bits Thread-Index: AQHcu6zkMXwXI9vy0EubjyivhQYRHA== Date: Tue, 24 Mar 2026 16:40:16 +0000 Message-ID: <20260324164007.549397-4-djordje.todorovic@htecgroup.com> References: <20260324164007.549397-1-djordje.todorovic@htecgroup.com> In-Reply-To: <20260324164007.549397-1-djordje.todorovic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a01:111:f403:c200::1; envelope-from=Djordje.Todorovic@htecgroup.com; helo=DB3PR0202CU003.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @htecgroup.com) X-ZM-MESSAGEID: 1774370547696154100 Content-Type: text/plain; charset="utf-8" Implement runtime big-endian data support by reading the MSTATUS UBE/SBE/MBE bits to determine data endianness per privilege level. The key changes are: - Add riscv_cpu_data_is_big_endian() helper in cpu.h that checks the appropriate MSTATUS endianness bit based on current privilege level (MBE for M-mode, SBE for S-mode, UBE for U-mode). - Update mo_endian() in translate.c to return MO_BE or MO_LE based on a new 'big_endian' field in DisasContext, rather than the previous hardcoded MO_TE. - Update mo_endian_env() in op_helper.c to call the new helper, giving hypervisor load/store helpers correct runtime endianness. - Pack the endianness flag into cs_base bit 32 (alongside misa_ext in bits 0-25) in riscv_get_tb_cpu_state(), ensuring translation blocks are correctly separated by data endianness. Note: instruction fetches continue to use MO_LE unconditionally (from the previous patch), as RISC-V instructions are always little-endian per the ISA specification. Signed-off-by: Djordje Todorovic --- target/riscv/cpu.h | 28 ++++++++++++++++++++++++++++ target/riscv/internals.h | 9 +-------- target/riscv/tcg/tcg-cpu.c | 9 ++++++++- target/riscv/translate.c | 12 ++++-------- 4 files changed, 41 insertions(+), 17 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 35d1f6362c..ef870d05b3 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -703,6 +703,12 @@ FIELD(TB_FLAGS, BCFI_ENABLED, 28, 1) FIELD(TB_FLAGS, PM_PMM, 29, 2) FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1) =20 +/* + * cs_base carries misa_ext (bits 0-25) plus additional flags. + * Bit 32 is used for data endianness since TB_FLAGS has no free bits. + */ +#define TB_CSBASE_BIG_ENDIAN (1ULL << 32) + #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) #else @@ -718,6 +724,28 @@ static inline const RISCVCPUConfig *riscv_cpu_cfg(CPUR= ISCVState *env) return &env_archcpu(env)->cfg; } =20 +/* + * Return true if data accesses are big-endian for the current privilege + * level, based on the MSTATUS MBE/SBE/UBE bits. + */ +static inline bool riscv_cpu_data_is_big_endian(CPURISCVState *env) +{ +#if defined(CONFIG_USER_ONLY) + return false; +#else + switch (env->priv) { + case PRV_M: + return env->mstatus & MSTATUS_MBE; + case PRV_S: + return env->mstatus & MSTATUS_SBE; + case PRV_U: + return env->mstatus & MSTATUS_UBE; + default: + g_assert_not_reached(); + } +#endif +} + #if !defined(CONFIG_USER_ONLY) static inline int cpu_address_mode(CPURISCVState *env) { diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 460346dd6d..e2f0334da8 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -64,14 +64,7 @@ static inline bool mmuidx_2stage(int mmu_idx) =20 static inline MemOp mo_endian_env(CPURISCVState *env) { - /* - * A couple of bits in MSTATUS set the endianness: - * - MSTATUS_UBE (User-mode), - * - MSTATUS_SBE (Supervisor-mode), - * - MSTATUS_MBE (Machine-mode) - * but we don't implement that yet. - */ - return MO_LE; + return riscv_cpu_data_is_big_endian(env) ? MO_BE : MO_LE; } =20 /* share data between vector helpers and decode code */ diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 3407191c22..fa42197e98 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -189,10 +189,17 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState = *cs) flags =3D FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); flags =3D FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); =20 + uint64_t cs_base =3D env->misa_ext; +#ifndef CONFIG_USER_ONLY + if (riscv_cpu_data_is_big_endian(env)) { + cs_base |=3D TB_CSBASE_BIG_ENDIAN; + } +#endif + return (TCGTBCPUState){ .pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc, .flags =3D flags, - .cs_base =3D env->misa_ext, + .cs_base =3D cs_base, }; } =20 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 5df5b73849..d7f1f8e466 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -119,6 +119,8 @@ typedef struct DisasContext { bool fcfi_lp_expected; /* zicfiss extension, if shadow stack was enabled during TB gen */ bool bcfi_enabled; + /* Data endianness from MSTATUS UBE/SBE/MBE */ + bool big_endian; } DisasContext; =20 static inline bool has_ext(DisasContext *ctx, uint32_t ext) @@ -128,14 +130,7 @@ static inline bool has_ext(DisasContext *ctx, uint32_t= ext) =20 static inline MemOp mo_endian(DisasContext *ctx) { - /* - * A couple of bits in MSTATUS set the endianness: - * - MSTATUS_UBE (User-mode), - * - MSTATUS_SBE (Supervisor-mode), - * - MSTATUS_MBE (Machine-mode) - * but we don't implement that yet. - */ - return MO_LE; + return ctx->big_endian ? MO_BE : MO_LE; } =20 #ifdef TARGET_RISCV32 @@ -1346,6 +1341,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->zero =3D tcg_constant_tl(0); ctx->virt_inst_excp =3D false; ctx->decoders =3D cpu->decoders; + ctx->big_endian =3D ctx->base.tb->cs_base & TB_CSBASE_BIG_ENDIAN; } =20 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) --=20 2.34.1