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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.78.66; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1774365402959154100 Content-Type: text/plain; charset="utf-8" Now that there's an on-demand interface for fetching CRs and segments, only query GPRs and query everything else on-demand for vmexits. Signed-off-by: Mohamed Mediouni --- target/i386/whpx/whpx-all.c | 77 +++++++++++++++++++++++++++++++++---- 1 file changed, 70 insertions(+), 7 deletions(-) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 6f23278642..acae61e089 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -156,6 +156,26 @@ static const WHV_REGISTER_NAME whpx_register_names[] = =3D { */ }; =20 +static const WHV_REGISTER_NAME whpx_register_names_for_vmexit[] =3D { + /* X64 General purpose registers */ + WHvX64RegisterRax, + WHvX64RegisterRcx, + WHvX64RegisterRdx, + WHvX64RegisterRbx, + WHvX64RegisterRsp, + WHvX64RegisterRbp, + WHvX64RegisterRsi, + WHvX64RegisterRdi, + WHvX64RegisterR8, + WHvX64RegisterR9, + WHvX64RegisterR10, + WHvX64RegisterR11, + WHvX64RegisterR12, + WHvX64RegisterR13, + WHvX64RegisterR14, + WHvX64RegisterR15, +}; + struct whpx_register_set { WHV_REGISTER_VALUE values[RTL_NUMBER_OF(whpx_register_names)]; }; @@ -593,6 +613,47 @@ static void whpx_get_xcrs(CPUState *cpu) cpu_env(cpu)->xcr0 =3D xcr0.Reg64; } =20 +static void whpx_get_registers_for_vmexit(CPUState *cpu, WHPXStateLevel le= vel) +{ + struct whpx_state *whpx =3D &whpx_global; + AccelCPUState *vcpu =3D cpu->accel; + X86CPU *x86_cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86_cpu->env; + struct whpx_register_set vcxt; + HRESULT hr; + int idx; + int idx_next; + + assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu)); + + hr =3D whp_dispatch.WHvGetVirtualProcessorRegisters( + whpx->partition, cpu->cpu_index, + whpx_register_names_for_vmexit, + RTL_NUMBER_OF(whpx_register_names_for_vmexit), + &vcxt.values[0]); + if (FAILED(hr)) { + error_report("WHPX: Failed to get virtual processor context, hr=3D= %08lx", + hr); + } + + idx =3D 0; + + /* Indexes for first 16 registers match between HV and QEMU definition= s */ + idx_next =3D 16; + for (idx =3D 0; idx < CPU_NB_REGS; idx +=3D 1) { + env->regs[idx] =3D vcxt.values[idx].Reg64; + } + idx =3D idx_next; + + env->eip =3D vcpu->exit_ctx.VpContext.Rip; + env->eflags =3D vcpu->exit_ctx.VpContext.Rflags; + rflags_to_lflags(env); + + assert(idx =3D=3D RTL_NUMBER_OF(whpx_register_names_for_vmexit)); + + x86_update_hflags(env); +} + void whpx_get_registers(CPUState *cpu, WHPXStateLevel level) { struct whpx_state *whpx =3D &whpx_global; @@ -608,7 +669,11 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel = level) =20 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu)); =20 - if (level > WHPX_LEVEL_FAST_RUNTIME_STATE && !env->tsc_valid) { + if (level =3D=3D WHPX_LEVEL_FAST_RUNTIME_STATE) { + return whpx_get_registers_for_vmexit(cpu, level); + } + + if (!env->tsc_valid) { whpx_get_tsc(cpu); env->tsc_valid =3D !runstate_is_running(); } @@ -623,7 +688,7 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel l= evel) hr); } =20 - if (level > WHPX_LEVEL_FAST_RUNTIME_STATE && whpx_irqchip_in_kernel())= { + if (whpx_irqchip_in_kernel()) { /* * Fetch the TPR value from the emulated APIC. It may get overwrit= ten * below with the value from CR8 returned by @@ -680,7 +745,7 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel l= evel) env->cr[4] =3D vcxt.values[idx++].Reg64; assert(whpx_register_names[idx] =3D=3D WHvX64RegisterCr8); tpr =3D vcxt.values[idx++].Reg64; - if (level > WHPX_LEVEL_FAST_RUNTIME_STATE && tpr !=3D vcpu->tpr) { + if (tpr !=3D vcpu->tpr) { vcpu->tpr =3D tpr; cpu_set_apic_tpr(x86_cpu->apic_state, whpx_cr8_to_apic_tpr(tpr)); } @@ -691,9 +756,7 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel l= evel) * Extended control registers needs to be handled separately depending * on whether xsave is supported/enabled or not. */ - if (level > WHPX_LEVEL_FAST_RUNTIME_STATE) { - whpx_get_xcrs(cpu); - } + whpx_get_xcrs(cpu); =20 /* 16 XMM registers */ assert(whpx_register_names[idx] =3D=3D WHvX64RegisterXmm0); @@ -768,7 +831,7 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel l= evel) =20 assert(idx =3D=3D RTL_NUMBER_OF(whpx_register_names)); =20 - if (level > WHPX_LEVEL_FAST_RUNTIME_STATE && whpx_irqchip_in_kernel())= { + if (whpx_irqchip_in_kernel()) { whpx_apic_get(x86_cpu->apic_state); } =20 --=20 2.50.1 (Apple Git-155)