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Reviewed-by: Eric Auger Tested-by: Eric Auger Reviewed-by: Shameer Kolothum Tested-by: Shameer Kolothum Signed-off-by: Nathan Chen Message-id: 20260323182454.1416110-9-nathanc@nvidia.com Signed-off-by: Peter Maydell --- qemu-options.hx | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/qemu-options.hx b/qemu-options.hx index dbcb0155ba..21972f8326 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -1279,13 +1279,43 @@ SRST ``aw-bits=3Dval`` (val between 32 and 64, default depends on machine) This decides the address width of the IOVA address space. =20 -``-device arm-smmuv3,primary-bus=3Did`` +``-device arm-smmuv3,primary-bus=3Did[,option=3D...]`` This is only supported by ``-machine virt`` (ARM). =20 ``primary-bus=3Did`` Accepts either the default root complex (pcie.0) or a pxb-pcie based root complex. =20 + ``accel=3Don|off`` (default: off) + Enables guest to leverage host SMMUv3 features for acceleration. + Enabling accel configures the host SMMUv3 in nested mode to support + vfio-pci passthrough. + + The following options are available when accel=3Don. + Note: 'auto' mode is not currently supported. + + ``ril=3Don|off`` (default: on) + Support for Range Invalidation, which allows the SMMUv3 driver to + invalidate TLB entries for a range of IOVAs at once instead of iss= uing + separate commands to invalidate each page. Must match with host SM= MUv3 + Range Invalidation support. + + ``ats=3Don|off`` (default: off) + Support for Address Translation Services, which enables PCIe devic= es to + cache address translations in their local TLB and reduce latency. = Host + SMMUv3 must support ATS in order to enable this feature for the vI= OMMU. + + ``oas=3Dval`` (supported values are 44 and 48. default: 44) + Sets the Output Address Size in bits. The value set here must be l= ess + than or equal to the host SMMUv3's supported OAS, so that the + intermediate physical addresses (IPA) consumed by host SMMU for st= age-2 + translation do not exceed the host's max supported IPA size. + + ``ssidsize=3Dval`` (val between 0 and 20. default: 0) + Sets the Substream ID size in bits. When set to a non-zero value, + PASID capability is advertised to the vIOMMU and accelerated use c= ases + such as Shared Virtual Addressing (SVA) are supported. + ``-device amd-iommu[,option=3D...]`` Enables emulation of an AMD-Vi I/O Memory Management Unit (IOMMU). Only available with ``-machine q35``, it supports the following option= s: --=20 2.43.0