From nobody Fri Apr 3 08:36:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774365138; cv=none; d=zohomail.com; s=zohoarc; b=e7HbOT8BuLV8SHtNAq/q/oD0tgkoySOD+zsrFQylKslUoDsU/pGi0+6q8YviSks6Y5s7abrFbgpYWTQYuhYBV2B55lxtKa5rKQcazQj45El841fLvTMS3c3zhqp0QVu2Zwh2oh5SPNvAQnU4cC+dhp9z1oVLW4LzUiOCuqB0a4M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774365138; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=ErylgoX7rGE2MPVTc4vGOkn7Dc6WAKHtKwRhn5S4AVo=; b=DbnGmu4atJqnaFngSjD8Tp+FnsC17iizzqkYCnegULw4/M/YEHX/fJCt2QxugTnsbMMS0hGakpiaR94pZQetpM1ovOYKsnsOBc4ZqIZe+S33C6tlDN6N5rIkjAt5Je9K/R3j2x0R3hzMCGbk/DbwLWNxiuP9ptuC3laG5ZqAYig= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774365138149283.8015210749875; Tue, 24 Mar 2026 08:12:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w53Pn-0000mm-6q; Tue, 24 Mar 2026 11:11:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w53Pb-0000bO-EZ for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:19 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w53PY-0005Bj-IJ for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:19 -0400 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-439c6fc2910so1102928f8f.0 for ; Tue, 24 Mar 2026 08:11:16 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b64717e97sm40781916f8f.35.2026.03.24.08.11.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Mar 2026 08:11:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774365075; x=1774969875; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ErylgoX7rGE2MPVTc4vGOkn7Dc6WAKHtKwRhn5S4AVo=; b=bTpInedDvaJq6S2mpiFeeED3lHQ42LBoqkiNUDlKqkLam1LRy8YhpddzftR4HYyZJG +AeZvSkR8SbQj29xU2iFS8TKVskX1mrxCgp58w7gfHeyCaP/F22n9ZKFl/VDNMGVPGPK hMvZ730JDaR6iDEKubaAta8Q18OksMi5MoVgF9xtJ4bE0SRhM/mDAw4KA8oTeyOQPNbg aMMdTaV6OTLuYqrbCxAaxQcpdITHE/ZpRs83KwC2sTeBrlTfmoq6jApYa9hltkzXwKVE rqnmEGI0hfTC0aw4Bw4GCBaNRYml6lUV6jSpwN5mH6BQBWCMAwD4Mjyzv4OwVq1VAAKS lpfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774365075; x=1774969875; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=ErylgoX7rGE2MPVTc4vGOkn7Dc6WAKHtKwRhn5S4AVo=; b=VgKYsEVIo9KI/FxrfOhxesxGUtpXw+BUiwt48J+ZMrUWKrCr6PyH9E3GBumSDi03gK 8XE+X0vwRKlP9eU4cyKJ+pWeV2CYbe1ziWM9Su8C5DQRPXvKJ5oizxNb1tLUZsftfLcx 1a+YV1NpI2LHtJtpoPgseNzzIkgxfzhH+x3HGjntp6OTyOTrb/inuWD8ZCiyEY07VlRS 08zxvwCBUojyY5eRjmwZ7FusbaWwiUehRU5TjUmwPMevx7kwXrtZaxAT7gqySmmN0DHx zStUgDyLPlPA+2Ms80Sa/HvpwVMxgQAZKh3e9C/df3g3TXzwUopKItu1Ny+2duQK8bmW 6NLA== X-Gm-Message-State: AOJu0YyM76VXjQTWEWMJWU7bkd/Yrw6JIOvMFfN34ThrEZEFZUgV0O8t Fw1dDkovrau4RLgGizy3LAohiS/xY9dGo0uJS+iFUI4j5FDCMozmopPM186Zt94Ntv/9qj+QHtQ oqT972tA= X-Gm-Gg: ATEYQzzXFungrCjnVRDId4mR7cYxWLdodGmbKQi+emIwANcFvKEW8LOXRroy3FUG2Jo J8wn8LOth+9jUGpxcSVb1K1+bT+9gITOE3i5HS3E+UfZyrtLY2xKeIRCwjSOF3D7OTxqRYQl3zs EIqtTi4uHFTicii3XPqkvnSa+o08K8FeifAKOd7bVA8FyB9zHEVFTBHmadtCjG9qpAtfIK7ndVE h/Q0mCdwsnY8bIWZVF78JamdH4DWS8hzAyjSnA8fOgoCUMh+i+DyNkgH0cGaiUY+x6Rdi9/V5Yk 8C76d7zh+v5Bfr30O20LQ1W3lE9yftfhvFqOMN7Hntctb9n+96KvYhBsoC80cCeer9KAYAXEfq1 vWdiE30O9l1jnXZ2SVpiKOkwUfkvg8PF5ZiWVqQRzsu53mC8BZWRxu6ndrYQdsRVSq6maGolupz Z9+n0YYvyMeLBhf5Ch/8nt3X6QbysjI/ugba73vooSTzKfDafkHCKoROb4tWaZI2mw26x+/CQoR u9ri+rSnfQjt1UIp+GICtkNKaKiqGg= X-Received: by 2002:a5d:5d82:0:b0:439:b3ff:9ab9 with SMTP id ffacd0b85a97d-43b642919b2mr26523385f8f.48.1774365074750; Tue, 24 Mar 2026 08:11:14 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/11] target/arm: fix s2prot not set for two-stage PMSA translations Date: Tue, 24 Mar 2026 15:11:01 +0000 Message-ID: <20260324151111.237411-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260324151111.237411-1-peter.maydell@linaro.org> References: <20260324151111.237411-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774365140272158500 Content-Type: text/plain; charset="utf-8" From: Jose Martins Commit a811c5dafb7 ("target/arm: Implement get_S2prot_indirect") changed get_phys_addr_twostage() to combine stage 1 and stage 2 permissions using the new s2prot field: result->f.prot =3D s1_prot & result->s2prot; The LPAE stage 2 path sets result->s2prot explicitly, but the PMSA stage 2 path (get_phys_addr_pmsav8) only sets result->f.prot, leaving s2prot at zero. This causes the combined permission to be zero, resulting in addr_read being set to -1 in the TLB entry and triggering an assertion in atomic_mmu_lookup() when the guest executes an atomic instruction on a two-stage PMSA platform (e.g. Cortex-R52 with EL2). Set s2prot from f.prot after the PMSA stage 2 lookup, consistent with what the LPAE path does. Cc: qemu-stable@nongnu.org Fixes: a811c5dafb7 ("target/arm: Implement get_S2prot_indirect") Signed-off-by: Jose Martins [PMM: refer to the right commit in the commit message] Reviewed-by: Peter Maydell Message-id: 20260321231916.2852653-1-josemartins90@gmail.com Reviewed-by: Gustavo Romero Signed-off-by: Peter Maydell --- target/arm/ptw.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8b8dc09e72..e289f88124 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3200,6 +3200,13 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, =20 ret =3D pmsav8_mpu_lookup(env, address, access_type, ptw->in_prot_chec= k, mmu_idx, secure, result, fi, NULL); + /* + * For two-stage PMSA translations, s2prot holds the stage 2 + * permissions to be combined with stage 1 in get_phys_addr_twostage(). + */ + if (regime_is_stage2(mmu_idx)) { + result->s2prot =3D result->f.prot; + } if (sattrs.subpage) { result->f.lg_page_size =3D 0; } --=20 2.43.0 From nobody Fri Apr 3 08:36:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774365141; cv=none; d=zohomail.com; s=zohoarc; b=BC9gYPWrfCTatsw7vBDn3r5JlmqyEreilhj3rl+67hhCN1clj1lSQGUkqZjDuKQgEE1qaRJXvN4/9YF8tdCL8njPfvIhOj2b33aPOnFazY55CPYWL2aeQo57+g3Es0cR+SZNcgzD/Ktvn8dc9PndR+JUet/VAu46h3aP0vxGi5s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774365141; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=IKbUTaFOqvDJxELefvnhulrQMMYMDi7DhugEoR6vIwo=; b=ed6zqKeV8T+cO6ZdGjh9e9PXGChZTEI4xzk4fRMGzE9qGlVW/4nvWyjUPv0iq3mP7TKFYgOQPVAY+dTQWAUR8En/eT21/x/zutF8jwFD/0l5PT4EDLzMHIaNq1c1gLhHrwmN5UspUz9xFmNsX1plD1adl0505oWcLwce+jMyi1M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774365141709361.0542417710252; Tue, 24 Mar 2026 08:12:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w53Pi-0000g7-3I; Tue, 24 Mar 2026 11:11:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w53Pb-0000cV-Te for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:20 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w53Pa-0005Br-7Z for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:19 -0400 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-439d8dc4ae4so4843272f8f.2 for ; Tue, 24 Mar 2026 08:11:17 -0700 (PDT) Received: from lanath.. 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We only use this struct definition in the definition of 'struct sigframe', where it is used in a field that is present only for legacy reasons to retain the offset of the following 'extramask' field. So really all that matters is its length, and we do get that right; but our previous definition using X86LegacySaveArea implicitly added an extra alignment constraint (because X86LegacySaveArea is tagged as 16-aligned) which the real target_fpstate_32 does not have. Because we allocate and use a 'struct sigframe' on the guest's stack with the guest's alignment requirements, this resulted in the undefined-behaviour sanitizer complaining during 'make check-tcg' for i386-linux-user: ../../linux-user/i386/signal.c:471:35: runtime error: member access within = misaligned address 0x1000c07f75ec for type 'struct sigframe', which require= s 16 byte alignment 0x1000c07f75ec: note: pointer points here 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00= 00 00 00 00 00 00 00 00 ^ ../../linux-user/i386/signal.c:808:5: runtime error: member access within m= isaligned address 0x1000c07f75f4 for type 'struct target_sigcontext_32', wh= ich requires 8 byte alignment 0x1000c07f75f4: note: pointer points here 0a 00 00 00 33 00 00 00 00 00 00 00 2b 00 00 00 2b 00 00 00 40 05 80 40= f4 7f 10 08 58 05 80 40 ^ and various similar errors. Replace the use of X86LegacyXSaveArea with a set of fields that match the kernel _fpstate_32 struct, and assert that the length is correct. We could equally have used uint8_t legacy_area[512]; but following the kernel is probably less confusing overall. Since in target/i386/cpu.h we assert that X86LegacySaveArea is 512 bytes, and in linux-user/i386/signal.c we assert that target_fregs_state is (32 + 80) bytes, the new assertion confirms that we didn't change the size of target_fpstate_32 here, only its alignment requirements. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20260305161739.1775232-1-peter.maydell@linaro.org --- linux-user/i386/signal.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/linux-user/i386/signal.c b/linux-user/i386/signal.c index 0f11dba831..b646fde431 100644 --- a/linux-user/i386/signal.c +++ b/linux-user/i386/signal.c @@ -60,10 +60,33 @@ struct target_fpx_sw_bytes { }; QEMU_BUILD_BUG_ON(sizeof(struct target_fpx_sw_bytes) !=3D 12*4); =20 +struct fpxreg { + uint16_t significand[4]; + uint16_t exponent; + uint16_t padding[3]; +}; + +struct xmmreg { + uint32_t element[4]; +}; + +/* + * This corresponds to the kernel's _fpstate_32. Since we + * only use it for the fpstate_unused padding section in + * the target sigcontext, it doesn't actually matter what fields + * we define here as long as we get the size right. + */ struct target_fpstate_32 { struct target_fregs_state fpstate; - X86LegacyXSaveArea fxstate; + uint32_t fxsr_env[6]; + uint32_t mxcsr; + uint32_t reserved; + struct fpxreg fxsr_st[8]; + struct xmmreg xmm[8]; + uint32_t padding1[44]; + uint32_t padding2[12]; /* aka sw_reserved */ }; +QEMU_BUILD_BUG_ON(sizeof(struct target_fpstate_32) !=3D 32 + 80 + 512); =20 struct target_sigcontext_32 { uint16_t gs, __gsh; --=20 2.43.0 From nobody Fri Apr 3 08:36:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774365127; cv=none; d=zohomail.com; s=zohoarc; b=EaJjxYxagwTUaSVLpgUOb1TOfywOiOgU3A4P1c5hAQrnFFhyZ7Xvifqc0KamjU6nW82g7P0w6GPXpPqIDiESNZp7CJ8W5Xe9OVdA5zzgegzPhFm5QlLnUEvMR22upt6fyISfjG/lLvh7MA2gp5gMYL5KWSj9z6/DRkec+ZEqbOE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774365127; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=dfNzBGzpTKbGiyXwJIuebHg/gBlotrth/GBr1EmFLrI=; b=JwfdirAPi3NCM0YrLUqK3aGI7fYOModtk7JNNxIvvgFFslCv2hnXj3DPCzRBY9iiewUpQUEo6okLjLky/2LX5t7rKbulZMQ/+FMeDrcwi/+gOgMlHq00RyReWZpMrs4kSLhLYaROt6/xPV6YEga5MzyPaRHNoPSo5YoTFmCJ8Ok= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177436512794839.4176232004437; Tue, 24 Mar 2026 08:12:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w53Pi-0000id-AI; Tue, 24 Mar 2026 11:11:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w53Pd-0000f2-O7 for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:22 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w53Pb-0005C8-Rv for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:21 -0400 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-439b97a8a8cso4338521f8f.1 for ; Tue, 24 Mar 2026 08:11:19 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b64717e97sm40781916f8f.35.2026.03.24.08.11.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Mar 2026 08:11:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774365078; x=1774969878; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=dfNzBGzpTKbGiyXwJIuebHg/gBlotrth/GBr1EmFLrI=; b=L9PQlHij6P2oa62nh/6vI/myNzR7cRrJTW1xJ096HLD5FhpdUdOtrE0wu8WcyoUbz7 /lSqpgn+96ypKo4kN5tp4U8SHXbetno48LZQF+LeRBxZg5chPVdkDJW2o0oB+2bWh6eJ wAfsp2+wRCGFF3AyJJeUoef99ihbcG0M6KsPdCkftkPLAysbw4iv/3jn48TZlFwCbmWz 5AKj1idqc3qaB0zVJ5SjcvKreCfsWl9T5ZUkbax3jqrrjuaBFIouM9YAUEiyFrgsyqMf UnWgDRLxmTFOvtDVmEeyiyykzsPBhmR0hwNa2ybsvE27L9Xil5IUsalXcmi1FwRMQFr0 IEgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774365078; x=1774969878; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=dfNzBGzpTKbGiyXwJIuebHg/gBlotrth/GBr1EmFLrI=; b=Fk2AXkTHFSUXpSCxNN+x5NNDn8IqYRJckO0cK5QPbeY4/OICn35q181ZBWBqlURTCl JGJooyOv4lie917uT524DjI13LYpDhW1OYVmX0trzLpMXyZAUpgJrfB5BgiY6T83NJ90 4fPo4DJMisAEaEX2evNf+RP4ksnAi5xsvDMVBbkZZYN+yCim+QEhhdKNh0s//dKI0PJ4 jCc3iNxsErMFz7WR4sj7CQw25uv6Ih8v54lQnGS4Ylsu2lZoi2Sxif/vLmjtQAGkkFFl NNUifo3M9j5aEuD8gw7A640Z+4EP68BABi024IO9gOPfWIbumzQNxvcu7m4a4VILc8Wj kMMQ== X-Gm-Message-State: AOJu0YxBfwheIDtSsyPk4lkKzIMgd0+uZGwU3v2sBLvSb8pzYMhjlB3K 2npnxZSxd8SbRLoAnYF9Ur8gLwiZ/jRj9c7FK2oTnE8i19tuNwfSgVexZT6jLbfP0CEwoRZDxjX MxEB9WKs= X-Gm-Gg: ATEYQzzbQvboBjeVKqQLCP74EKyrVoEk/ieSlgjloWWo6D47B5JqT4beR/VlNu7/Hrh L6+vXU9wQMIOX5Oy3Zz+NrzJWnv2n4rKC0uYDrlftVUfEygbEpNbaJQKvpsEZh6LllLU9u+4vkS yji3rfapB3BFflygxZnNy+qwTq5lVoSGLPLJoTujUhMS1JRncnQ39cdRfHsSJrljcsbd2ftLMEA XSBrPbTTHWpKf8oUiWo8vX02FQwurnkMFpz04b/mo5PZZfNRPxS+MT4fD11AcVkrMmLnIGqpJ7u aRfZCBjzwF/JcdILtzHtQppfJyb0ecObJhci8KPNuV0u+gq4DOGhXcCKtfnGl0YBweF3o4Vh9pa apBnUD8EZAqYP1MfdqnyGKtmPUg+RzqlIASW2r38HThLb5LExj9t+5d1oCnb8kKHmopBPoVQMyl By/TDFs46B/Cc5AGdshs+rCHqIEGehElnqGaK+UNjBR0NGwTq6LTXsRvp3JvnwQ7Kcm4rEakyks I6uQ5IBVh7UGiUzj7LHggAbTabhzNc= X-Received: by 2002:a05:6000:2c0e:b0:439:b744:c5fe with SMTP id ffacd0b85a97d-43b6427d272mr25436263f8f.52.1774365077977; Tue, 24 Mar 2026 08:11:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/11] hw/dma/pl080: Fix transfer logic in PL080 Date: Tue, 24 Mar 2026 15:11:03 +0000 Message-ID: <20260324151111.237411-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260324151111.237411-1-peter.maydell@linaro.org> References: <20260324151111.237411-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774365128242158500 Content-Type: text/plain; charset="utf-8" From: Tao Ding The logic in the PL080 for transferring data has multiple bugs: * The TransferSize field in the channel control register counts in units of the source width; because our loop may do multiple source loads if the destination width is greater than the source width, we need to decrement it by (xsize / swidth), not by 1, each loop * It is documented in the TRM that it is a software error to program the source and destination width such that SWidth < DWidth and TransferSize * SWidth is not a multiple of DWidth. (This would mean that there isn't enough data to do a full final destination write.) We weren't doing anything sensible with this case. The TRM doesn't document what the hardware actually does (though it drops some hints that suggest that it probably over-reads from the source). * In the loop to write to the destination, each loop adds swidth to ch->dest for each loop and also uses (ch->dest + n) as the destination address. This moves the destination address on further than we should each time round the loop, and also is incrementing ch->dest by swidth when it should be dwidth. This patch fixes these problems: * decrement TransferSize by the correct amount * log and ignore the transfer size mismatch case * correct the loop logic for the destination writes A repro case which exercises some of this is as follows. It configures swidth to 1 byte, dwidth to 4 bytes, and transfer size 4, for a transfer from 0x00000000 to 0x000010000. Examining the destination memory in the QEMU monitor should show that the source data 0x44332211 has all been copied, but before this fix it is not: ./qemu-system-arm -M versatilepb -m 128M -nographic -S \ -device loader,addr=3D0x00000000,data=3D0x44332211,data-len=3D4 \ -device loader,addr=3D0x00001000,data=3D0x00000000,data-len=3D4 \ -device loader,addr=3D0x10130030,data=3D0x00000001,data-len=3D4 \ -device loader,addr=3D0x10130100,data=3D0x00000000,data-len=3D4 \ -device loader,addr=3D0x10130104,data=3D0x00001000,data-len=3D4 \ -device loader,addr=3D0x10130108,data=3D0x00000000,data-len=3D4 \ -device loader,addr=3D0x1013010C,data=3D0x9e47f004,data-len=3D4 \ -device loader,addr=3D0x10130110,data=3D0x0000c001,data-len=3D4 Without this patch the QEMU monitor shows: (qemu) xp /1wx 0x00001000 00001000: 0x00002211 Correct result: (qemu) xp /1wx 0x00001000 00001000: 0x44332211 Cc: qemu-stable@nongnu.org Suggested-by: Peter Maydell Signed-off-by: Tao Ding [PMM: Wrote up what we are fixing in the commit message] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/dma/pl080.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c index 627ccbbd81..4a90c7bb27 100644 --- a/hw/dma/pl080.c +++ b/hw/dma/pl080.c @@ -179,23 +179,28 @@ again: c, extract32(ch->ctrl, 21, 3)); continue; } - - for (n =3D 0; n < dwidth; n+=3D swidth) { + if ((size * swidth) % dwidth) { + qemu_log_mask(LOG_GUEST_ERROR, + "pl080: channel %d: transfer size mismatch: size=3D%d = swidth=3D%d dwidth=3D%d\n", + c, size, swidth, dwidth); + continue; + } + xsize =3D MAX(swidth, dwidth); + for (n =3D 0; n < xsize; n +=3D swidth) { address_space_read(&s->downstream_as, ch->src, MEMTXATTRS_UNSPECIFIED, buff + n, swidt= h); if (ch->ctrl & PL080_CCTRL_SI) ch->src +=3D swidth; } - xsize =3D (dwidth < swidth) ? swidth : dwidth; /* ??? This may pad the value incorrectly for dwidth < 32. */ for (n =3D 0; n < xsize; n +=3D dwidth) { - address_space_write(&s->downstream_as, ch->dest + n, + address_space_write(&s->downstream_as, ch->dest, MEMTXATTRS_UNSPECIFIED, buff + n, dwid= th); if (ch->ctrl & PL080_CCTRL_DI) - ch->dest +=3D swidth; + ch->dest +=3D dwidth; } =20 - size--; + size -=3D xsize / swidth; ch->ctrl =3D (ch->ctrl & 0xfffff000) | size; if (size =3D=3D 0) { /* Transfer complete. */ --=20 2.43.0 From nobody Fri Apr 3 08:36:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774365154; cv=none; d=zohomail.com; s=zohoarc; b=JMOypgs3sMoi1XuBO7EesBR2IY0JXSAVzoiwlR9nNRgdqB1heQWXew+fY7WQq9aBo1WHhuYkm/KtmWg902xtOUAeqD7x43vHiczJUfWH0V/KLwgs75+oi1LmHo6Y9b6y2WqXWSQnYw+w+CPh1x2ebiEV+Gw/T1hMTHjgF/neCgE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774365154; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=X/T6NKMBBCp43C4zrqXDY7PYiA/ptjcwEOPnc9umZvk=; b=Xa/nrCw3DvKg+COmRhs7EvZfJZiYcJkEgbDv/7k5gYipNNtlZz0h7GQXZ9yLsawJWLGFpahFe9fn/OfJMuLNl4QmgLkJ5W0UClA67hXasWMg0E3HJksJSuUpKHPD6fBioo/m1AQEP4Zw8XVLa1a/LFh8gqAlaEW2ST9LEDjhIec= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774365154676789.0381387404506; Tue, 24 Mar 2026 08:12:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w53Pk-0000k4-36; Tue, 24 Mar 2026 11:11:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w53Pe-0000ff-Sq for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:23 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w53Pc-0005CV-R3 for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:22 -0400 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-43b3d9d0695so5025437f8f.0 for ; Tue, 24 Mar 2026 08:11:20 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b64717e97sm40781916f8f.35.2026.03.24.08.11.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Mar 2026 08:11:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774365079; x=1774969879; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=X/T6NKMBBCp43C4zrqXDY7PYiA/ptjcwEOPnc9umZvk=; b=neJ27DWVaK4PjWIEQpN1VX7z7m6/vgICxHUgYFW7QjZgWYSkDp8CmaR6DLBunuCxcL DzyYfgLwdSSh5kz4+N6q3VAh7japAKvxfebz/lmmcmuegz6OgLKmz+5HC632IZWnOmVq OTjr14jzGWTI3g5PL8fJtRsmiCktvGZH5QEW+GiwJiQlqFdfTJkK/oe/BNvcM+0TBRye nt4viAgBH4OlJPbTgTH9AoKRqnc9mpwqsWhQmurCeTAciL8q7nYOQVdqyMsXjURhYbcC VFmfCFvvfCOJU7maDHAI9zmhKn/kIax5Pyee7sHP7mzgf9NAvnVRLyK0k/dnLC9cn8y3 hFxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774365079; x=1774969879; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=X/T6NKMBBCp43C4zrqXDY7PYiA/ptjcwEOPnc9umZvk=; b=df3u4TTNUjiFKZzl4ymlpp8Q5APotjONLDBE9bF4lOIYc+cY/ObmP0S41SdGS6ns3v +ytRUs6mWYDLrW9c9wXXeqWBEZPFmg1EsXLHz9lHbNNTOG0Gm9ozd17JTiTsXNG/eLN5 QxoRT0q7gkpVCadiIjrvwITDs/1MmsW4naoK9NZ88fmKuYCcTx/BJIap81suUamdFf+b FwtWzZh/ium1JjuZMFjEHjipTYosy5NdvMEFTqQankl6ulPFxmsCCMJgWNqYK0Y1nABW AJ8aIu6BkrtzbbKpY1jiBhWsGxEs3rvV20uu/HysQegYZ+26FeHkd5QzmXEBc5PsGiD9 31zA== X-Gm-Message-State: AOJu0YyirB2D/Opo3SPvwf+CCQT3Pn1wckUdhmmT5LW0xGGmPJY+AcOg DwYcUI/16rxXXJN2QHWGgfOw6ID0fSW+eACsiUh5BoOJ23gog0Nfz+QqmBKRxNXitr6mBtuvmGh dEawO/yc= X-Gm-Gg: ATEYQzy1RAHxS8B4ZvOZDMUZc/ZFff2m0FLepro+zFJuRSygHcT+VkZMBQ4H0XUirvW 2DY/5ab3lQ5DlRZEMPqn2JuyMTEPkxpHqt6XQ7HBZl+LuZjKGtoxYQTyWd7YBVOF/74rAl3Ar4Z UNwZth6nTCMB9yxQKxA3kT6i18dNTRTVz7dPU2ItbOaMw461SpMrs962XDSbDHTmb9vOFRUnBLr 6I6R7sc2dej2RfUjSAQFyZpZapRV9zXVyD311zlEi+foDniT0iGnClVBF7Q6DSIJzcz3VREwXG2 tcMpRd/5No0eufo4Y6jUpvXgu3eBdejUyz3tu7/3yqfpxd8ROqw5ofGMDkhdPlB1S9CyZv56oue Jw3UpsVFgPT4hFHgyyBYSQiOsbk18o0pOqU4m3vKx4l4SMVsONeAb3V6SZLyZkrtmaL7Lh4alJ0 bRz0d7yjj7S5JtlVgkWR3n7SQzZW+cHAtsS2SGlg8JEwdRszq/bRmHlinGtVVzHcIYKJku5cKKb 8U7TAhWYyEUj212mwo7UVd4wte3zy0= X-Received: by 2002:a05:6000:4012:b0:437:7719:ca82 with SMTP id ffacd0b85a97d-43b88362a5dmr270000f8f.3.1774365079050; Tue, 24 Mar 2026 08:11:19 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/11] hw/arm/smmuv3-accel: Check ATS compatibility between host and guest Date: Tue, 24 Mar 2026 15:11:04 +0000 Message-ID: <20260324151111.237411-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260324151111.237411-1-peter.maydell@linaro.org> References: <20260324151111.237411-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774365156369158500 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Compare the host SMMUv3 ATS support bit with the guest SMMUv3 ATS support bit in IDR0 and fail the compatibility check if ATS support is opted as enabled on the guest SMMUv3 when it is not supported on host SMMUv3. Fixes: f7f5013a55a3 ("hw/arm/smmuv3-accel: Add support for ATS") Reviewed-by: Eric Auger Tested-by: Eric Auger Reviewed-by: Shameer Kolothum Tested-by: Shameer Kolothum Signed-off-by: Nathan Chen Message-id: 20260323182454.1416110-2-nathanc@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 17306cd04b..2bb142c47f 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -101,6 +101,12 @@ smmuv3_accel_check_hw_compatible(SMMUv3State *s, smmuv3_oas_bits(FIELD_EX32(s->idr[5], IDR5, OAS))); return false; } + /* Check ATS value opted is compatible with Host SMMUv3 */ + if (FIELD_EX32(info->idr[0], IDR0, ATS) < + FIELD_EX32(s->idr[0], IDR0, ATS)) { + error_setg(errp, "Host SMMUv3 doesn't support Address Translation = Services"); + return false; + } =20 /* QEMU SMMUv3 supports GRAN4K/GRAN16K/GRAN64K translation granules */ if (FIELD_EX32(info->idr[5], IDR5, GRAN4K) !=3D --=20 2.43.0 From nobody Fri Apr 3 08:36:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774365139; cv=none; d=zohomail.com; s=zohoarc; b=NDp5QoWqUQr7bsxF0KCfE5r0MyZgKCWNgXZc0sd7qhsEyizEWCouNK8w9scoZ1GqHJEN/Rq7GOu2jVe3xQd2oJ8CH5w153x9NCwgGp+kYmpkiLVG2bsxKjCImPKQuI0UtnDAZmuXoSnGwp1XyZIXncOyfCwQXloNzJRuWVHnN/c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774365139; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=SNjKRlPgyHByobSZXWFL5LbzsZyidVKneZpX7LBz9rs=; b=BRlUPjNzdM7Ul+t13KE5L2bz0JbWSHACJjXIOCR+asIDtnNbuLL5WPnrvEkVVlQEW2jouSxXai5S11Ww6s/wLVtBkirjP/O8xip5s9AAFzgewqeWqGZelcLI8xLHRuBkF76Ur7MulRAusPm8PAKKmjEtwPZp/veA/H6V+vA2xqk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774365139197199.65378215995702; Tue, 24 Mar 2026 08:12:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w53Pk-0000kR-5z; Tue, 24 Mar 2026 11:11:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w53Pg-0000g6-Fe for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:25 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w53Pe-0005Cr-LN for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:24 -0400 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-439af7d77f0so4121617f8f.0 for ; Tue, 24 Mar 2026 08:11:21 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b64717e97sm40781916f8f.35.2026.03.24.08.11.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Mar 2026 08:11:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774365080; x=1774969880; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=SNjKRlPgyHByobSZXWFL5LbzsZyidVKneZpX7LBz9rs=; b=hroRSSoDKLKfSPbhermzzM8azuX8HhT6ZVzAx3LYgxHZQdIPDyCkHSw4e2zaHeMIe0 duTJtdbDrrskFGiP7gpQZkpy0HSom8iCwHBH8+tYZwLFl+kOiW4o8AR2R8sOeHa7x0x0 74ljfpPFLBKyoWAFCCfe0DMqv9+1iDu2I0D6zx65u9hnRUA7zm4GJHtMZb4bRovzRefJ M8BjIa8C53uYXGx0Zfc5s9eTF4HigXbzMIQi8u9H+8EhVD/MTV2s72ERaYJIQzLDofKC ASFym7pc/ycSLxebgSpo+awMb9+ExcrA8j2tuf0/sgkG2FwFU9y3Ru5v5lPCuWYQCLm9 9Lcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774365080; x=1774969880; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=SNjKRlPgyHByobSZXWFL5LbzsZyidVKneZpX7LBz9rs=; b=sfgXPyjH4ooqhL2Nldsfsd0h6ULEtveifaZkEP4rENCqp0RQbJW4sks5/m3WDnL0oK UjYSbD+RG3rTw+8NnMZaThPc7gMOWBt2Ydnk7aAMQJBL0tK1H3sxZH7kTMG8XcirnZHv S6GaZbTkPxaz+m3dSoYTYb1ZmbeIvPL5hI26H+zNJQsvbcz3lHfvu1KdJ36mPvO19S6p 4jdv0s94Z7FNnoaqd81t6VmSFIqQHcTmw52PXdy1Huek/4PH7d1ejaNAfM8BodSoXGIN dRqiS5GVhh+3WkCjjcpONXeEyoaePx3TQHq1ySfN6e3SVPX3RD2dXCdTFH2MsYuiX8mO /+Uw== X-Gm-Message-State: AOJu0Yw5BXVyebNIIFojKjrUL6X2xMk2lqbIw8/bDVRRyEUm43rWnpAx z/i+4LLVNLXIbdhSM/ZbJfPjuPt1FJhzF9kP2qSGu0Ahh7Ge2UqRuIGiAxNVajLzYipUCbJZ4aH KkTdh9Dg= X-Gm-Gg: ATEYQzzu26PQ5msjP6kYaBnqpC1wYppdHaU/lQkioGj+rjKtBsN7PDtAwEpXED7QlxS NQdpESHWSSvy0c7k5dTh+5g7Ht3Q+z/KfPp7XMzAoiUyrKTG/W4jepK7qiaU6/hwEQrxvsgPKg0 QLHzt9xMVGBfqXW7xu276+g4wc+Mb+AZD4nnYCer3NxRPUaMjlnqLMX7C1MtR8YsVzKrFglyz7w /Le0nxqaGFa/EL4EOTyx8f9J1PLTMhKSqN4CEskh2FSK6VHAAsL9XkJl4e92BfghfN0MSrl9BE0 D6068p+ocJxatc8DnCoMoU9kCjCmQfcMaup4N9YdfoJTQf7mfUP6gEjMQeQBM0U2p/ixMtmnri2 +SPLjZFNc6KG++tQWn0TMI5DJQeVWoPfifptCYEhtMsZOJIdGHETEFVSi9xYO42n29CMnpyvIMR YD+f6nRnurZLR8wxTum/SsxQKAQPPFypIE9mV6Z+LRUtQPIji+kDWvJ7TgDM3jq8q+9sGRlqSAa ZCG5Hn73svTV/zmrFkEFLA0XZnNiUEJicgtW/ThSw== X-Received: by 2002:a5d:64c6:0:b0:439:bd26:3c63 with SMTP id ffacd0b85a97d-43b64262da5mr24967152f8f.28.1774365080321; Tue, 24 Mar 2026 08:11:20 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/11] hw/arm/smmuv3-accel: Change "ats" property type to OnOffAuto Date: Tue, 24 Mar 2026 15:11:05 +0000 Message-ID: <20260324151111.237411-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260324151111.237411-1-peter.maydell@linaro.org> References: <20260324151111.237411-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774365140337158500 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Change accel SMMUv3 ATS property from bool to OnOffAuto. The 'auto' value is not implemented, as this commit is meant to set the property to the correct type and avoid breaking JSON/QMP when the auto mode is introduced. A future patch will implement resolution of the 'auto' value to match the host SMMUv3 ATS support. The conversion of the ATS property type to OnOffAuto is an incompatible change for JSON/QMP when a bool value is expected for "ats", but the "ats" property is new in 11.0 and this patch is submitted as a fix to the property type. Fixes: f7f5013a55a3 ("hw/arm/smmuv3-accel: Add support for ATS") Tested-by: Eric Auger Reviewed-by: Shameer Kolothum Tested-by: Shameer Kolothum Reviewed-by: Eric Auger Acked-by: Markus Armbruster Signed-off-by: Nathan Chen Message-id: 20260323182454.1416110-3-nathanc@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel.c | 4 +++- hw/arm/smmuv3.c | 17 ++++++++++++++--- hw/arm/virt-acpi-build.c | 2 +- include/hw/arm/smmuv3.h | 4 +++- 4 files changed, 21 insertions(+), 6 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 2bb142c47f..f21a6a9997 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -827,7 +827,9 @@ void smmuv3_accel_idr_override(SMMUv3State *s) s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, s->ril); =20 /* QEMU SMMUv3 has no ATS. Advertise ATS if opt-in by property */ - s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, ATS, s->ats); + if (s->ats =3D=3D ON_OFF_AUTO_ON) { + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, ATS, 1); + } =20 /* Advertise 48-bit OAS in IDR5 when requested (default is 44 bits). */ if (s->oas =3D=3D SMMU_OAS_48BIT) { diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 068108e49b..a683402a0c 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -317,6 +317,11 @@ static void smmuv3_init_id_regs(SMMUv3State *s) smmuv3_accel_idr_override(s); } =20 +bool smmuv3_ats_enabled(SMMUv3State *s) +{ + return FIELD_EX32(s->idr[0], IDR0, ATS); +} + static void smmuv3_reset(SMMUv3State *s) { s->cmdq.base =3D deposit64(s->cmdq.base, 0, 5, SMMU_CMDQS); @@ -1966,12 +1971,17 @@ static bool smmu_validate_property(SMMUv3State *s, = Error **errp) } #endif =20 + if (s->ats =3D=3D ON_OFF_AUTO_AUTO) { + error_setg(errp, "ats auto mode is not supported"); + return false; + } + if (!s->accel) { if (!s->ril) { error_setg(errp, "ril can only be disabled if accel=3Don"); return false; } - if (s->ats) { + if (s->ats =3D=3D ON_OFF_AUTO_ON) { error_setg(errp, "ats can only be enabled if accel=3Don"); return false; } @@ -2128,7 +2138,7 @@ static const Property smmuv3_properties[] =3D { DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0), /* RIL can be turned off for accel cases */ DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true), - DEFINE_PROP_BOOL("ats", SMMUv3State, ats, false), + DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_OFF), DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0), }; @@ -2160,7 +2170,8 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) "Disable range invalidation support (for accel=3Don)"); object_class_property_set_description(klass, "ats", "Enable/disable ATS support (for accel=3Don). Please ensure host " - "platform has ATS support before enabling this"); + "platform has ATS support before enabling this. ats=3Dauto is not " + "supported."); object_class_property_set_description(klass, "oas", "Specify Output Address Size (for accel=3Don). Supported values " "are 44 or 48 bits. Defaults to 44 bits"); diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 719d2f994e..591cfc993c 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -402,7 +402,7 @@ static int iort_smmuv3_devices(Object *obj, void *opaqu= e) =20 bus =3D PCI_BUS(object_property_get_link(obj, "primary-bus", &error_ab= ort)); sdev.accel =3D object_property_get_bool(obj, "accel", &error_abort); - sdev.ats =3D object_property_get_bool(obj, "ats", &error_abort); + sdev.ats =3D smmuv3_ats_enabled(ARM_SMMUV3(obj)); pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); sbdev =3D SYS_BUS_DEVICE(obj); sdev.base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 26b2fc42fd..ce51a5b9b4 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -70,7 +70,7 @@ struct SMMUv3State { uint64_t msi_gpa; Error *migration_blocker; bool ril; - bool ats; + OnOffAuto ats; uint8_t oas; uint8_t ssidsize; }; @@ -91,6 +91,8 @@ struct SMMUv3Class { ResettablePhases parent_phases; }; =20 +bool smmuv3_ats_enabled(struct SMMUv3State *s); + #define TYPE_ARM_SMMUV3 "arm-smmuv3" OBJECT_DECLARE_TYPE(SMMUv3State, SMMUv3Class, ARM_SMMUV3) =20 --=20 2.43.0 From nobody Fri Apr 3 08:36:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774365166; cv=none; d=zohomail.com; s=zohoarc; b=j0ELfmhJpbLUiTVClYUln4DoFYLCP3xQdtj2nMepcY5Y1kDn3V6KHfCiwSssuxzXjGGYnZAmM8n+pDHwwPoHSyqrPRXaGTkRlsdW2vhYiVYfAJTGNnE42kJpm8b4AduuUOuWnyty7zBHbHX58oybCwvTYIAUxGSjW6/I7KNo6mg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774365166; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=E6ZwApvfGFbQl/yLyHCasjz6LaGeymRacGWTzWNB6N4=; b=HoR4nKPx0Y0Buc5YvlcxY41fQ0QXFWWh0BmhI+9DOufNS9TEZbJnGPV4zyQ/lWwEgtjNu0MtyQSr9hBwGNCRxgn1MdGnlz5NkMkBHDiqHBX7opQNh1rwnJMsqQp8J0P6O51DzW9w3epDm4DKhbO5VMQit1ouHWjvOd93duOvOgA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774365166041263.6859754291945; Tue, 24 Mar 2026 08:12:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w53Pk-0000lJ-MK; Tue, 24 Mar 2026 11:11:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w53Ph-0000hv-P3 for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:25 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w53Pf-0005DI-FK for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:24 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-43b3d9d0695so5025473f8f.0 for ; Tue, 24 Mar 2026 08:11:23 -0700 (PDT) Received: from lanath.. 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The 'auto' value is not implemented, as this commit is meant to set the property to the correct type and avoid breaking JSON/QMP when the auto mode is introduced. A future patch will implement resolution of the 'auto' value to match the host SMMUv3 RIL support. The conversion of the RIL property type to OnOffAuto is an incompatible change for JSON/QMP when a bool value is expected for "ril", but the "ril" property is new in 11.0 and this patch is submitted as a fix to the property type. Fixes: bd715ff5bda9 ("hw/arm/smmuv3-accel: Add a property to specify RIL su= pport") Tested-by: Eric Auger Reviewed-by: Shameer Kolothum Tested-by: Shameer Kolothum Reviewed-by: Eric Auger Acked-by: Markus Armbruster Signed-off-by: Nathan Chen Message-id: 20260323182454.1416110-4-nathanc@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel.c | 6 ++++-- hw/arm/smmuv3.c | 11 ++++++++--- include/hw/arm/smmuv3.h | 2 +- 3 files changed, 13 insertions(+), 6 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index f21a6a9997..c31b64295e 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -823,8 +823,10 @@ void smmuv3_accel_idr_override(SMMUv3State *s) return; } =20 - /* By default QEMU SMMUv3 has RIL. Update IDR3 if user has disabled it= */ - s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, s->ril); + /* Only override RIL if user explicitly set OFF */ + if (s->ril =3D=3D ON_OFF_AUTO_OFF) { + s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, 0); + } =20 /* QEMU SMMUv3 has no ATS. Advertise ATS if opt-in by property */ if (s->ats =3D=3D ON_OFF_AUTO_ON) { diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index a683402a0c..ea285bdf64 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1975,9 +1975,13 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) error_setg(errp, "ats auto mode is not supported"); return false; } + if (s->ril =3D=3D ON_OFF_AUTO_AUTO) { + error_setg(errp, "ril auto mode is not supported"); + return false; + } =20 if (!s->accel) { - if (!s->ril) { + if (s->ril =3D=3D ON_OFF_AUTO_OFF) { error_setg(errp, "ril can only be disabled if accel=3Don"); return false; } @@ -2137,7 +2141,7 @@ static const Property smmuv3_properties[] =3D { /* GPA of MSI doorbell, for SMMUv3 accel use. */ DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0), /* RIL can be turned off for accel cases */ - DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true), + DEFINE_PROP_ON_OFF_AUTO("ril", SMMUv3State, ril, ON_OFF_AUTO_ON), DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_OFF), DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0), @@ -2167,7 +2171,8 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) "Enable SMMUv3 accelerator support. Allows host SMMUv3 to be " "configured in nested mode for vfio-pci dev assignment"); object_class_property_set_description(klass, "ril", - "Disable range invalidation support (for accel=3Don)"); + "Disable range invalidation support (for accel=3Don). ril=3Dauto " + "is not supported."); object_class_property_set_description(klass, "ats", "Enable/disable ATS support (for accel=3Don). Please ensure host " "platform has ATS support before enabling this. ats=3Dauto is not " diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index ce51a5b9b4..c35e599bbc 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -69,7 +69,7 @@ struct SMMUv3State { struct SMMUv3AccelState *s_accel; uint64_t msi_gpa; Error *migration_blocker; - bool ril; + OnOffAuto ril; OnOffAuto ats; uint8_t oas; uint8_t ssidsize; --=20 2.43.0 From nobody Fri Apr 3 08:36:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774365136; cv=none; d=zohomail.com; s=zohoarc; b=G2NOsCpd/+/mwQoR4EvB2gCebLw2Hw1lEEB+F7pURxKpa+jz3EUpI/EQJl+ep1DFf7BTjL0Nczy6TRjB/+UsFo/tt4FmOS/n03ympBgmRGNY7BKw0t5iC3Y3hAD+GdVUflCxQ20Gp/p6CRG9UTu8eW/nN73V8sNkU5TeWF04bKk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774365136; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Rgr2enp+qbVDThQZJFr+FEHlpspYgEBOwZezu1EGo0U=; b=bKcU1UxGam78Dnao7s4+TpF2ZSSZ/6hG/aBcLvhp16VdErHLjoFtiujOaNFlJ7n+fCKRZvmNdN9Z6q1FnItGpeKbzjfI4rgrXcLolNwNwn6pVbaY/iDFLTrpLghkR2ldDRp6z3MpXu2oQt23uS6DIjhgxUzFXzhzmKzf9Gk27Qg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774365136406119.92513686583425; Tue, 24 Mar 2026 08:12:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w53Pt-0000rb-PX; Tue, 24 Mar 2026 11:11:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w53Pi-0000j1-Bf for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:27 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w53Pg-0005DX-J5 for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:26 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-43b44c0bcdbso5918511f8f.1 for ; Tue, 24 Mar 2026 08:11:24 -0700 (PDT) Received: from lanath.. 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Values are auto and 0..20. The auto value allows SSID size property to be derived from host IOMMU capabilities. A value of 0 disables SubstreamID, while non-zero values specify the SSID size in bits. Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Shameer Kolothum Acked-by: Markus Armbruster Signed-off-by: Nathan Chen Message-id: 20260323182454.1416110-5-nathanc@nvidia.com Signed-off-by: Peter Maydell --- hw/core/qdev-properties-system.c | 14 ++++++++++++++ include/hw/core/qdev-properties-system.h | 3 +++ qapi/misc-arm.json | 16 ++++++++++++++++ qapi/pragma.json | 1 + 4 files changed, 34 insertions(+) diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-sys= tem.c index a402321f42..4aca1d4326 100644 --- a/hw/core/qdev-properties-system.c +++ b/hw/core/qdev-properties-system.c @@ -18,6 +18,7 @@ #include "qapi/qapi-types-block.h" #include "qapi/qapi-types-machine.h" #include "qapi/qapi-types-migration.h" +#include "qapi/qapi-types-misc-arm.h" #include "qapi/qapi-visit-virtio.h" #include "qapi/qmp/qerror.h" #include "qemu/ctype.h" @@ -723,6 +724,19 @@ const PropertyInfo qdev_prop_zero_page_detection =3D { .set_default_value =3D qdev_propinfo_set_default_value_enum, }; =20 +/* --- SsidSizeMode --- */ + +QEMU_BUILD_BUG_ON(sizeof(SsidSizeMode) !=3D sizeof(int)); + +const PropertyInfo qdev_prop_ssidsize_mode =3D { + .type =3D "SsidSizeMode", + .description =3D "ssidsize mode: auto, 0-20", + .enum_table =3D &SsidSizeMode_lookup, + .get =3D qdev_propinfo_get_enum, + .set =3D qdev_propinfo_set_enum, + .set_default_value =3D qdev_propinfo_set_default_value_enum, +}; + /* --- Reserved Region --- */ =20 /* diff --git a/include/hw/core/qdev-properties-system.h b/include/hw/core/qde= v-properties-system.h index ec21732ce5..4708885164 100644 --- a/include/hw/core/qdev-properties-system.h +++ b/include/hw/core/qdev-properties-system.h @@ -14,6 +14,7 @@ extern const PropertyInfo qdev_prop_multifd_compression; extern const PropertyInfo qdev_prop_mig_mode; extern const PropertyInfo qdev_prop_granule_mode; extern const PropertyInfo qdev_prop_zero_page_detection; +extern const PropertyInfo qdev_prop_ssidsize_mode; extern const PropertyInfo qdev_prop_losttickpolicy; extern const PropertyInfo qdev_prop_blockdev_on_error; extern const PropertyInfo qdev_prop_bios_chs_trans; @@ -61,6 +62,8 @@ extern const PropertyInfo qdev_prop_virtio_gpu_output_lis= t; #define DEFINE_PROP_ZERO_PAGE_DETECTION(_n, _s, _f, _d) \ DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_zero_page_detection, \ ZeroPageDetection) +#define DEFINE_PROP_SSIDSIZE_MODE(_n, _s, _f, _d) \ + DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_ssidsize_mode, SsidSizeMo= de) #define DEFINE_PROP_LOSTTICKPOLICY(_n, _s, _f, _d) \ DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_losttickpolicy, \ LostTickPolicy) diff --git a/qapi/misc-arm.json b/qapi/misc-arm.json index f921d740f1..416b4240e2 100644 --- a/qapi/misc-arm.json +++ b/qapi/misc-arm.json @@ -45,3 +45,19 @@ # { "version": 3, "emulated": false, "kernel": true } = ] } ## { 'command': 'query-gic-capabilities', 'returns': ['GICCapability'] } + +## +# @SsidSizeMode: +# +# SMMUv3 SubstreamID size configuration mode. +# +# @auto: derive from host IOMMU capabilities +# +# Values 0-20: SSIDSIZE value in bits. 0 disables SubstreamID. +# +# Since: 11.0 +## +{ 'enum': 'SsidSizeMode', + 'data': [ 'auto', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', + '10', '11', '12', '13', '14', '15', '16', '17', '18', + '19', '20' ] } # order matters, see ssidsize_mode_to_value() diff --git a/qapi/pragma.json b/qapi/pragma.json index 193bc39059..24aebbe8f5 100644 --- a/qapi/pragma.json +++ b/qapi/pragma.json @@ -68,6 +68,7 @@ 'S390CpuEntitlement', 'S390CpuPolarization', 'S390CpuState', + 'SsidSizeMode', 'String', 'StringWrapper', 'SysEmuTarget', --=20 2.43.0 From nobody Fri Apr 3 08:36:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b64717e97sm40781916f8f.35.2026.03.24.08.11.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Mar 2026 08:11:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774365084; x=1774969884; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=kvuAX+aljmK1WGcU3Y0ud4Mf1yP5fbh/2lCieSQZkf0=; b=Kq0kaArPKQYg21Gs27QQepvLKa3ni3u0L6ZMKckhno5Z9SMcGoPs4w0Ni9oZql/vsC FdKZ+ymnMrzVwYTzNaY1APvo5KfqFHnjRQXihignHWVYibVtW9VpIu5GL04OHvba6JT6 KyOpyPGkT6DBWZCzcfoLenu7ViD52xxixHaGVXAdD/ry03QciAmNaGSysv4YahuC6hG7 9YeWl0/HeD96atOlZG/ndzreQe4vhMbbRDfXCr1NSi/+BOoZ5CwpS3an0LRn+dnXE+La ZOvmx26weHLf8WxM5eY6i7Ia1ePLxaWVxejR3eAzmIzuT2Vw32Jopongdhz5qZwdoRL5 00fQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774365084; x=1774969884; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=kvuAX+aljmK1WGcU3Y0ud4Mf1yP5fbh/2lCieSQZkf0=; b=DMHmKCeokqqWuu96vHUGV1m2kwUCma9xyx+gjEkc5/PfagaMkq3KwW4kJ7EnFCsfGZ rrf031BzGGEeFlhfqFf05D+HhY2qFxborH/AMq3j9CQ1ArLfrdMDnci4vlC+EaNiJ2jM iJdlqu0ZLug+053oTdElkPkVxOpnNzszGr4ULPFMLO7syD2Ft4JRxx4HZ3gHU4oUor8v 9DG49Ln1Skan3YeBh21o+3M5BEAnQfIWibkXfHlOs5nCJlIudlHPxSx5VC3pHjA2XB1W MZVEL3n3N6m0mMFQzOQwnEw81lo5mbtC9TLl+Y+b12NwqlviZqYGIHJo9RySvcAM6e/a FyBA== X-Gm-Message-State: AOJu0Yy2i/QMJTgOJQcqmWJ2QkqVryu4TNFsK6/JjLHHOFfNUWASVqg7 XCDkazsrb/Ep/wZBTftqSG1XcvgQU4bIY5aIFSG1pk913c18Lg+4CxUH1E13Nhx2p7EOKK2cqO6 FVNeM4mQ= X-Gm-Gg: ATEYQzxCz51ZIetJyMZo19VH++J8hIEmpAfPKmobrfNTsWsw6P1+xexn/X/ZLpQSzMl VAj6LUaWVEbf9ndE9Mlgog1q/wkIxyzy9RhcZ8OyyWJPSUa9e739/n7EV5J/N2D6YsXfioolzs3 3wQT8JW/Fb45GHuJWRQwmsq+13uoMdsjcBUK6kKQYv1DA9co9XeH2YUo9CT4C1jujRpCOX4QG8d IZlogRY4uTESXhX4sbv7T+SvdyuZIUGTx/criMyorLtS/Ql+OZqwCWdCD6CuSiT7ZLS3xANXnrO kGlrLzKzYFaS7tjS+uiB+l4r3DuP1daz9hR2PjIToT9Ks4O/t1VSByvV4An00jiVoGaSX68r9IP HScAxOaK59bxlNHsK+cyqVqUhp0TzOEdk7BnAkaYjahVV4AhbmHTADFQ4EJIYvjoTvoyI8ZeqQh U+fqVkQWH/PdWksny0WLpAR9USiR7StEdwEiXw2fKSwIvo6HNdSBV+PHv69PKaUexkKFbGBIRZY 2DcZYyR/mg7h3yhoH8THOcPyjWh4EJXJK6uVCBnJg== X-Received: by 2002:a05:600c:4e87:b0:477:6d96:b3e5 with SMTP id 5b1f17b1804b1-48715fd463emr2270045e9.7.1774365084025; Tue, 24 Mar 2026 08:11:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/11] hw/arm/smmuv3-accel: Change "ssidsize" property type to SsidSizeMode Date: Tue, 24 Mar 2026 15:11:08 +0000 Message-ID: <20260324151111.237411-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260324151111.237411-1-peter.maydell@linaro.org> References: <20260324151111.237411-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774365114348158500 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Change accel SMMUv3 SSIDSIZE property from uint8_t to SsidSizeMode. The 'auto' value is not implemented, as this commit is meant to set the property to the correct type and avoid breaking JSON/QMP when the auto mode is introduced. A future patch will implement resolution of 'auto' value to match the host SMMUv3 SSIDSIZE value. The conversion of the "ssidsize" property type to OnOffAuto is an incompatible change for JSON/QMP when a uint8_t value is expected for "ssidsize", but this property is new in 11.0 and this patch is submitted as a fix to the property type. Fixes: b8c6f8a69d27 ("hw/arm/smmuv3-accel: Make SubstreamID support configu= rable") Tested-by: Eric Auger Reviewed-by: Shameer Kolothum Reviewed-by: Eric Auger Tested-by: Shameer Kolothum Acked-by: Markus Armbruster Signed-off-by: Nathan Chen Message-id: 20260323182454.1416110-6-nathanc@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel.c | 23 +++++++++++++++++++++-- hw/arm/smmuv3.c | 19 ++++++++++--------- include/hw/arm/smmuv3-common.h | 1 - include/hw/arm/smmuv3.h | 3 ++- 4 files changed, 33 insertions(+), 13 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index c31b64295e..bc6cbfebc2 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -802,7 +802,7 @@ static uint64_t smmuv3_accel_get_viommu_flags(void *opa= que) SMMUState *bs =3D opaque; SMMUv3State *s =3D ARM_SMMUV3(bs); =20 - if (s->ssidsize) { + if (s->ssidsize > SSID_SIZE_MODE_0) { flags |=3D VIOMMU_FLAG_PASID_SUPPORTED; } return flags; @@ -817,6 +817,22 @@ static const PCIIOMMUOps smmuv3_accel_ops =3D { .get_msi_direct_gpa =3D smmuv3_accel_get_msi_gpa, }; =20 +/* + * This returns the value of a SsidSizeMode value offset by 1 to + * account for the enum values offset by 1 from actual values. + * + * SSID_SIZE_MODE_0 =3D 1, SSID_SIZE_MODE_1 =3D 2, etc. so return 0 + * if SSID_SIZE_MODE_0 is passed as input, return 1 if + * SSID_SIZE_MODE_1 is passed as input, etc. + */ +static uint8_t ssidsize_mode_to_value(SsidSizeMode mode) +{ + if (mode =3D=3D SSID_SIZE_MODE_AUTO) { + return 0; + } + return mode - 1; +} + void smmuv3_accel_idr_override(SMMUv3State *s) { if (!s->accel) { @@ -842,7 +858,10 @@ void smmuv3_accel_idr_override(SMMUv3State *s) * By default QEMU SMMUv3 has no SubstreamID support. Update IDR1 if u= ser * has enabled it. */ - s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, SSIDSIZE, s->ssidsize); + if (s->ssidsize > SSID_SIZE_MODE_0) { + s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, SSIDSIZE, + ssidsize_mode_to_value(s->ssidsize)); + } } =20 /* Based on SMUUv3 GPBA.ABORT configuration, attach a corresponding HWPT */ diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index ea285bdf64..79018f8d66 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -20,6 +20,7 @@ #include "qemu/bitops.h" #include "hw/core/irq.h" #include "hw/core/sysbus.h" +#include "hw/core/qdev-properties-system.h" #include "migration/blocker.h" #include "migration/vmstate.h" #include "hw/core/qdev-properties.h" @@ -625,7 +626,7 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg, } =20 /* Multiple context descriptors require SubstreamID support */ - if (!s->ssidsize && STE_S1CDMAX(ste) !=3D 0) { + if (s->ssidsize =3D=3D SSID_SIZE_MODE_0 && STE_S1CDMAX(ste) !=3D 0) { qemu_log_mask(LOG_UNIMP, "SMMUv3: multiple S1 context descriptors require Substream= ID support. " "Configure ssidsize > 0 (requires accel=3Don)\n"); @@ -1979,6 +1980,10 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) error_setg(errp, "ril auto mode is not supported"); return false; } + if (s->ssidsize =3D=3D SSID_SIZE_MODE_AUTO) { + error_setg(errp, "ssidsize auto mode is not supported"); + return false; + } =20 if (!s->accel) { if (s->ril =3D=3D ON_OFF_AUTO_OFF) { @@ -1993,7 +1998,7 @@ static bool smmu_validate_property(SMMUv3State *s, Er= ror **errp) error_setg(errp, "OAS must be 44 bits when accel=3Doff"); return false; } - if (s->ssidsize) { + if (s->ssidsize > SSID_SIZE_MODE_0) { error_setg(errp, "ssidsize can only be set if accel=3Don"); return false; } @@ -2011,11 +2016,6 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) error_setg(errp, "OAS can only be set to 44 or 48 bits"); return false; } - if (s->ssidsize > SMMU_SSID_MAX_BITS) { - error_setg(errp, "ssidsize must be in the range 0 to %d", - SMMU_SSID_MAX_BITS); - return false; - } =20 return true; } @@ -2144,7 +2144,8 @@ static const Property smmuv3_properties[] =3D { DEFINE_PROP_ON_OFF_AUTO("ril", SMMUv3State, ril, ON_OFF_AUTO_ON), DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_OFF), DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), - DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0), + DEFINE_PROP_SSIDSIZE_MODE("ssidsize", SMMUv3State, ssidsize, + SSID_SIZE_MODE_0), }; =20 static void smmuv3_instance_init(Object *obj) @@ -2185,7 +2186,7 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) "A value of N allows SSIDs in the range [0 .. 2^N - 1]. " "Valid range is 0-20, where 0 disables SubstreamID support. " "Defaults to 0. A value greater than 0 is required to enable " - "PASID support."); + "PASID support. ssidsize=3Dauto is not supported."); } =20 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, diff --git a/include/hw/arm/smmuv3-common.h b/include/hw/arm/smmuv3-common.h index 9f78bbe89e..7f0f992dfd 100644 --- a/include/hw/arm/smmuv3-common.h +++ b/include/hw/arm/smmuv3-common.h @@ -311,7 +311,6 @@ REG32(IDR1, 0x4) FIELD(IDR1, TABLES_PRESET, 30, 1) FIELD(IDR1, ECMDQ, 31, 1) =20 -#define SMMU_SSID_MAX_BITS 20 #define SMMU_IDR1_SIDSIZE 16 #define SMMU_CMDQS 19 #define SMMU_EVENTQS 19 diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index c35e599bbc..ddf472493d 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -21,6 +21,7 @@ =20 #include "hw/arm/smmu-common.h" #include "qom/object.h" +#include "qapi/qapi-types-misc-arm.h" =20 #define TYPE_SMMUV3_IOMMU_MEMORY_REGION "smmuv3-iommu-memory-region" =20 @@ -72,7 +73,7 @@ struct SMMUv3State { OnOffAuto ril; OnOffAuto ats; uint8_t oas; - uint8_t ssidsize; + SsidSizeMode ssidsize; }; =20 typedef enum { --=20 2.43.0 From nobody Fri Apr 3 08:36:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774365123; cv=none; d=zohomail.com; s=zohoarc; b=J/3Tbh6MgLD7ft/pHA4I9e8qtQ7eB2Xci2Vddl1sPAicbq3V0X721HxoZNRseGgGG8fXCBVo4x95uDFzkij6vbxh9cQlK0Yqmoha6PgoQ7m7kTBv6XDxmILeQ60Nsd7e2QPiZJ3LWqqcNR5ckam5JtwDJwsCLZXwtFrpNF4rOKI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774365123; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=5wiSFi8wnswcXFlOefRmA6X45uTbRfHYHACuotQz0g4=; b=QxqYgl41drkm9cjb4K5m2pTqEWxPx807R5Rn6mUtua0cA2kJ6Q3mTBPiFqBlGCV4c0dDLKgSTcLDMoXv+qUsInxRB2LU0Pi/dYMX/gr/LdFPmghlhdm2UXZlqybHUzA6Dhqhvw3jdpmSFfGiQhER+DAyLEc33cq11HEN232CMo0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774365123644785.1812682485635; Tue, 24 Mar 2026 08:12:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w53Pn-0000ms-9V; Tue, 24 Mar 2026 11:11:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w53Pl-0000lX-3y for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:29 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w53Pj-0005E9-FS for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:28 -0400 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-439d8dc4ae4so4843460f8f.2 for ; Tue, 24 Mar 2026 08:11:27 -0700 (PDT) Received: from lanath.. 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Values are auto, 32, 36, 40, 42, 44, 48, 52, and 56, where a value of N specifies an N-bit OAS. Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Shameer Kolothum Acked-by: Markus Armbruster Signed-off-by: Nathan Chen Message-id: 20260323182454.1416110-7-nathanc@nvidia.com Signed-off-by: Peter Maydell --- hw/core/qdev-properties-system.c | 13 +++++++++++ include/hw/core/qdev-properties-system.h | 3 +++ qapi/misc-arm.json | 28 ++++++++++++++++++++++++ 3 files changed, 44 insertions(+) diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-sys= tem.c index 4aca1d4326..a805ee2e1f 100644 --- a/hw/core/qdev-properties-system.c +++ b/hw/core/qdev-properties-system.c @@ -737,6 +737,19 @@ const PropertyInfo qdev_prop_ssidsize_mode =3D { .set_default_value =3D qdev_propinfo_set_default_value_enum, }; =20 +/* --- OasMode --- */ + +QEMU_BUILD_BUG_ON(sizeof(OasMode) !=3D sizeof(int)); + +const PropertyInfo qdev_prop_oas_mode =3D { + .type =3D "OasMode", + .description =3D "oas mode: auto, 32, 36, 40, 42, 44, 48, 52, 56", + .enum_table =3D &OasMode_lookup, + .get =3D qdev_propinfo_get_enum, + .set =3D qdev_propinfo_set_enum, + .set_default_value =3D qdev_propinfo_set_default_value_enum, +}; + /* --- Reserved Region --- */ =20 /* diff --git a/include/hw/core/qdev-properties-system.h b/include/hw/core/qde= v-properties-system.h index 4708885164..2cbea16d61 100644 --- a/include/hw/core/qdev-properties-system.h +++ b/include/hw/core/qdev-properties-system.h @@ -15,6 +15,7 @@ extern const PropertyInfo qdev_prop_mig_mode; extern const PropertyInfo qdev_prop_granule_mode; extern const PropertyInfo qdev_prop_zero_page_detection; extern const PropertyInfo qdev_prop_ssidsize_mode; +extern const PropertyInfo qdev_prop_oas_mode; extern const PropertyInfo qdev_prop_losttickpolicy; extern const PropertyInfo qdev_prop_blockdev_on_error; extern const PropertyInfo qdev_prop_bios_chs_trans; @@ -64,6 +65,8 @@ extern const PropertyInfo qdev_prop_virtio_gpu_output_lis= t; ZeroPageDetection) #define DEFINE_PROP_SSIDSIZE_MODE(_n, _s, _f, _d) \ DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_ssidsize_mode, SsidSizeMo= de) +#define DEFINE_PROP_OAS_MODE(_n, _s, _f, _d) \ + DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_oas_mode, OasMode) #define DEFINE_PROP_LOSTTICKPOLICY(_n, _s, _f, _d) \ DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_losttickpolicy, \ LostTickPolicy) diff --git a/qapi/misc-arm.json b/qapi/misc-arm.json index 416b4240e2..4dc66d00e5 100644 --- a/qapi/misc-arm.json +++ b/qapi/misc-arm.json @@ -61,3 +61,31 @@ 'data': [ 'auto', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', '10', '11', '12', '13', '14', '15', '16', '17', '18', '19', '20' ] } # order matters, see ssidsize_mode_to_value() + +## +# @OasMode: +# +# SMMUv3 Output Address Size configuration mode. +# +# @auto: derive from host IOMMU capabilities +# +# @32: 32-bit output address size +# +# @36: 36-bit output address size +# +# @40: 40-bit output address size +# +# @42: 42-bit output address size +# +# @44: 44-bit output address size +# +# @48: 48-bit output address size +# +# @52: 52-bit output address size +# +# @56: 56-bit output address size +# +# Since: 11.0 +## +{ 'enum': 'OasMode', + 'data': [ 'auto', '32', '36', '40', '42', '44', '48', '52', '56' ] } --=20 2.43.0 From nobody Fri Apr 3 08:36:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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The 'auto' value is not implemented, as this commit is meant to set the property to the correct type and avoid breaking JSON/QMP when the auto mode is introduced. A future patch will implement resolution of 'auto' value to match the host SMMUv3 OAS value. The conversion of the "oas" property type to OnOffAuto is an incompatible change for JSON/QMP when a uint8_t value is expected for "oas", but this property is new in 11.0 and this patch is submitted as a fix to the property type. Fixes: a015ac990fd3 ("hw/arm/smmuv3-accel: Add property to specify OAS bits= ") Tested-by: Eric Auger Reviewed-by: Shameer Kolothum Reviewed-by: Eric Auger Tested-by: Shameer Kolothum Acked-by: Markus Armbruster Signed-off-by: Nathan Chen Message-id: 20260323182454.1416110-8-nathanc@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel.c | 2 +- hw/arm/smmuv3.c | 17 +++++++++-------- include/hw/arm/smmuv3-common.h | 2 -- include/hw/arm/smmuv3.h | 2 +- 4 files changed, 11 insertions(+), 12 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index bc6cbfebc2..65c2f44880 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -850,7 +850,7 @@ void smmuv3_accel_idr_override(SMMUv3State *s) } =20 /* Advertise 48-bit OAS in IDR5 when requested (default is 44 bits). */ - if (s->oas =3D=3D SMMU_OAS_48BIT) { + if (s->oas =3D=3D OAS_MODE_48) { s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS_48); } =20 diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 79018f8d66..7fead1c3cf 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1984,6 +1984,11 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) error_setg(errp, "ssidsize auto mode is not supported"); return false; } + if (s->oas !=3D OAS_MODE_44 && s->oas !=3D OAS_MODE_48) { + error_setg(errp, "QEMU SMMUv3 model only implements 44 and 48 bit" + "OAS; other OasMode values are not supported"); + return false; + } =20 if (!s->accel) { if (s->ril =3D=3D ON_OFF_AUTO_OFF) { @@ -1994,7 +1999,7 @@ static bool smmu_validate_property(SMMUv3State *s, Er= ror **errp) error_setg(errp, "ats can only be enabled if accel=3Don"); return false; } - if (s->oas !=3D SMMU_OAS_44BIT) { + if (s->oas > OAS_MODE_44) { error_setg(errp, "OAS must be 44 bits when accel=3Doff"); return false; } @@ -2012,11 +2017,6 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) return false; } =20 - if (s->oas !=3D SMMU_OAS_44BIT && s->oas !=3D SMMU_OAS_48BIT) { - error_setg(errp, "OAS can only be set to 44 or 48 bits"); - return false; - } - return true; } =20 @@ -2143,7 +2143,7 @@ static const Property smmuv3_properties[] =3D { /* RIL can be turned off for accel cases */ DEFINE_PROP_ON_OFF_AUTO("ril", SMMUv3State, ril, ON_OFF_AUTO_ON), DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_OFF), - DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), + DEFINE_PROP_OAS_MODE("oas", SMMUv3State, oas, OAS_MODE_44), DEFINE_PROP_SSIDSIZE_MODE("ssidsize", SMMUv3State, ssidsize, SSID_SIZE_MODE_0), }; @@ -2180,7 +2180,8 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) "supported."); object_class_property_set_description(klass, "oas", "Specify Output Address Size (for accel=3Don). Supported values " - "are 44 or 48 bits. Defaults to 44 bits"); + "are 44 or 48 bits. Defaults to 44 bits. oas=3Dauto is not " + "supported."); object_class_property_set_description(klass, "ssidsize", "Number of bits used to represent SubstreamIDs (SSIDs). " "A value of N allows SSIDs in the range [0 .. 2^N - 1]. " diff --git a/include/hw/arm/smmuv3-common.h b/include/hw/arm/smmuv3-common.h index 7f0f992dfd..4609975edf 100644 --- a/include/hw/arm/smmuv3-common.h +++ b/include/hw/arm/smmuv3-common.h @@ -342,8 +342,6 @@ REG32(IDR5, 0x14) FIELD(IDR5, VAX, 10, 2); FIELD(IDR5, STALL_MAX, 16, 16); =20 -#define SMMU_OAS_44BIT 44 -#define SMMU_OAS_48BIT 48 #define SMMU_IDR5_OAS_44 4 #define SMMU_IDR5_OAS_48 5 =20 diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index ddf472493d..82f18eb090 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -72,7 +72,7 @@ struct SMMUv3State { Error *migration_blocker; OnOffAuto ril; OnOffAuto ats; - uint8_t oas; + OasMode oas; SsidSizeMode ssidsize; }; =20 --=20 2.43.0 From nobody Fri Apr 3 08:36:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1774365150; cv=none; d=zohomail.com; s=zohoarc; b=lOS2xNQBW50PrHmDZFuW/O1zXYAWwJ78fh7g9Ko/T3XPd6nvG45flTRVeFfnDfXeIv/mJIGNkAcY1aep+WEDRS49dYYjzPhiGoE5ktqXRgL1vmBJnGU5S+Wj/cfLvbezQ1Pcts/lgo9af8oOkAIukaK6Vzqv1IvIkIHCS22X5C8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774365150; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=t6RuVFBjGQxXKkbjdmtXNHPThUXn3bXy8K/7GIwt1EU=; b=DFRm0iX+vtqDLFVL4zHcoEWzSg4qzQAEdexSuKjcfd3NFqsI3zA1Zj3NXBMgJlU69dXWfXwLJBzdK5qvddgrS2cfzWTl27c2DkxFkwSrJtVOUj/KILJj9awMFPBvTEfh9W9IwLHoOFdCP+V5W8izlMITwH9neFT//4IrCB4DRa0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774365150554375.92312188312667; Tue, 24 Mar 2026 08:12:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w53Q3-0000zL-Uy; Tue, 24 Mar 2026 11:11:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w53Pq-0000qe-3H for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:37 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w53Pl-0005EU-V8 for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:32 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-486fb439299so45578245e9.0 for ; Tue, 24 Mar 2026 08:11:29 -0700 (PDT) Received: from lanath.. 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Reviewed-by: Eric Auger Tested-by: Eric Auger Reviewed-by: Shameer Kolothum Tested-by: Shameer Kolothum Signed-off-by: Nathan Chen Message-id: 20260323182454.1416110-9-nathanc@nvidia.com Signed-off-by: Peter Maydell --- qemu-options.hx | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/qemu-options.hx b/qemu-options.hx index dbcb0155ba..21972f8326 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -1279,13 +1279,43 @@ SRST ``aw-bits=3Dval`` (val between 32 and 64, default depends on machine) This decides the address width of the IOVA address space. =20 -``-device arm-smmuv3,primary-bus=3Did`` +``-device arm-smmuv3,primary-bus=3Did[,option=3D...]`` This is only supported by ``-machine virt`` (ARM). =20 ``primary-bus=3Did`` Accepts either the default root complex (pcie.0) or a pxb-pcie based root complex. =20 + ``accel=3Don|off`` (default: off) + Enables guest to leverage host SMMUv3 features for acceleration. + Enabling accel configures the host SMMUv3 in nested mode to support + vfio-pci passthrough. + + The following options are available when accel=3Don. + Note: 'auto' mode is not currently supported. + + ``ril=3Don|off`` (default: on) + Support for Range Invalidation, which allows the SMMUv3 driver to + invalidate TLB entries for a range of IOVAs at once instead of iss= uing + separate commands to invalidate each page. Must match with host SM= MUv3 + Range Invalidation support. + + ``ats=3Don|off`` (default: off) + Support for Address Translation Services, which enables PCIe devic= es to + cache address translations in their local TLB and reduce latency. = Host + SMMUv3 must support ATS in order to enable this feature for the vI= OMMU. + + ``oas=3Dval`` (supported values are 44 and 48. default: 44) + Sets the Output Address Size in bits. The value set here must be l= ess + than or equal to the host SMMUv3's supported OAS, so that the + intermediate physical addresses (IPA) consumed by host SMMU for st= age-2 + translation do not exceed the host's max supported IPA size. + + ``ssidsize=3Dval`` (val between 0 and 20. default: 0) + Sets the Substream ID size in bits. When set to a non-zero value, + PASID capability is advertised to the vIOMMU and accelerated use c= ases + such as Shared Virtual Addressing (SVA) are supported. + ``-device amd-iommu[,option=3D...]`` Enables emulation of an AMD-Vi I/O Memory Management Unit (IOMMU). Only available with ``-machine q35``, it supports the following option= s: --=20 2.43.0