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The following changes since commit fa4b2e31e649ba6fdb3eb2dd43952aad4a3bd675: Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging (2026-03-24 10:41:21 +0000) are available in the Git repository at: https://gitlab.com/pm215/qemu.git tags/pull-target-arm-20260324 for you to fetch changes up to af35bc0c146ced44f6bfe98587495ae193adcec4: qemu-options.hx: Document arm-smmuv3 device's accel properties (2026-03-24 14:02:30 +0000) ---------------------------------------------------------------- target-arm queue: * linux-user/i386/signal.c: Correct definition of target_fpstate_32 * hw/dma/pl080: Fix transfer logic in PL080 * hw/arm/smmuv3-accel: Switch to OnOffAuto properties * qemu-options.hx: Document arm-smmuv3 device's accel properties ---------------------------------------------------------------- Jose Martins (1): target/arm: fix s2prot not set for two-stage PMSA translations Nathan Chen (8): hw/arm/smmuv3-accel: Check ATS compatibility between host and guest hw/arm/smmuv3-accel: Change "ats" property type to OnOffAuto hw/arm/smmuv3-accel: Change "ril" property type to OnOffAuto qdev: Add a SsidSizeMode property type hw/arm/smmuv3-accel: Change "ssidsize" property type to SsidSizeMode qdev: Add an OasMode property type hw/arm/smmuv3-accel: Change "oas" property type to OasMode qemu-options.hx: Document arm-smmuv3 device's accel properties Peter Maydell (1): linux-user/i386/signal.c: Correct definition of target_fpstate_32 Tao Ding (1): hw/dma/pl080: Fix transfer logic in PL080 hw/arm/smmuv3-accel.c | 41 +++++++++++++++++--- hw/arm/smmuv3.c | 64 ++++++++++++++++++++------------ hw/arm/virt-acpi-build.c | 2 +- hw/core/qdev-properties-system.c | 27 ++++++++++++++ hw/dma/pl080.c | 17 ++++++--- include/hw/arm/smmuv3-common.h | 3 -- include/hw/arm/smmuv3.h | 11 ++++-- include/hw/core/qdev-properties-system.h | 6 +++ linux-user/i386/signal.c | 25 ++++++++++++- qapi/misc-arm.json | 44 ++++++++++++++++++++++ qapi/pragma.json | 1 + qemu-options.hx | 32 +++++++++++++++- target/arm/ptw.c | 7 ++++ 13 files changed, 235 insertions(+), 45 deletions(-)
From: Jose Martins <josemartins90@gmail.com> Commit a811c5dafb7 ("target/arm: Implement get_S2prot_indirect") changed get_phys_addr_twostage() to combine stage 1 and stage 2 permissions using the new s2prot field: result->f.prot = s1_prot & result->s2prot; The LPAE stage 2 path sets result->s2prot explicitly, but the PMSA stage 2 path (get_phys_addr_pmsav8) only sets result->f.prot, leaving s2prot at zero. This causes the combined permission to be zero, resulting in addr_read being set to -1 in the TLB entry and triggering an assertion in atomic_mmu_lookup() when the guest executes an atomic instruction on a two-stage PMSA platform (e.g. Cortex-R52 with EL2). Set s2prot from f.prot after the PMSA stage 2 lookup, consistent with what the LPAE path does. Cc: qemu-stable@nongnu.org Fixes: a811c5dafb7 ("target/arm: Implement get_S2prot_indirect") Signed-off-by: Jose Martins <josemartins90@gmail.com> [PMM: refer to the right commit in the commit message] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260321231916.2852653-1-josemartins90@gmail.com Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/ptw.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ret = pmsav8_mpu_lookup(env, address, access_type, ptw->in_prot_check, mmu_idx, secure, result, fi, NULL); + /* + * For two-stage PMSA translations, s2prot holds the stage 2 + * permissions to be combined with stage 1 in get_phys_addr_twostage(). + */ + if (regime_is_stage2(mmu_idx)) { + result->s2prot = result->f.prot; + } if (sattrs.subpage) { result->f.lg_page_size = 0; } -- 2.43.0
Our definition of the target_fpstate_32 struct doesn't match the kernel's version. We only use this struct definition in the definition of 'struct sigframe', where it is used in a field that is present only for legacy reasons to retain the offset of the following 'extramask' field. So really all that matters is its length, and we do get that right; but our previous definition using X86LegacySaveArea implicitly added an extra alignment constraint (because X86LegacySaveArea is tagged as 16-aligned) which the real target_fpstate_32 does not have. Because we allocate and use a 'struct sigframe' on the guest's stack with the guest's alignment requirements, this resulted in the undefined-behaviour sanitizer complaining during 'make check-tcg' for i386-linux-user: ../../linux-user/i386/signal.c:471:35: runtime error: member access within misaligned address 0x1000c07f75ec for type 'struct sigframe', which requires 16 byte alignment 0x1000c07f75ec: note: pointer points here 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ^ ../../linux-user/i386/signal.c:808:5: runtime error: member access within misaligned address 0x1000c07f75f4 for type 'struct target_sigcontext_32', which requires 8 byte alignment 0x1000c07f75f4: note: pointer points here 0a 00 00 00 33 00 00 00 00 00 00 00 2b 00 00 00 2b 00 00 00 40 05 80 40 f4 7f 10 08 58 05 80 40 ^ and various similar errors. Replace the use of X86LegacyXSaveArea with a set of fields that match the kernel _fpstate_32 struct, and assert that the length is correct. We could equally have used uint8_t legacy_area[512]; but following the kernel is probably less confusing overall. Since in target/i386/cpu.h we assert that X86LegacySaveArea is 512 bytes, and in linux-user/i386/signal.c we assert that target_fregs_state is (32 + 80) bytes, the new assertion confirms that we didn't change the size of target_fpstate_32 here, only its alignment requirements. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260305161739.1775232-1-peter.maydell@linaro.org --- linux-user/i386/signal.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/linux-user/i386/signal.c b/linux-user/i386/signal.c index XXXXXXX..XXXXXXX 100644 --- a/linux-user/i386/signal.c +++ b/linux-user/i386/signal.c @@ -XXX,XX +XXX,XX @@ struct target_fpx_sw_bytes { }; QEMU_BUILD_BUG_ON(sizeof(struct target_fpx_sw_bytes) != 12*4); +struct fpxreg { + uint16_t significand[4]; + uint16_t exponent; + uint16_t padding[3]; +}; + +struct xmmreg { + uint32_t element[4]; +}; + +/* + * This corresponds to the kernel's _fpstate_32. Since we + * only use it for the fpstate_unused padding section in + * the target sigcontext, it doesn't actually matter what fields + * we define here as long as we get the size right. + */ struct target_fpstate_32 { struct target_fregs_state fpstate; - X86LegacyXSaveArea fxstate; + uint32_t fxsr_env[6]; + uint32_t mxcsr; + uint32_t reserved; + struct fpxreg fxsr_st[8]; + struct xmmreg xmm[8]; + uint32_t padding1[44]; + uint32_t padding2[12]; /* aka sw_reserved */ }; +QEMU_BUILD_BUG_ON(sizeof(struct target_fpstate_32) != 32 + 80 + 512); struct target_sigcontext_32 { uint16_t gs, __gsh; -- 2.43.0
From: Tao Ding <dingtao0430@163.com> The logic in the PL080 for transferring data has multiple bugs: * The TransferSize field in the channel control register counts in units of the source width; because our loop may do multiple source loads if the destination width is greater than the source width, we need to decrement it by (xsize / swidth), not by 1, each loop * It is documented in the TRM that it is a software error to program the source and destination width such that SWidth < DWidth and TransferSize * SWidth is not a multiple of DWidth. (This would mean that there isn't enough data to do a full final destination write.) We weren't doing anything sensible with this case. The TRM doesn't document what the hardware actually does (though it drops some hints that suggest that it probably over-reads from the source). * In the loop to write to the destination, each loop adds swidth to ch->dest for each loop and also uses (ch->dest + n) as the destination address. This moves the destination address on further than we should each time round the loop, and also is incrementing ch->dest by swidth when it should be dwidth. This patch fixes these problems: * decrement TransferSize by the correct amount * log and ignore the transfer size mismatch case * correct the loop logic for the destination writes A repro case which exercises some of this is as follows. It configures swidth to 1 byte, dwidth to 4 bytes, and transfer size 4, for a transfer from 0x00000000 to 0x000010000. Examining the destination memory in the QEMU monitor should show that the source data 0x44332211 has all been copied, but before this fix it is not: ./qemu-system-arm -M versatilepb -m 128M -nographic -S \ -device loader,addr=0x00000000,data=0x44332211,data-len=4 \ -device loader,addr=0x00001000,data=0x00000000,data-len=4 \ -device loader,addr=0x10130030,data=0x00000001,data-len=4 \ -device loader,addr=0x10130100,data=0x00000000,data-len=4 \ -device loader,addr=0x10130104,data=0x00001000,data-len=4 \ -device loader,addr=0x10130108,data=0x00000000,data-len=4 \ -device loader,addr=0x1013010C,data=0x9e47f004,data-len=4 \ -device loader,addr=0x10130110,data=0x0000c001,data-len=4 Without this patch the QEMU monitor shows: (qemu) xp /1wx 0x00001000 00001000: 0x00002211 Correct result: (qemu) xp /1wx 0x00001000 00001000: 0x44332211 Cc: qemu-stable@nongnu.org Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Tao Ding <dingtao0430@163.com> [PMM: Wrote up what we are fixing in the commit message] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/dma/pl080.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c index XXXXXXX..XXXXXXX 100644 --- a/hw/dma/pl080.c +++ b/hw/dma/pl080.c @@ -XXX,XX +XXX,XX @@ again: c, extract32(ch->ctrl, 21, 3)); continue; } - - for (n = 0; n < dwidth; n+= swidth) { + if ((size * swidth) % dwidth) { + qemu_log_mask(LOG_GUEST_ERROR, + "pl080: channel %d: transfer size mismatch: size=%d swidth=%d dwidth=%d\n", + c, size, swidth, dwidth); + continue; + } + xsize = MAX(swidth, dwidth); + for (n = 0; n < xsize; n += swidth) { address_space_read(&s->downstream_as, ch->src, MEMTXATTRS_UNSPECIFIED, buff + n, swidth); if (ch->ctrl & PL080_CCTRL_SI) ch->src += swidth; } - xsize = (dwidth < swidth) ? swidth : dwidth; /* ??? This may pad the value incorrectly for dwidth < 32. */ for (n = 0; n < xsize; n += dwidth) { - address_space_write(&s->downstream_as, ch->dest + n, + address_space_write(&s->downstream_as, ch->dest, MEMTXATTRS_UNSPECIFIED, buff + n, dwidth); if (ch->ctrl & PL080_CCTRL_DI) - ch->dest += swidth; + ch->dest += dwidth; } - size--; + size -= xsize / swidth; ch->ctrl = (ch->ctrl & 0xfffff000) | size; if (size == 0) { /* Transfer complete. */ -- 2.43.0
From: Nathan Chen <nathanc@nvidia.com> Compare the host SMMUv3 ATS support bit with the guest SMMUv3 ATS support bit in IDR0 and fail the compatibility check if ATS support is opted as enabled on the guest SMMUv3 when it is not supported on host SMMUv3. Fixes: f7f5013a55a3 ("hw/arm/smmuv3-accel: Add support for ATS") Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Shameer Kolothum <skolothumtho@nvidia.com> Tested-by: Shameer Kolothum <skolothumtho@nvidia.com> Signed-off-by: Nathan Chen <nathanc@nvidia.com> Message-id: 20260323182454.1416110-2-nathanc@nvidia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/smmuv3-accel.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -XXX,XX +XXX,XX @@ smmuv3_accel_check_hw_compatible(SMMUv3State *s, smmuv3_oas_bits(FIELD_EX32(s->idr[5], IDR5, OAS))); return false; } + /* Check ATS value opted is compatible with Host SMMUv3 */ + if (FIELD_EX32(info->idr[0], IDR0, ATS) < + FIELD_EX32(s->idr[0], IDR0, ATS)) { + error_setg(errp, "Host SMMUv3 doesn't support Address Translation Services"); + return false; + } /* QEMU SMMUv3 supports GRAN4K/GRAN16K/GRAN64K translation granules */ if (FIELD_EX32(info->idr[5], IDR5, GRAN4K) != -- 2.43.0
From: Nathan Chen <nathanc@nvidia.com> Change accel SMMUv3 ATS property from bool to OnOffAuto. The 'auto' value is not implemented, as this commit is meant to set the property to the correct type and avoid breaking JSON/QMP when the auto mode is introduced. A future patch will implement resolution of the 'auto' value to match the host SMMUv3 ATS support. The conversion of the ATS property type to OnOffAuto is an incompatible change for JSON/QMP when a bool value is expected for "ats", but the "ats" property is new in 11.0 and this patch is submitted as a fix to the property type. Fixes: f7f5013a55a3 ("hw/arm/smmuv3-accel: Add support for ATS") Tested-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Shameer Kolothum <skolothumtho@nvidia.com> Tested-by: Shameer Kolothum <skolothumtho@nvidia.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Acked-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Nathan Chen <nathanc@nvidia.com> Message-id: 20260323182454.1416110-3-nathanc@nvidia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/smmuv3-accel.c | 4 +++- hw/arm/smmuv3.c | 17 ++++++++++++++--- hw/arm/virt-acpi-build.c | 2 +- include/hw/arm/smmuv3.h | 4 +++- 4 files changed, 21 insertions(+), 6 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -XXX,XX +XXX,XX @@ void smmuv3_accel_idr_override(SMMUv3State *s) s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, s->ril); /* QEMU SMMUv3 has no ATS. Advertise ATS if opt-in by property */ - s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ATS, s->ats); + if (s->ats == ON_OFF_AUTO_ON) { + s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ATS, 1); + } /* Advertise 48-bit OAS in IDR5 when requested (default is 44 bits). */ if (s->oas == SMMU_OAS_48BIT) { diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -XXX,XX +XXX,XX @@ static void smmuv3_init_id_regs(SMMUv3State *s) smmuv3_accel_idr_override(s); } +bool smmuv3_ats_enabled(SMMUv3State *s) +{ + return FIELD_EX32(s->idr[0], IDR0, ATS); +} + static void smmuv3_reset(SMMUv3State *s) { s->cmdq.base = deposit64(s->cmdq.base, 0, 5, SMMU_CMDQS); @@ -XXX,XX +XXX,XX @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp) } #endif + if (s->ats == ON_OFF_AUTO_AUTO) { + error_setg(errp, "ats auto mode is not supported"); + return false; + } + if (!s->accel) { if (!s->ril) { error_setg(errp, "ril can only be disabled if accel=on"); return false; } - if (s->ats) { + if (s->ats == ON_OFF_AUTO_ON) { error_setg(errp, "ats can only be enabled if accel=on"); return false; } @@ -XXX,XX +XXX,XX @@ static const Property smmuv3_properties[] = { DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0), /* RIL can be turned off for accel cases */ DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true), - DEFINE_PROP_BOOL("ats", SMMUv3State, ats, false), + DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_OFF), DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0), }; @@ -XXX,XX +XXX,XX @@ static void smmuv3_class_init(ObjectClass *klass, const void *data) "Disable range invalidation support (for accel=on)"); object_class_property_set_description(klass, "ats", "Enable/disable ATS support (for accel=on). Please ensure host " - "platform has ATS support before enabling this"); + "platform has ATS support before enabling this. ats=auto is not " + "supported."); object_class_property_set_description(klass, "oas", "Specify Output Address Size (for accel=on). Supported values " "are 44 or 48 bits. Defaults to 44 bits"); diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -XXX,XX +XXX,XX @@ static int iort_smmuv3_devices(Object *obj, void *opaque) bus = PCI_BUS(object_property_get_link(obj, "primary-bus", &error_abort)); sdev.accel = object_property_get_bool(obj, "accel", &error_abort); - sdev.ats = object_property_get_bool(obj, "ats", &error_abort); + sdev.ats = smmuv3_ats_enabled(ARM_SMMUV3(obj)); pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev); sbdev = SYS_BUS_DEVICE(obj); sdev.base = platform_bus_get_mmio_addr(pbus, sbdev, 0); diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -XXX,XX +XXX,XX @@ struct SMMUv3State { uint64_t msi_gpa; Error *migration_blocker; bool ril; - bool ats; + OnOffAuto ats; uint8_t oas; uint8_t ssidsize; }; @@ -XXX,XX +XXX,XX @@ struct SMMUv3Class { ResettablePhases parent_phases; }; +bool smmuv3_ats_enabled(struct SMMUv3State *s); + #define TYPE_ARM_SMMUV3 "arm-smmuv3" OBJECT_DECLARE_TYPE(SMMUv3State, SMMUv3Class, ARM_SMMUV3) -- 2.43.0
From: Nathan Chen <nathanc@nvidia.com> Change accel SMMUv3 RIL property from bool to OnOffAuto. The 'auto' value is not implemented, as this commit is meant to set the property to the correct type and avoid breaking JSON/QMP when the auto mode is introduced. A future patch will implement resolution of the 'auto' value to match the host SMMUv3 RIL support. The conversion of the RIL property type to OnOffAuto is an incompatible change for JSON/QMP when a bool value is expected for "ril", but the "ril" property is new in 11.0 and this patch is submitted as a fix to the property type. Fixes: bd715ff5bda9 ("hw/arm/smmuv3-accel: Add a property to specify RIL support") Tested-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Shameer Kolothum <skolothumtho@nvidia.com> Tested-by: Shameer Kolothum <skolothumtho@nvidia.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Acked-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Nathan Chen <nathanc@nvidia.com> Message-id: 20260323182454.1416110-4-nathanc@nvidia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/smmuv3-accel.c | 6 ++++-- hw/arm/smmuv3.c | 11 ++++++++--- include/hw/arm/smmuv3.h | 2 +- 3 files changed, 13 insertions(+), 6 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -XXX,XX +XXX,XX @@ void smmuv3_accel_idr_override(SMMUv3State *s) return; } - /* By default QEMU SMMUv3 has RIL. Update IDR3 if user has disabled it */ - s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, s->ril); + /* Only override RIL if user explicitly set OFF */ + if (s->ril == ON_OFF_AUTO_OFF) { + s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 0); + } /* QEMU SMMUv3 has no ATS. Advertise ATS if opt-in by property */ if (s->ats == ON_OFF_AUTO_ON) { diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -XXX,XX +XXX,XX @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp) error_setg(errp, "ats auto mode is not supported"); return false; } + if (s->ril == ON_OFF_AUTO_AUTO) { + error_setg(errp, "ril auto mode is not supported"); + return false; + } if (!s->accel) { - if (!s->ril) { + if (s->ril == ON_OFF_AUTO_OFF) { error_setg(errp, "ril can only be disabled if accel=on"); return false; } @@ -XXX,XX +XXX,XX @@ static const Property smmuv3_properties[] = { /* GPA of MSI doorbell, for SMMUv3 accel use. */ DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0), /* RIL can be turned off for accel cases */ - DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true), + DEFINE_PROP_ON_OFF_AUTO("ril", SMMUv3State, ril, ON_OFF_AUTO_ON), DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_OFF), DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0), @@ -XXX,XX +XXX,XX @@ static void smmuv3_class_init(ObjectClass *klass, const void *data) "Enable SMMUv3 accelerator support. Allows host SMMUv3 to be " "configured in nested mode for vfio-pci dev assignment"); object_class_property_set_description(klass, "ril", - "Disable range invalidation support (for accel=on)"); + "Disable range invalidation support (for accel=on). ril=auto " + "is not supported."); object_class_property_set_description(klass, "ats", "Enable/disable ATS support (for accel=on). Please ensure host " "platform has ATS support before enabling this. ats=auto is not " diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -XXX,XX +XXX,XX @@ struct SMMUv3State { struct SMMUv3AccelState *s_accel; uint64_t msi_gpa; Error *migration_blocker; - bool ril; + OnOffAuto ril; OnOffAuto ats; uint8_t oas; uint8_t ssidsize; -- 2.43.0
From: Nathan Chen <nathanc@nvidia.com> Introduce a new enum type property allowing to set a Substream ID size for HW-accelerated smmuv3. Values are auto and 0..20. The auto value allows SSID size property to be derived from host IOMMU capabilities. A value of 0 disables SubstreamID, while non-zero values specify the SSID size in bits. Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Tested-by: Shameer Kolothum <skolothumtho@nvidia.com> Acked-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Nathan Chen <nathanc@nvidia.com> Message-id: 20260323182454.1416110-5-nathanc@nvidia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/core/qdev-properties-system.c | 14 ++++++++++++++ include/hw/core/qdev-properties-system.h | 3 +++ qapi/misc-arm.json | 16 ++++++++++++++++ qapi/pragma.json | 1 + 4 files changed, 34 insertions(+) diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-system.c index XXXXXXX..XXXXXXX 100644 --- a/hw/core/qdev-properties-system.c +++ b/hw/core/qdev-properties-system.c @@ -XXX,XX +XXX,XX @@ #include "qapi/qapi-types-block.h" #include "qapi/qapi-types-machine.h" #include "qapi/qapi-types-migration.h" +#include "qapi/qapi-types-misc-arm.h" #include "qapi/qapi-visit-virtio.h" #include "qapi/qmp/qerror.h" #include "qemu/ctype.h" @@ -XXX,XX +XXX,XX @@ const PropertyInfo qdev_prop_zero_page_detection = { .set_default_value = qdev_propinfo_set_default_value_enum, }; +/* --- SsidSizeMode --- */ + +QEMU_BUILD_BUG_ON(sizeof(SsidSizeMode) != sizeof(int)); + +const PropertyInfo qdev_prop_ssidsize_mode = { + .type = "SsidSizeMode", + .description = "ssidsize mode: auto, 0-20", + .enum_table = &SsidSizeMode_lookup, + .get = qdev_propinfo_get_enum, + .set = qdev_propinfo_set_enum, + .set_default_value = qdev_propinfo_set_default_value_enum, +}; + /* --- Reserved Region --- */ /* diff --git a/include/hw/core/qdev-properties-system.h b/include/hw/core/qdev-properties-system.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/core/qdev-properties-system.h +++ b/include/hw/core/qdev-properties-system.h @@ -XXX,XX +XXX,XX @@ extern const PropertyInfo qdev_prop_multifd_compression; extern const PropertyInfo qdev_prop_mig_mode; extern const PropertyInfo qdev_prop_granule_mode; extern const PropertyInfo qdev_prop_zero_page_detection; +extern const PropertyInfo qdev_prop_ssidsize_mode; extern const PropertyInfo qdev_prop_losttickpolicy; extern const PropertyInfo qdev_prop_blockdev_on_error; extern const PropertyInfo qdev_prop_bios_chs_trans; @@ -XXX,XX +XXX,XX @@ extern const PropertyInfo qdev_prop_virtio_gpu_output_list; #define DEFINE_PROP_ZERO_PAGE_DETECTION(_n, _s, _f, _d) \ DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_zero_page_detection, \ ZeroPageDetection) +#define DEFINE_PROP_SSIDSIZE_MODE(_n, _s, _f, _d) \ + DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_ssidsize_mode, SsidSizeMode) #define DEFINE_PROP_LOSTTICKPOLICY(_n, _s, _f, _d) \ DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_losttickpolicy, \ LostTickPolicy) diff --git a/qapi/misc-arm.json b/qapi/misc-arm.json index XXXXXXX..XXXXXXX 100644 --- a/qapi/misc-arm.json +++ b/qapi/misc-arm.json @@ -XXX,XX +XXX,XX @@ # { "version": 3, "emulated": false, "kernel": true } ] } ## { 'command': 'query-gic-capabilities', 'returns': ['GICCapability'] } + +## +# @SsidSizeMode: +# +# SMMUv3 SubstreamID size configuration mode. +# +# @auto: derive from host IOMMU capabilities +# +# Values 0-20: SSIDSIZE value in bits. 0 disables SubstreamID. +# +# Since: 11.0 +## +{ 'enum': 'SsidSizeMode', + 'data': [ 'auto', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', + '10', '11', '12', '13', '14', '15', '16', '17', '18', + '19', '20' ] } # order matters, see ssidsize_mode_to_value() diff --git a/qapi/pragma.json b/qapi/pragma.json index XXXXXXX..XXXXXXX 100644 --- a/qapi/pragma.json +++ b/qapi/pragma.json @@ -XXX,XX +XXX,XX @@ 'S390CpuEntitlement', 'S390CpuPolarization', 'S390CpuState', + 'SsidSizeMode', 'String', 'StringWrapper', 'SysEmuTarget', -- 2.43.0
From: Nathan Chen <nathanc@nvidia.com> Change accel SMMUv3 SSIDSIZE property from uint8_t to SsidSizeMode. The 'auto' value is not implemented, as this commit is meant to set the property to the correct type and avoid breaking JSON/QMP when the auto mode is introduced. A future patch will implement resolution of 'auto' value to match the host SMMUv3 SSIDSIZE value. The conversion of the "ssidsize" property type to OnOffAuto is an incompatible change for JSON/QMP when a uint8_t value is expected for "ssidsize", but this property is new in 11.0 and this patch is submitted as a fix to the property type. Fixes: b8c6f8a69d27 ("hw/arm/smmuv3-accel: Make SubstreamID support configurable") Tested-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Shameer Kolothum <skolothumtho@nvidia.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Shameer Kolothum <skolothumtho@nvidia.com> Acked-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Nathan Chen <nathanc@nvidia.com> Message-id: 20260323182454.1416110-6-nathanc@nvidia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/smmuv3-accel.c | 23 +++++++++++++++++++++-- hw/arm/smmuv3.c | 19 ++++++++++--------- include/hw/arm/smmuv3-common.h | 1 - include/hw/arm/smmuv3.h | 3 ++- 4 files changed, 33 insertions(+), 13 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -XXX,XX +XXX,XX @@ static uint64_t smmuv3_accel_get_viommu_flags(void *opaque) SMMUState *bs = opaque; SMMUv3State *s = ARM_SMMUV3(bs); - if (s->ssidsize) { + if (s->ssidsize > SSID_SIZE_MODE_0) { flags |= VIOMMU_FLAG_PASID_SUPPORTED; } return flags; @@ -XXX,XX +XXX,XX @@ static const PCIIOMMUOps smmuv3_accel_ops = { .get_msi_direct_gpa = smmuv3_accel_get_msi_gpa, }; +/* + * This returns the value of a SsidSizeMode value offset by 1 to + * account for the enum values offset by 1 from actual values. + * + * SSID_SIZE_MODE_0 = 1, SSID_SIZE_MODE_1 = 2, etc. so return 0 + * if SSID_SIZE_MODE_0 is passed as input, return 1 if + * SSID_SIZE_MODE_1 is passed as input, etc. + */ +static uint8_t ssidsize_mode_to_value(SsidSizeMode mode) +{ + if (mode == SSID_SIZE_MODE_AUTO) { + return 0; + } + return mode - 1; +} + void smmuv3_accel_idr_override(SMMUv3State *s) { if (!s->accel) { @@ -XXX,XX +XXX,XX @@ void smmuv3_accel_idr_override(SMMUv3State *s) * By default QEMU SMMUv3 has no SubstreamID support. Update IDR1 if user * has enabled it. */ - s->idr[1] = FIELD_DP32(s->idr[1], IDR1, SSIDSIZE, s->ssidsize); + if (s->ssidsize > SSID_SIZE_MODE_0) { + s->idr[1] = FIELD_DP32(s->idr[1], IDR1, SSIDSIZE, + ssidsize_mode_to_value(s->ssidsize)); + } } /* Based on SMUUv3 GPBA.ABORT configuration, attach a corresponding HWPT */ diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -XXX,XX +XXX,XX @@ #include "qemu/bitops.h" #include "hw/core/irq.h" #include "hw/core/sysbus.h" +#include "hw/core/qdev-properties-system.h" #include "migration/blocker.h" #include "migration/vmstate.h" #include "hw/core/qdev-properties.h" @@ -XXX,XX +XXX,XX @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg, } /* Multiple context descriptors require SubstreamID support */ - if (!s->ssidsize && STE_S1CDMAX(ste) != 0) { + if (s->ssidsize == SSID_SIZE_MODE_0 && STE_S1CDMAX(ste) != 0) { qemu_log_mask(LOG_UNIMP, "SMMUv3: multiple S1 context descriptors require SubstreamID support. " "Configure ssidsize > 0 (requires accel=on)\n"); @@ -XXX,XX +XXX,XX @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp) error_setg(errp, "ril auto mode is not supported"); return false; } + if (s->ssidsize == SSID_SIZE_MODE_AUTO) { + error_setg(errp, "ssidsize auto mode is not supported"); + return false; + } if (!s->accel) { if (s->ril == ON_OFF_AUTO_OFF) { @@ -XXX,XX +XXX,XX @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp) error_setg(errp, "OAS must be 44 bits when accel=off"); return false; } - if (s->ssidsize) { + if (s->ssidsize > SSID_SIZE_MODE_0) { error_setg(errp, "ssidsize can only be set if accel=on"); return false; } @@ -XXX,XX +XXX,XX @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp) error_setg(errp, "OAS can only be set to 44 or 48 bits"); return false; } - if (s->ssidsize > SMMU_SSID_MAX_BITS) { - error_setg(errp, "ssidsize must be in the range 0 to %d", - SMMU_SSID_MAX_BITS); - return false; - } return true; } @@ -XXX,XX +XXX,XX @@ static const Property smmuv3_properties[] = { DEFINE_PROP_ON_OFF_AUTO("ril", SMMUv3State, ril, ON_OFF_AUTO_ON), DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_OFF), DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), - DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0), + DEFINE_PROP_SSIDSIZE_MODE("ssidsize", SMMUv3State, ssidsize, + SSID_SIZE_MODE_0), }; static void smmuv3_instance_init(Object *obj) @@ -XXX,XX +XXX,XX @@ static void smmuv3_class_init(ObjectClass *klass, const void *data) "A value of N allows SSIDs in the range [0 .. 2^N - 1]. " "Valid range is 0-20, where 0 disables SubstreamID support. " "Defaults to 0. A value greater than 0 is required to enable " - "PASID support."); + "PASID support. ssidsize=auto is not supported."); } static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, diff --git a/include/hw/arm/smmuv3-common.h b/include/hw/arm/smmuv3-common.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/smmuv3-common.h +++ b/include/hw/arm/smmuv3-common.h @@ -XXX,XX +XXX,XX @@ REG32(IDR1, 0x4) FIELD(IDR1, TABLES_PRESET, 30, 1) FIELD(IDR1, ECMDQ, 31, 1) -#define SMMU_SSID_MAX_BITS 20 #define SMMU_IDR1_SIDSIZE 16 #define SMMU_CMDQS 19 #define SMMU_EVENTQS 19 diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -XXX,XX +XXX,XX @@ #include "hw/arm/smmu-common.h" #include "qom/object.h" +#include "qapi/qapi-types-misc-arm.h" #define TYPE_SMMUV3_IOMMU_MEMORY_REGION "smmuv3-iommu-memory-region" @@ -XXX,XX +XXX,XX @@ struct SMMUv3State { OnOffAuto ril; OnOffAuto ats; uint8_t oas; - uint8_t ssidsize; + SsidSizeMode ssidsize; }; typedef enum { -- 2.43.0
From: Nathan Chen <nathanc@nvidia.com> Introduce a new enum type property allowing to set an Output Address Size. Values are auto, 32, 36, 40, 42, 44, 48, 52, and 56, where a value of N specifies an N-bit OAS. Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Tested-by: Shameer Kolothum <skolothumtho@nvidia.com> Acked-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Nathan Chen <nathanc@nvidia.com> Message-id: 20260323182454.1416110-7-nathanc@nvidia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/core/qdev-properties-system.c | 13 +++++++++++ include/hw/core/qdev-properties-system.h | 3 +++ qapi/misc-arm.json | 28 ++++++++++++++++++++++++ 3 files changed, 44 insertions(+) diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-system.c index XXXXXXX..XXXXXXX 100644 --- a/hw/core/qdev-properties-system.c +++ b/hw/core/qdev-properties-system.c @@ -XXX,XX +XXX,XX @@ const PropertyInfo qdev_prop_ssidsize_mode = { .set_default_value = qdev_propinfo_set_default_value_enum, }; +/* --- OasMode --- */ + +QEMU_BUILD_BUG_ON(sizeof(OasMode) != sizeof(int)); + +const PropertyInfo qdev_prop_oas_mode = { + .type = "OasMode", + .description = "oas mode: auto, 32, 36, 40, 42, 44, 48, 52, 56", + .enum_table = &OasMode_lookup, + .get = qdev_propinfo_get_enum, + .set = qdev_propinfo_set_enum, + .set_default_value = qdev_propinfo_set_default_value_enum, +}; + /* --- Reserved Region --- */ /* diff --git a/include/hw/core/qdev-properties-system.h b/include/hw/core/qdev-properties-system.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/core/qdev-properties-system.h +++ b/include/hw/core/qdev-properties-system.h @@ -XXX,XX +XXX,XX @@ extern const PropertyInfo qdev_prop_mig_mode; extern const PropertyInfo qdev_prop_granule_mode; extern const PropertyInfo qdev_prop_zero_page_detection; extern const PropertyInfo qdev_prop_ssidsize_mode; +extern const PropertyInfo qdev_prop_oas_mode; extern const PropertyInfo qdev_prop_losttickpolicy; extern const PropertyInfo qdev_prop_blockdev_on_error; extern const PropertyInfo qdev_prop_bios_chs_trans; @@ -XXX,XX +XXX,XX @@ extern const PropertyInfo qdev_prop_virtio_gpu_output_list; ZeroPageDetection) #define DEFINE_PROP_SSIDSIZE_MODE(_n, _s, _f, _d) \ DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_ssidsize_mode, SsidSizeMode) +#define DEFINE_PROP_OAS_MODE(_n, _s, _f, _d) \ + DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_oas_mode, OasMode) #define DEFINE_PROP_LOSTTICKPOLICY(_n, _s, _f, _d) \ DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_losttickpolicy, \ LostTickPolicy) diff --git a/qapi/misc-arm.json b/qapi/misc-arm.json index XXXXXXX..XXXXXXX 100644 --- a/qapi/misc-arm.json +++ b/qapi/misc-arm.json @@ -XXX,XX +XXX,XX @@ 'data': [ 'auto', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', '10', '11', '12', '13', '14', '15', '16', '17', '18', '19', '20' ] } # order matters, see ssidsize_mode_to_value() + +## +# @OasMode: +# +# SMMUv3 Output Address Size configuration mode. +# +# @auto: derive from host IOMMU capabilities +# +# @32: 32-bit output address size +# +# @36: 36-bit output address size +# +# @40: 40-bit output address size +# +# @42: 42-bit output address size +# +# @44: 44-bit output address size +# +# @48: 48-bit output address size +# +# @52: 52-bit output address size +# +# @56: 56-bit output address size +# +# Since: 11.0 +## +{ 'enum': 'OasMode', + 'data': [ 'auto', '32', '36', '40', '42', '44', '48', '52', '56' ] } -- 2.43.0
From: Nathan Chen <nathanc@nvidia.com> Change accel SMMUv3 OAS property from uint8_t to OasMode. The 'auto' value is not implemented, as this commit is meant to set the property to the correct type and avoid breaking JSON/QMP when the auto mode is introduced. A future patch will implement resolution of 'auto' value to match the host SMMUv3 OAS value. The conversion of the "oas" property type to OnOffAuto is an incompatible change for JSON/QMP when a uint8_t value is expected for "oas", but this property is new in 11.0 and this patch is submitted as a fix to the property type. Fixes: a015ac990fd3 ("hw/arm/smmuv3-accel: Add property to specify OAS bits") Tested-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Shameer Kolothum <skolothumtho@nvidia.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Shameer Kolothum <skolothumtho@nvidia.com> Acked-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Nathan Chen <nathanc@nvidia.com> Message-id: 20260323182454.1416110-8-nathanc@nvidia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/smmuv3-accel.c | 2 +- hw/arm/smmuv3.c | 17 +++++++++-------- include/hw/arm/smmuv3-common.h | 2 -- include/hw/arm/smmuv3.h | 2 +- 4 files changed, 11 insertions(+), 12 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -XXX,XX +XXX,XX @@ void smmuv3_accel_idr_override(SMMUv3State *s) } /* Advertise 48-bit OAS in IDR5 when requested (default is 44 bits). */ - if (s->oas == SMMU_OAS_48BIT) { + if (s->oas == OAS_MODE_48) { s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS_48); } diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -XXX,XX +XXX,XX @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp) error_setg(errp, "ssidsize auto mode is not supported"); return false; } + if (s->oas != OAS_MODE_44 && s->oas != OAS_MODE_48) { + error_setg(errp, "QEMU SMMUv3 model only implements 44 and 48 bit" + "OAS; other OasMode values are not supported"); + return false; + } if (!s->accel) { if (s->ril == ON_OFF_AUTO_OFF) { @@ -XXX,XX +XXX,XX @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp) error_setg(errp, "ats can only be enabled if accel=on"); return false; } - if (s->oas != SMMU_OAS_44BIT) { + if (s->oas > OAS_MODE_44) { error_setg(errp, "OAS must be 44 bits when accel=off"); return false; } @@ -XXX,XX +XXX,XX @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp) return false; } - if (s->oas != SMMU_OAS_44BIT && s->oas != SMMU_OAS_48BIT) { - error_setg(errp, "OAS can only be set to 44 or 48 bits"); - return false; - } - return true; } @@ -XXX,XX +XXX,XX @@ static const Property smmuv3_properties[] = { /* RIL can be turned off for accel cases */ DEFINE_PROP_ON_OFF_AUTO("ril", SMMUv3State, ril, ON_OFF_AUTO_ON), DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_OFF), - DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), + DEFINE_PROP_OAS_MODE("oas", SMMUv3State, oas, OAS_MODE_44), DEFINE_PROP_SSIDSIZE_MODE("ssidsize", SMMUv3State, ssidsize, SSID_SIZE_MODE_0), }; @@ -XXX,XX +XXX,XX @@ static void smmuv3_class_init(ObjectClass *klass, const void *data) "supported."); object_class_property_set_description(klass, "oas", "Specify Output Address Size (for accel=on). Supported values " - "are 44 or 48 bits. Defaults to 44 bits"); + "are 44 or 48 bits. Defaults to 44 bits. oas=auto is not " + "supported."); object_class_property_set_description(klass, "ssidsize", "Number of bits used to represent SubstreamIDs (SSIDs). " "A value of N allows SSIDs in the range [0 .. 2^N - 1]. " diff --git a/include/hw/arm/smmuv3-common.h b/include/hw/arm/smmuv3-common.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/smmuv3-common.h +++ b/include/hw/arm/smmuv3-common.h @@ -XXX,XX +XXX,XX @@ REG32(IDR5, 0x14) FIELD(IDR5, VAX, 10, 2); FIELD(IDR5, STALL_MAX, 16, 16); -#define SMMU_OAS_44BIT 44 -#define SMMU_OAS_48BIT 48 #define SMMU_IDR5_OAS_44 4 #define SMMU_IDR5_OAS_48 5 diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -XXX,XX +XXX,XX @@ struct SMMUv3State { Error *migration_blocker; OnOffAuto ril; OnOffAuto ats; - uint8_t oas; + OasMode oas; SsidSizeMode ssidsize; }; -- 2.43.0
From: Nathan Chen <nathanc@nvidia.com> Document arm-smmuv3 properties for setting HW-acceleration, Range Invalidation, and Address Translation Services support, as well as setting Output Address size and Substream ID size. Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Shameer Kolothum <skolothumtho@nvidia.com> Tested-by: Shameer Kolothum <skolothumtho@nvidia.com> Signed-off-by: Nathan Chen <nathanc@nvidia.com> Message-id: 20260323182454.1416110-9-nathanc@nvidia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- qemu-options.hx | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/qemu-options.hx b/qemu-options.hx index XXXXXXX..XXXXXXX 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -XXX,XX +XXX,XX @@ SRST ``aw-bits=val`` (val between 32 and 64, default depends on machine) This decides the address width of the IOVA address space. -``-device arm-smmuv3,primary-bus=id`` +``-device arm-smmuv3,primary-bus=id[,option=...]`` This is only supported by ``-machine virt`` (ARM). ``primary-bus=id`` Accepts either the default root complex (pcie.0) or a pxb-pcie based root complex. + ``accel=on|off`` (default: off) + Enables guest to leverage host SMMUv3 features for acceleration. + Enabling accel configures the host SMMUv3 in nested mode to support + vfio-pci passthrough. + + The following options are available when accel=on. + Note: 'auto' mode is not currently supported. + + ``ril=on|off`` (default: on) + Support for Range Invalidation, which allows the SMMUv3 driver to + invalidate TLB entries for a range of IOVAs at once instead of issuing + separate commands to invalidate each page. Must match with host SMMUv3 + Range Invalidation support. + + ``ats=on|off`` (default: off) + Support for Address Translation Services, which enables PCIe devices to + cache address translations in their local TLB and reduce latency. Host + SMMUv3 must support ATS in order to enable this feature for the vIOMMU. + + ``oas=val`` (supported values are 44 and 48. default: 44) + Sets the Output Address Size in bits. The value set here must be less + than or equal to the host SMMUv3's supported OAS, so that the + intermediate physical addresses (IPA) consumed by host SMMU for stage-2 + translation do not exceed the host's max supported IPA size. + + ``ssidsize=val`` (val between 0 and 20. default: 0) + Sets the Substream ID size in bits. When set to a non-zero value, + PASID capability is advertised to the vIOMMU and accelerated use cases + such as Shared Virtual Addressing (SVA) are supported. + ``-device amd-iommu[,option=...]`` Enables emulation of an AMD-Vi I/O Memory Management Unit (IOMMU). Only available with ``-machine q35``, it supports the following options: -- 2.43.0
v3->v4: Windows headers define an INT type which clashed with an enum value name in arm_gicv3_its.c... The following changes since commit eae587e8e3694b1aceab23239493fb4c7e1a80f5: Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-09-13' into staging (2021-09-13 11:00:30 +0100) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210913-3 for you to fetch changes up to 28e987a7e7edaa3ca7feeac65edca26145df8814: hw/arm/mps2.c: Mark internal-only I2C buses as 'full' (2021-09-13 21:01:08 +0100) ---------------------------------------------------------------- target-arm queue: * mark MPS2/MPS3 board-internal i2c buses as 'full' so that command line user-created devices are not plugged into them * Take an exception if PSTATE.IL is set * Support an emulated ITS in the virt board * Add support for kudo-bmc board * Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM * cadence_uart: Fix clock handling issues that prevented u-boot from running ---------------------------------------------------------------- Bin Meng (6): hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase hw/char: cadence_uart: Disable transmit when input clock is disabled hw/char: cadence_uart: Move clock/reset check to uart_can_receive() hw/char: cadence_uart: Convert to memop_with_attrs() ops hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read, write}() hw/char: cadence_uart: Log a guest error when device is unclocked or in reset Chris Rauer (1): hw/arm: Add support for kudo-bmc board. Marc Zyngier (1): hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM Peter Maydell (5): target/arm: Take an exception if PSTATE.IL is set qdev: Support marking individual buses as 'full' hw/arm/mps2-tz.c: Add extra data parameter to MakeDevFn hw/arm/mps2-tz.c: Mark internal-only I2C buses as 'full' hw/arm/mps2.c: Mark internal-only I2C buses as 'full' Richard Henderson (1): target/arm: Merge disas_a64_insn into aarch64_tr_translate_insn Shashi Mallela (9): hw/intc: GICv3 ITS initial framework hw/intc: GICv3 ITS register definitions added hw/intc: GICv3 ITS command queue framework hw/intc: GICv3 ITS Command processing hw/intc: GICv3 ITS Feature enablement hw/intc: GICv3 redistributor ITS processing tests/data/acpi/virt: Add IORT files for ITS hw/arm/virt: add ITS support in virt GIC tests/data/acpi/virt: Update IORT files for ITS docs/system/arm/nuvoton.rst | 1 + hw/intc/gicv3_internal.h | 188 ++++- include/hw/arm/virt.h | 2 + include/hw/intc/arm_gicv3_common.h | 13 + include/hw/intc/arm_gicv3_its_common.h | 32 +- include/hw/qdev-core.h | 24 + target/arm/cpu.h | 1 + target/arm/kvm_arm.h | 4 +- target/arm/syndrome.h | 5 + target/arm/translate.h | 2 + hw/arm/mps2-tz.c | 92 ++- hw/arm/mps2.c | 12 +- hw/arm/npcm7xx_boards.c | 34 + hw/arm/virt.c | 29 +- hw/char/cadence_uart.c | 61 +- hw/intc/arm_gicv3.c | 14 + hw/intc/arm_gicv3_common.c | 13 + hw/intc/arm_gicv3_cpuif.c | 7 +- hw/intc/arm_gicv3_dist.c | 5 +- hw/intc/arm_gicv3_its.c | 1322 ++++++++++++++++++++++++++++++++ hw/intc/arm_gicv3_its_common.c | 7 +- hw/intc/arm_gicv3_its_kvm.c | 2 +- hw/intc/arm_gicv3_redist.c | 153 +++- hw/misc/zynq_slcr.c | 31 +- softmmu/qdev-monitor.c | 7 +- target/arm/helper-a64.c | 1 + target/arm/helper.c | 8 + target/arm/kvm.c | 7 +- target/arm/translate-a64.c | 255 +++--- target/arm/translate.c | 21 + hw/intc/meson.build | 1 + tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.memhp | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.numamem | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.pxb | Bin 0 -> 124 bytes 35 files changed, 2144 insertions(+), 210 deletions(-) create mode 100644 hw/intc/arm_gicv3_its.c create mode 100644 tests/data/acpi/virt/IORT create mode 100644 tests/data/acpi/virt/IORT.memhp create mode 100644 tests/data/acpi/virt/IORT.numamem create mode 100644 tests/data/acpi/virt/IORT.pxb