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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.72.248; envelope-from=mohamed@unpredictable.fr; helo=outbound.ms.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1774294732407158500 Content-Type: text/plain; charset="utf-8" Prepare to have on-demand fetch of registers from the backend during faults Signed-off-by: Mohamed Mediouni --- target/i386/emulate/x86_emu.h | 3 +++ target/i386/emulate/x86_helpers.c | 28 ++++++++++++++++------------ target/i386/emulate/x86_mmu.c | 8 ++------ 3 files changed, 21 insertions(+), 18 deletions(-) diff --git a/target/i386/emulate/x86_emu.h b/target/i386/emulate/x86_emu.h index 4ed970bd53..a8d4c93098 100644 --- a/target/i386/emulate/x86_emu.h +++ b/target/i386/emulate/x86_emu.h @@ -28,6 +28,7 @@ struct x86_emul_ops { MMUTranslateResult (*mmu_gva_to_gpa) (CPUState *cpu, target_ulong gva,= uint64_t *gpa, MMUTranslateFlags flags); void (*read_segment_descriptor)(CPUState *cpu, struct x86_segment_desc= riptor *desc, enum X86Seg seg); + target_ulong (*read_cr) (CPUState *cpu, int cr); void (*handle_io)(CPUState *cpu, uint16_t port, void *data, int direct= ion, int size, int count); void (*simulate_rdmsr)(CPUState *cs); @@ -45,6 +46,8 @@ void x86_emul_raise_exception(CPUX86State *env, int excep= tion_index, int error_c =20 target_ulong read_reg(CPUX86State *env, int reg, int size); void write_reg(CPUX86State *env, int reg, target_ulong val, int size); +target_ulong x86_read_cr(CPUState *cpu, int cr); + target_ulong read_val_from_reg(void *reg_ptr, int size); void write_val_to_reg(void *reg_ptr, target_ulong val, int size); bool write_val_ext(CPUX86State *env, struct x86_decode_op *decode, target_= ulong val, int size); diff --git a/target/i386/emulate/x86_helpers.c b/target/i386/emulate/x86_he= lpers.c index ebbf40f2b0..336862e2c4 100644 --- a/target/i386/emulate/x86_helpers.c +++ b/target/i386/emulate/x86_helpers.c @@ -206,15 +206,25 @@ bool x86_read_call_gate(CPUState *cpu, struct x86_cal= l_gate *idt_desc, return true; } =20 -bool x86_is_protected(CPUState *cpu) -{ +target_ulong x86_read_cr(CPUState *cpu, int cr) { X86CPU *x86_cpu =3D X86_CPU(cpu); CPUX86State *env =3D &x86_cpu->env; - uint64_t cr0 =3D env->cr[0]; + + if (emul_ops->read_cr) { + return emul_ops->read_cr(cpu, cr); + } + return env->cr[cr]; +} + +bool x86_is_protected(CPUState *cpu) +{ + uint64_t cr0; + if (emul_ops->is_protected_mode) { return emul_ops->is_protected_mode(cpu); } =20 + cr0 =3D x86_read_cr(cpu, 0); return cr0 & CR0_PE_MASK; } =20 @@ -245,9 +255,7 @@ bool x86_is_long_mode(CPUState *cpu) =20 bool x86_is_la57(CPUState *cpu) { - X86CPU *x86_cpu =3D X86_CPU(cpu); - CPUX86State *env =3D &x86_cpu->env; - uint64_t is_la57 =3D env->cr[4] & CR4_LA57_MASK; + uint64_t is_la57 =3D x86_read_cr(cpu, 4) & CR4_LA57_MASK; return is_la57; } =20 @@ -259,18 +267,14 @@ bool x86_is_long64_mode(CPUState *cpu) =20 bool x86_is_paging_mode(CPUState *cpu) { - X86CPU *x86_cpu =3D X86_CPU(cpu); - CPUX86State *env =3D &x86_cpu->env; - uint64_t cr0 =3D env->cr[0]; + uint64_t cr0 =3D x86_read_cr(cpu, 0); =20 return cr0 & CR0_PG_MASK; } =20 bool x86_is_pae_enabled(CPUState *cpu) { - X86CPU *x86_cpu =3D X86_CPU(cpu); - CPUX86State *env =3D &x86_cpu->env; - uint64_t cr4 =3D env->cr[4]; + uint64_t cr4 =3D x86_read_cr(cpu, 4); =20 return cr4 & CR4_PAE_MASK; } diff --git a/target/i386/emulate/x86_mmu.c b/target/i386/emulate/x86_mmu.c index 670939acdb..ba0ebe4268 100644 --- a/target/i386/emulate/x86_mmu.c +++ b/target/i386/emulate/x86_mmu.c @@ -114,8 +114,6 @@ static bool get_pt_entry(CPUState *cpu, struct gpt_tran= slation *pt, static MMUTranslateResult test_pt_entry(CPUState *cpu, struct gpt_translat= ion *pt, int level, int *largeness, bool pae, MMUTranslat= eFlags flags) { - X86CPU *x86_cpu =3D X86_CPU(cpu); - CPUX86State *env =3D &x86_cpu->env; uint64_t pte =3D pt->pte[level]; =20 if (!pte_present(pte)) { @@ -130,7 +128,7 @@ static MMUTranslateResult test_pt_entry(CPUState *cpu, = struct gpt_translation *p *largeness =3D level; } =20 - uint32_t cr0 =3D env->cr[0]; + uint32_t cr0 =3D x86_read_cr(cpu, 0); /* check protection */ if (cr0 & CR0_WP_MASK) { if (mmu_validate_write(flags) && !pte_write_access(pte)) { @@ -184,11 +182,9 @@ static inline uint64_t large_page_gpa(struct gpt_trans= lation *pt, bool pae, static MMUTranslateResult walk_gpt(CPUState *cpu, target_ulong addr, MMUTr= anslateFlags flags, struct gpt_translation *pt, bool pae) { - X86CPU *x86_cpu =3D X86_CPU(cpu); - CPUX86State *env =3D &x86_cpu->env; int top_level, level; int largeness =3D 0; - target_ulong cr3 =3D env->cr[3]; + target_ulong cr3 =3D x86_read_cr(cpu, 3); uint64_t page_mask =3D pae ? PAE_PTE_PAGE_MASK : LEGACY_PTE_PAGE_MASK; MMUTranslateResult res; =20 --=20 2.50.1 (Apple Git-155)