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Tsirkin" , Igor Mammedov , Ani Sinha , Shannon Zhao , Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Eric Blake , Markus Armbruster , Shameer Kolothum , Matt Ochs , Nicolin Chen , Nathan Chen Subject: [PATCH v5 3/8] hw/arm/smmuv3-accel: Change "ril" property type to OnOffAuto Date: Mon, 23 Mar 2026 11:24:49 -0700 Message-ID: <20260323182454.1416110-4-nathanc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260323182454.1416110-1-nathanc@nvidia.com> References: <20260323182454.1416110-1-nathanc@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BYAPR06CA0031.namprd06.prod.outlook.com (2603:10b6:a03:d4::44) To DS2PR12MB9567.namprd12.prod.outlook.com (2603:10b6:8:27c::8) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PR12MB9567:EE_|CY8PR12MB8268:EE_ X-MS-Office365-Filtering-Correlation-Id: c585fcef-8d5f-4835-99f6-08de890981fc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c101::7; envelope-from=nathanc@nvidia.com; helo=BL0PR03CU003.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1774290406617154100 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Change accel SMMUv3 RIL property from bool to OnOffAuto. The 'auto' value is not implemented, as this commit is meant to set the property to the correct type and avoid breaking JSON/QMP when the auto mode is introduced. A future patch will implement resolution of the 'auto' value to match the host SMMUv3 RIL support. The conversion of the RIL property type to OnOffAuto is an incompatible change for JSON/QMP when a bool value is expected for "ril", but the "ril" property is new in 11.0 and this patch is submitted as a fix to the property type. Fixes: bd715ff5bda9 ("hw/arm/smmuv3-accel: Add a property to specify RIL su= pport") Tested-by: Eric Auger Reviewed-by: Shameer Kolothum Tested-by: Shameer Kolothum Reviewed-by: Eric Auger Acked-by: Markus Armbruster Signed-off-by: Nathan Chen --- hw/arm/smmuv3-accel.c | 6 ++++-- hw/arm/smmuv3.c | 11 ++++++++--- include/hw/arm/smmuv3.h | 2 +- 3 files changed, 13 insertions(+), 6 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index f21a6a9997..c31b64295e 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -823,8 +823,10 @@ void smmuv3_accel_idr_override(SMMUv3State *s) return; } =20 - /* By default QEMU SMMUv3 has RIL. Update IDR3 if user has disabled it= */ - s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, s->ril); + /* Only override RIL if user explicitly set OFF */ + if (s->ril =3D=3D ON_OFF_AUTO_OFF) { + s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, 0); + } =20 /* QEMU SMMUv3 has no ATS. Advertise ATS if opt-in by property */ if (s->ats =3D=3D ON_OFF_AUTO_ON) { diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index a683402a0c..ea285bdf64 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1975,9 +1975,13 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) error_setg(errp, "ats auto mode is not supported"); return false; } + if (s->ril =3D=3D ON_OFF_AUTO_AUTO) { + error_setg(errp, "ril auto mode is not supported"); + return false; + } =20 if (!s->accel) { - if (!s->ril) { + if (s->ril =3D=3D ON_OFF_AUTO_OFF) { error_setg(errp, "ril can only be disabled if accel=3Don"); return false; } @@ -2137,7 +2141,7 @@ static const Property smmuv3_properties[] =3D { /* GPA of MSI doorbell, for SMMUv3 accel use. */ DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0), /* RIL can be turned off for accel cases */ - DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true), + DEFINE_PROP_ON_OFF_AUTO("ril", SMMUv3State, ril, ON_OFF_AUTO_ON), DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_OFF), DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0), @@ -2167,7 +2171,8 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) "Enable SMMUv3 accelerator support. Allows host SMMUv3 to be " "configured in nested mode for vfio-pci dev assignment"); object_class_property_set_description(klass, "ril", - "Disable range invalidation support (for accel=3Don)"); + "Disable range invalidation support (for accel=3Don). ril=3Dauto " + "is not supported."); object_class_property_set_description(klass, "ats", "Enable/disable ATS support (for accel=3Don). Please ensure host " "platform has ATS support before enabling this. ats=3Dauto is not " diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index ce51a5b9b4..c35e599bbc 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -69,7 +69,7 @@ struct SMMUv3State { struct SMMUv3AccelState *s_accel; uint64_t msi_gpa; Error *migration_blocker; - bool ril; + OnOffAuto ril; OnOffAuto ats; uint8_t oas; uint8_t ssidsize; --=20 2.43.0