From nobody Fri Apr 3 22:35:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1774274339; cv=none; d=zohomail.com; s=zohoarc; b=JiC1mM6PJxuCoyQ/9bKyVnWjlSVgHrhZbxbEDD3szZvJDtJRIJEOTEEf/jJu/TV8n7Iv2tGGFFqjYiGSnygLXWckxBzHolOKN4sGpcZFfFheOojM9kcemEmyTusQm6eBhWWfGQTXum1sA/fa2Qi8IXotMggLUEG23J7bvJVI/co= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774274339; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=YCyjkeVZjehmvMqQkFEvROL42xs/v9qbwCcFiaYqzZg=; b=ZTfnFhtSqbmW/TSH/4TtWpcm0e3+bk812fp47rOWqceNJSxNl3X/5dFs17ZxZzWFfWt9k34Um10Cxe9J8m+Etem5IAxg7jaWiGz3Fa5cBftl7N1pX6jOAOQthG1m/gLuo6OAqnUydOKuxyac99FjaaP+uxXd5RgN3lUooWG+qrg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774274339499647.5859111986429; Mon, 23 Mar 2026 06:58:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w4fnd-0007m1-Je; Mon, 23 Mar 2026 09:58:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w4fna-0007ey-9s for qemu-devel@nongnu.org; Mon, 23 Mar 2026 09:58:30 -0400 Received: from linux.microsoft.com ([13.77.154.182]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w4fnW-0006ld-S3 for qemu-devel@nongnu.org; Mon, 23 Mar 2026 09:58:28 -0400 Received: from DESKTOP-TUU1E5L.localdomain (unknown [167.220.208.76]) by linux.microsoft.com (Postfix) with ESMTPSA id E81B720B7129; Mon, 23 Mar 2026 06:58:22 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com E81B720B7129 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1774274305; bh=YCyjkeVZjehmvMqQkFEvROL42xs/v9qbwCcFiaYqzZg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bNNnk4MMJ4vbAAJ2OXqT59mNqJKnUAZxhosxCIavInExD+4F65zTbDkNgopkDPB6K KY+mrlZr3rKPFY10z1h2XF0RWQotir9tHdsmjgbbO1OyZ+y8DhdvLHemRL/vOTQ2YN urxPXNOr1gN1l0e9CWXA6gsHzxzDa4wCNAD9cQxA= From: Magnus Kulke To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Wei Liu , Richard Henderson , Marcelo Tosatti , Marcel Apfelbaum , Wei Liu , Alex Williamson , Paolo Bonzini , Zhao Liu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Magnus Kulke , Magnus Kulke , "Michael S. Tsirkin" Subject: [RFC 02/32] target/i386/mshv: use generic FPU/xcr0 state Date: Mon, 23 Mar 2026 14:57:42 +0100 Message-Id: <20260323135812.383509-3-magnuskulke@linux.microsoft.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260323135812.383509-1-magnuskulke@linux.microsoft.com> References: <20260323135812.383509-1-magnuskulke@linux.microsoft.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=magnuskulke@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1774274340096154100 Content-Type: text/plain; charset="utf-8" Instead of using an mshv-specific FPU state representation we switch to the generic i386 representation of the registers. Signed-off-by: Magnus Kulke --- include/system/mshv_int.h | 15 +------- target/i386/mshv/mshv-cpu.c | 76 ++++++++++++++++++++++--------------- 2 files changed, 47 insertions(+), 44 deletions(-) diff --git a/include/system/mshv_int.h b/include/system/mshv_int.h index a142dd241a..e3d1867a77 100644 --- a/include/system/mshv_int.h +++ b/include/system/mshv_int.h @@ -58,19 +58,6 @@ typedef struct MshvMsiControl { #define mshv_vcpufd(cpu) (cpu->accel->cpufd) =20 /* cpu */ -typedef struct MshvFPU { - uint8_t fpr[8][16]; - uint16_t fcw; - uint16_t fsw; - uint8_t ftwx; - uint8_t pad1; - uint16_t last_opcode; - uint64_t last_ip; - uint64_t last_dp; - uint8_t xmm[16][16]; - uint32_t mxcsr; - uint32_t pad2; -} MshvFPU; =20 typedef enum MshvVmExit { MshvVmExitIgnore =3D 0, @@ -81,7 +68,7 @@ typedef enum MshvVmExit { void mshv_init_mmio_emu(void); int mshv_create_vcpu(int vm_fd, uint8_t vp_index, int *cpu_fd); void mshv_remove_vcpu(int vm_fd, int cpu_fd); -int mshv_configure_vcpu(const CPUState *cpu, const MshvFPU *fpu, uint64_t = xcr0); +int mshv_configure_vcpu(const CPUState *cpu); int mshv_run_vcpu(int vm_fd, CPUState *cpu, hv_message *msg, MshvVmExit *e= xit); int mshv_arch_load_regs(CPUState *cpu); int mshv_arch_store_regs(CPUState *cpu); diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index 9456e75277..78b218e596 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -108,6 +108,9 @@ static enum hv_register_name FPU_REGISTER_NAMES[26] =3D= { }; =20 static int set_special_regs(const CPUState *cpu); +static int get_generic_regs(CPUState *cpu, + struct hv_register_assoc *assocs, + size_t n_regs); =20 static int translate_gva(const CPUState *cpu, uint64_t gva, uint64_t *gpa, uint64_t flags) @@ -717,48 +720,65 @@ static int set_special_regs(const CPUState *cpu) return 0; } =20 -static int set_fpu(const CPUState *cpu, const struct MshvFPU *regs) +static int set_fpu(const CPUState *cpu) { struct hv_register_assoc assocs[ARRAY_SIZE(FPU_REGISTER_NAMES)]; union hv_register_value *value; - size_t fp_i; union hv_x64_fp_control_status_register *ctrl_status; union hv_x64_xmm_control_status_register *xmm_ctrl_status; int ret; size_t n_regs =3D ARRAY_SIZE(FPU_REGISTER_NAMES); + X86CPU *x86cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86cpu->env; + size_t i, fp_i; + bool valid; =20 /* first 16 registers are xmm0-xmm15 */ - for (size_t i =3D 0; i < 16; i++) { + for (i =3D 0; i < 16; i++) { assocs[i].name =3D FPU_REGISTER_NAMES[i]; value =3D &assocs[i].value; - memcpy(&value->reg128, ®s->xmm[i], 16); + value->reg128.low_part =3D env->xmm_regs[i].ZMM_Q(0); + value->reg128.high_part =3D env->xmm_regs[i].ZMM_Q(1); } =20 /* next 8 registers are fp_mmx0-fp_mmx7 */ - for (size_t i =3D 16; i < 24; i++) { - assocs[i].name =3D FPU_REGISTER_NAMES[i]; + for (i =3D 16; i < 24; i++) { fp_i =3D (i - 16); + assocs[i].name =3D FPU_REGISTER_NAMES[i]; value =3D &assocs[i].value; - memcpy(&value->reg128, ®s->fpr[fp_i], 16); + value->fp.mantissa =3D env->fpregs[fp_i].d.low; + value->fp.biased_exponent =3D env->fpregs[fp_i].d.high & 0x7FFF; + value->fp.sign =3D (env->fpregs[fp_i].d.high >> 15) & 0= x1; + value->fp.reserved =3D 0; } =20 /* last two registers are fp_control_status and xmm_control_status */ assocs[24].name =3D FPU_REGISTER_NAMES[24]; value =3D &assocs[24].value; ctrl_status =3D &value->fp_control_status; - ctrl_status->fp_control =3D regs->fcw; - ctrl_status->fp_status =3D regs->fsw; - ctrl_status->fp_tag =3D regs->ftwx; + + ctrl_status->fp_control =3D env->fpuc; + /* bits 11,12,13 are the top of stack pointer */ + ctrl_status->fp_status =3D (env->fpus & ~0x3800) | ((env->fpstt & 0x7)= << 11); + + ctrl_status->fp_tag =3D 0; + for (i =3D 0; i < 8; i++) { + valid =3D (env->fptags[i] =3D=3D 0); + if (valid) { + ctrl_status->fp_tag |=3D (1u << i); + } + } + ctrl_status->reserved =3D 0; - ctrl_status->last_fp_op =3D regs->last_opcode; - ctrl_status->last_fp_rip =3D regs->last_ip; + ctrl_status->last_fp_op =3D env->fpop; + ctrl_status->last_fp_rip =3D env->fpip; =20 assocs[25].name =3D FPU_REGISTER_NAMES[25]; value =3D &assocs[25].value; xmm_ctrl_status =3D &value->xmm_control_status; - xmm_ctrl_status->xmm_status_control =3D regs->mxcsr; - xmm_ctrl_status->xmm_status_control_mask =3D 0; - xmm_ctrl_status->last_fp_rdp =3D regs->last_dp; + xmm_ctrl_status->xmm_status_control =3D env->mxcsr; + xmm_ctrl_status->xmm_status_control_mask =3D 0x0000ffff; + xmm_ctrl_status->last_fp_rdp =3D env->fpdp; =20 ret =3D mshv_set_generic_regs(cpu, assocs, n_regs); if (ret < 0) { @@ -769,12 +789,15 @@ static int set_fpu(const CPUState *cpu, const struct = MshvFPU *regs) return 0; } =20 -static int set_xc_reg(const CPUState *cpu, uint64_t xcr0) +static int set_xc_reg(const CPUState *cpu) { int ret; + X86CPU *x86cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86cpu->env; + struct hv_register_assoc assoc =3D { .name =3D HV_X64_REGISTER_XFEM, - .value.reg64 =3D xcr0, + .value.reg64 =3D env->xcr0, }; =20 ret =3D mshv_set_generic_regs(cpu, &assoc, 1); @@ -785,8 +808,7 @@ static int set_xc_reg(const CPUState *cpu, uint64_t xcr= 0) return 0; } =20 -static int set_cpu_state(const CPUState *cpu, const MshvFPU *fpu_regs, - uint64_t xcr0) +static int set_cpu_state(const CPUState *cpu) { int ret; =20 @@ -798,11 +820,11 @@ static int set_cpu_state(const CPUState *cpu, const M= shvFPU *fpu_regs, if (ret < 0) { return ret; } - ret =3D set_fpu(cpu, fpu_regs); + ret =3D set_fpu(cpu); if (ret < 0) { return ret; } - ret =3D set_xc_reg(cpu, xcr0); + ret =3D set_xc_reg(cpu); if (ret < 0) { return ret; } @@ -951,8 +973,7 @@ static int setup_msrs(const CPUState *cpu) * CPUX86State *env =3D &x86cpu->env; * X86CPUTopoInfo *topo_info =3D &env->topo_info; */ -int mshv_configure_vcpu(const CPUState *cpu, const struct MshvFPU *fpu, - uint64_t xcr0) +int mshv_configure_vcpu(const CPUState *cpu) { int ret; int cpu_fd =3D mshv_vcpufd(cpu); @@ -969,7 +990,7 @@ int mshv_configure_vcpu(const CPUState *cpu, const stru= ct MshvFPU *fpu, return -1; } =20 - ret =3D set_cpu_state(cpu, fpu, xcr0); + ret =3D set_cpu_state(cpu); if (ret < 0) { error_report("failed to set cpu state"); return -1; @@ -986,14 +1007,9 @@ int mshv_configure_vcpu(const CPUState *cpu, const st= ruct MshvFPU *fpu, =20 static int put_regs(const CPUState *cpu) { - X86CPU *x86cpu =3D X86_CPU(cpu); - CPUX86State *env =3D &x86cpu->env; - MshvFPU fpu =3D {0}; int ret; =20 - memset(&fpu, 0, sizeof(fpu)); - - ret =3D mshv_configure_vcpu(cpu, &fpu, env->xcr0); + ret =3D mshv_configure_vcpu(cpu); if (ret < 0) { error_report("failed to configure vcpu"); return ret; --=20 2.34.1