From nobody Fri Apr 3 22:39:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1774274697; cv=none; d=zohomail.com; s=zohoarc; b=kimxmmOyFCuFSFE1zlYLqqDbW/gL/YdotIs7NbGlbsakKKw/FW5yYV2SNHLElV63H2G7werL924TQfUcYQd+l6Pu7D8nTmyieSh4hIEVSwGOzOr5veYEEijv+YBx4XZXBxvMNRCbaUvSBYk517ZKeJtuBnaQGkVDxYVgvnCKgTI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774274697; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=y5n6XcDjhdUcCeYhcYqonW1SGbx+ZfqghjHafqkUNaI=; b=Cf7grJy6L3eVeclCyyUWzYkHSFyzjy8vQug+rsjoxmOCeLf7mjl9EGzX3HDzjToXziAn7y7s0cbvrL4KEgQb2+uwMRnWDZt0iPgFVIHvhwig/L060sQ4gv7CiHz3pvkgIETvq5xG/YDluiChStEywaUhKmtS6cPjZaiPmh/rSNc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774274697338678.3533024443559; Mon, 23 Mar 2026 07:04:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w4frz-0003KL-9R; Mon, 23 Mar 2026 10:03:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w4fpE-0000qL-0f for qemu-devel@nongnu.org; Mon, 23 Mar 2026 10:00:17 -0400 Received: from linux.microsoft.com ([13.77.154.182]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w4fpB-00074K-Gs for qemu-devel@nongnu.org; Mon, 23 Mar 2026 10:00:11 -0400 Received: from DESKTOP-TUU1E5L.localdomain (unknown [167.220.208.76]) by linux.microsoft.com (Postfix) with ESMTPSA id C51A720B6F0C; Mon, 23 Mar 2026 06:59:55 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com C51A720B6F0C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1774274398; bh=y5n6XcDjhdUcCeYhcYqonW1SGbx+ZfqghjHafqkUNaI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rwms7er1i4rx+bIDzSkjhj8f3Yi4yf2DnOV4Ve4PgBWqy1b0o3Qrga5cwEz4KvVVh NOb5L5/myhhXAMBZA7FR+xWMBFIrwPcrxNrhlFiP44RW8i2rBbNMd8qmBUil3Esv70 v6BME3POxLDaMFlohJeDWwuViOE7ViTZ5W+zfF98= From: Magnus Kulke To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Wei Liu , Richard Henderson , Marcelo Tosatti , Marcel Apfelbaum , Wei Liu , Alex Williamson , Paolo Bonzini , Zhao Liu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Magnus Kulke , Magnus Kulke , "Michael S. Tsirkin" Subject: [RFC 27/32] target/i386/mshv: migrate pending ints/excs Date: Mon, 23 Mar 2026 14:58:07 +0100 Message-Id: <20260323135812.383509-28-magnuskulke@linux.microsoft.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260323135812.383509-1-magnuskulke@linux.microsoft.com> References: <20260323135812.383509-1-magnuskulke@linux.microsoft.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=magnuskulke@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1774274699905154100 Content-Type: text/plain; charset="utf-8" We use PENDING_INTERRUPTION, INTERRUPT_STATE, PENDING_EVENT hv registers to map and roundtrip from/to CPUX86State. We ignore HV_REGISTER_PENDING_EVENT1 which represent events for nested virt contexts, as we don't support nested virt with MSHV currently. Signed-off-by: Magnus Kulke --- include/hw/hyperv/hvgdk_mini.h | 3 + include/system/mshv_int.h | 13 +++ target/i386/mshv/mshv-cpu.c | 168 +++++++++++++++++++++++++++++++++ 3 files changed, 184 insertions(+) diff --git a/include/hw/hyperv/hvgdk_mini.h b/include/hw/hyperv/hvgdk_mini.h index 00daac0431..a88420fafe 100644 --- a/include/hw/hyperv/hvgdk_mini.h +++ b/include/hw/hyperv/hvgdk_mini.h @@ -28,6 +28,9 @@ typedef enum hv_register_name { =20 /* Pending Interruption Register */ HV_REGISTER_PENDING_INTERRUPTION =3D 0x00010002, + HV_REGISTER_INTERRUPT_STATE =3D 0x00010003, + HV_REGISTER_PENDING_EVENT0 =3D 0x00010004, + HV_REGISTER_PENDING_EVENT1 =3D 0x00010005, =20 /* X64 User-Mode Registers */ HV_X64_REGISTER_RAX =3D 0x00020000, diff --git a/include/system/mshv_int.h b/include/system/mshv_int.h index 7052f20a00..bc16b794b2 100644 --- a/include/system/mshv_int.h +++ b/include/system/mshv_int.h @@ -18,6 +18,19 @@ =20 struct mshv_get_set_vp_state; =20 +/* + * Interruption-type encoding, used by the hypervisor in + * hv_x64_pending_interruption_register.interruption_type + * See TLFS 6.0 section 7.9.2, p55 + * https://learn.microsoft.com/en-us/virtualization/hyper-v-on-windows/tlf= s/tlfs + */ +#define MSHV_HV_INTERRUPTION_TYPE_EXT_INT 0 +#define MSHV_HV_INTERRUPTION_TYPE_NMI 2 +#define MSHV_HV_INTERRUPTION_TYPE_HW_EXC 3 +#define MSHV_HV_INTERRUPTION_TYPE_SW_INT 4 +#define MSHV_HV_INTERRUPTION_TYPE_PRIV_SW_EXC 5 +#define MSHV_HV_INTERRUPTION_TYPE_SW_EXC 6 + typedef struct hyperv_message hv_message; =20 typedef struct MshvHvCallArgs { diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index 0b08f478ce..746987d62b 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -584,6 +584,164 @@ static int load_regs(CPUState *cpu) return 0; } =20 +static int get_vcpu_events(CPUState *cpu) +{ + X86CPU *x86cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86cpu->env; + struct hv_register_assoc assocs[] =3D { + { .name =3D HV_REGISTER_PENDING_INTERRUPTION }, + { .name =3D HV_REGISTER_INTERRUPT_STATE }, + { .name =3D HV_REGISTER_PENDING_EVENT0 }, + }; + union hv_x64_pending_interruption_register pending_int; + union hv_x64_interrupt_state_register int_state; + union hv_x64_pending_exception_event pending_exc; + int ret; + + ret =3D mshv_get_generic_regs(cpu, assocs, ARRAY_SIZE(assocs)); + if (ret < 0) { + error_report("failed to get vcpu event registers"); + return -1; + } + + pending_int.as_uint64 =3D assocs[0].value.reg64; + int_state.as_uint64 =3D assocs[1].value.reg64; + pending_exc =3D assocs[2].value.pending_exception_event; + + /* Clear previous state. injected ints/excs are blanked w/ -1 */ + env->interrupt_injected =3D -1; + env->soft_interrupt =3D 0; + env->exception_injected =3D 0; + env->exception_pending =3D 0; + env->exception_nr =3D -1; + env->has_error_code =3D 0; + env->error_code =3D 0; + env->exception_has_payload =3D 0; + env->exception_payload =3D 0; + env->nmi_injected =3D 0; + + if (pending_int.interruption_pending) { + switch (pending_int.interruption_type) { + case MSHV_HV_INTERRUPTION_TYPE_EXT_INT: + env->interrupt_injected =3D pending_int.interruption_vector; + break; + case MSHV_HV_INTERRUPTION_TYPE_NMI: + env->nmi_injected =3D 1; + break; + case MSHV_HV_INTERRUPTION_TYPE_HW_EXC: + env->exception_injected =3D 1; + env->exception_nr =3D pending_int.interruption_vector; + env->has_error_code =3D pending_int.deliver_error_code; + env->error_code =3D pending_int.error_code; + break; + case MSHV_HV_INTERRUPTION_TYPE_SW_INT: + env->interrupt_injected =3D pending_int.interruption_vector; + env->soft_interrupt =3D 1; + break; + case MSHV_HV_INTERRUPTION_TYPE_SW_EXC: + case MSHV_HV_INTERRUPTION_TYPE_PRIV_SW_EXC: + env->exception_injected =3D 1; + env->exception_nr =3D pending_int.interruption_vector; + env->has_error_code =3D pending_int.deliver_error_code; + env->error_code =3D pending_int.error_code; + break; + default: + error_report("unknown interruption type %u", + pending_int.interruption_type); + return -EINVAL; + } + } + + /* disabled for one instr after STI, MOV/POP SS, see hvf_store_events(= ) */ + if (int_state.interrupt_shadow) { + env->hflags |=3D HF_INHIBIT_IRQ_MASK; + } else { + env->hflags &=3D ~HF_INHIBIT_IRQ_MASK; + } + + /* see kvm_get_vcpu_events(), hvf_store_events() */ + if (int_state.nmi_masked) { + env->hflags2 |=3D HF2_NMI_MASK; + } else { + env->hflags2 &=3D ~HF2_NMI_MASK; + } + + /* HV_REGISTER_PENDING_EVENT0: pending exception not yet injected */ + if (pending_exc.event_pending) { + env->exception_pending =3D 1; + env->exception_nr =3D pending_exc.vector; + env->has_error_code =3D pending_exc.deliver_error_code; + env->error_code =3D pending_exc.error_code; + env->exception_has_payload =3D (pending_exc.exception_parameter != =3D 0); + env->exception_payload =3D pending_exc.exception_parameter; + } + + /* + * Ignoring HV_REGISTER_PENDING_EVENT1, virtualization fault events, M= SHV + * does not support nested virtualization. + */ + + return 0; +} + +static int set_vcpu_events(const CPUState *cpu) +{ + X86CPU *x86cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86cpu->env; + union hv_x64_pending_interruption_register pending_int =3D { 0 }; + union hv_x64_interrupt_state_register int_state =3D { 0 }; + union hv_x64_pending_exception_event pending_exc =3D { 0 }; + struct hv_register_assoc assocs[3]; + int ret; + + /* build pending_int from CPUX86State */ + if (env->exception_injected) { + pending_int.interruption_pending =3D 1; + pending_int.interruption_type =3D MSHV_HV_INTERRUPTION_TYPE_HW_= EXC; + pending_int.interruption_vector =3D env->exception_nr; + pending_int.deliver_error_code =3D env->has_error_code; + pending_int.error_code =3D env->error_code; + } else if (env->nmi_injected) { + pending_int.interruption_pending =3D 1; + pending_int.interruption_type =3D MSHV_HV_INTERRUPTION_TYPE_NMI; + pending_int.interruption_vector =3D EXCP02_NMI; + } else if (env->interrupt_injected >=3D 0) { + pending_int.interruption_pending =3D 1; + pending_int.interruption_type =3D env->soft_interrupt + ? MSHV_HV_INTERRUPTION_TYPE_SW_INT + : MSHV_HV_INTERRUPTION_TYPE_EXT_INT; + pending_int.interruption_vector =3D env->interrupt_injected; + } + + /* build int_state, normalize to bool */ + int_state.interrupt_shadow =3D !!(env->hflags & HF_INHIBIT_IRQ_MASK); + int_state.nmi_masked =3D !!(env->hflags2 & HF2_NMI_MASK); + + /* build pending_exc */ + if (env->exception_pending) { + pending_exc.event_pending =3D 1; + pending_exc.vector =3D env->exception_nr; + pending_exc.deliver_error_code =3D env->has_error_code; + pending_exc.error_code =3D env->error_code; + pending_exc.exception_parameter =3D env->exception_payload; + } + + assocs[0].name =3D HV_REGISTER_PENDING_INTERRUPTION; + assocs[0].value.reg64 =3D pending_int.as_uint64; + assocs[1].name =3D HV_REGISTER_INTERRUPT_STATE; + assocs[1].value.reg64 =3D int_state.as_uint64; + assocs[2].name =3D HV_REGISTER_PENDING_EVENT0; + assocs[2].value.pending_exception_event =3D pending_exc; + + ret =3D mshv_set_generic_regs(cpu, assocs, ARRAY_SIZE(assocs)); + if (ret < 0) { + error_report("failed to set vcpu event registers"); + return -1; + } + + return 0; +} + int mshv_arch_load_vcpu_state(CPUState *cpu) { int ret; @@ -623,6 +781,11 @@ int mshv_arch_load_vcpu_state(CPUState *cpu) return ret; } =20 + ret =3D get_vcpu_events(cpu); + if (ret < 0) { + return ret; + } + return 0; } =20 @@ -1138,6 +1301,11 @@ int mshv_arch_store_vcpu_state(const CPUState *cpu) return ret; } =20 + ret =3D set_vcpu_events(cpu); + if (ret < 0) { + return ret; + } + return 0; } =20 --=20 2.34.1