From nobody Fri Apr 3 22:22:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1774274605; cv=none; d=zohomail.com; s=zohoarc; b=UTw8FtTuLb+fFyN14q+2JGK3/5WzWFt1SaoNZ03PSZe85ZGhRHo/eKrapgq8HTmyVca8V/v4YDBcyJxuKQrZ+UgHwkRwWFVLvf1g3zmnIhZWU3VvdkS4dbi/0O5D9BVe1h2laP6EVmPLwv61IjgAxPLdU4Zc7AIFTDp6trCHvaI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774274605; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=kNzA8nCp9csQuvyKSQjGHIiPTieqMCR2YGTGwsfe1DM=; b=PXr7bWHqgrNBngA6vGi9EQfbTFdY5wyndf0SE3i4fLIdQtmdWnhgMAz7hx1YzfAH7FuIA0HTVTqIdcoRdIbL7gYijFgeyhH7iHcUqOnLSl7mafpNGhuhk1D5RdoUtvQ3TlsdmKmhY6ZQQU4xn9RLsyFQydZ2ooABc6yau+cqqLM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774274605328438.7251170156959; Mon, 23 Mar 2026 07:03:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w4frb-0002Zo-NV; Mon, 23 Mar 2026 10:02:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w4for-0000YQ-6J for qemu-devel@nongnu.org; Mon, 23 Mar 2026 09:59:52 -0400 Received: from linux.microsoft.com ([13.77.154.182]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w4fop-0006zc-5v for qemu-devel@nongnu.org; Mon, 23 Mar 2026 09:59:48 -0400 Received: from DESKTOP-TUU1E5L.localdomain (unknown [167.220.208.76]) by linux.microsoft.com (Postfix) with ESMTPSA id 6E01F20B6F20; Mon, 23 Mar 2026 06:59:30 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 6E01F20B6F20 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1774274373; bh=kNzA8nCp9csQuvyKSQjGHIiPTieqMCR2YGTGwsfe1DM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Z2x/rK1YVfd43elLLTjnYxDtiCBArIejTnoZ+7DgMuO1eQsCj9aW3kqk31goAXghj OS+QnP9pdprlU9bqLtMyvuy6rsmfFIb8jgQOZhpwdpeXiZZIHjk1Wd8Z/ob3VT81IM LPpcpAJ0/g719Qzm260FRSb8TerQrWfgkNClk+Lo= From: Magnus Kulke To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Wei Liu , Richard Henderson , Marcelo Tosatti , Marcel Apfelbaum , Wei Liu , Alex Williamson , Paolo Bonzini , Zhao Liu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Magnus Kulke , Magnus Kulke , "Michael S. Tsirkin" Subject: [RFC 20/32] target/i386/mshv: migrate MTRR MSRs Date: Mon, 23 Mar 2026 14:58:00 +0100 Message-Id: <20260323135812.383509-21-magnuskulke@linux.microsoft.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260323135812.383509-1-magnuskulke@linux.microsoft.com> References: <20260323135812.383509-1-magnuskulke@linux.microsoft.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=magnuskulke@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1774274606465158500 Content-Type: text/plain; charset="utf-8" This change roundtrips memory access/caching MSRs. The mapping scheme is a bit more elaborate on these, so we have added a special handling instead of individual entries in the MSR mapping table. Signed-off-by: Magnus Kulke --- target/i386/mshv/msr.c | 136 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 129 insertions(+), 7 deletions(-) diff --git a/target/i386/mshv/msr.c b/target/i386/mshv/msr.c index 6e53874787..240ee84447 100644 --- a/target/i386/mshv/msr.c +++ b/target/i386/mshv/msr.c @@ -74,6 +74,10 @@ static const MshvMsrEnvMap msr_env_map[] =3D { { HV_X64_MSR_SIMP, HV_REGISTER_SIMP, offsetof(CPUX86State, msr_hv_synic_msg_page) }, =20 + /* MTRR default type */ + { IA32_MSR_MTRR_DEF_TYPE, HV_X64_REGISTER_MSR_MTRR_DEF_TYPE, + offsetof(CPUX86State, mtrr_deftype) }, + /* Other */ =20 /* TODO: find out processor features that correlate to unsupported MSR= s. */ @@ -85,6 +89,98 @@ static const MshvMsrEnvMap msr_env_map[] =3D { offsetof(CPUX86State, spec_ctrl) }, }; =20 +/* + * The assocs have to be set according to this schema: + * 8 entries for 0-7 mtrr_base + * 8 entries for mtrr_mask 0-7 + * 11 entries for 1 x 64k, 2 x 16k, 8 x 4k fixed MTRR + * 27 total entries + */ + +#define MSHV_MTRR_MSR_COUNT 27 +#define MSHV_MSR_TOTAL_COUNT (ARRAY_SIZE(msr_env_map) + MSHV_MTRR_MSR_COUN= T) + +static void store_in_env_mtrr_phys(CPUState *cpu, + const struct hv_register_assoc *assocs, + size_t n_assocs) +{ + X86CPU *x86_cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86_cpu->env; + size_t i, fixed_offset; + hv_register_name hv_name; + uint64_t base, mask; + + assert(n_assocs =3D=3D MSHV_MTRR_MSR_COUNT); + + for (i =3D 0; i < MSR_MTRRcap_VCNT; i++) { + hv_name =3D HV_X64_REGISTER_MSR_MTRR_PHYS_BASE0 + i; + assert(assocs[i].name =3D=3D hv_name); + hv_name =3D HV_X64_REGISTER_MSR_MTRR_PHYS_MASK0 + i; + assert(assocs[i + MSR_MTRRcap_VCNT].name =3D=3D hv_name); + + base =3D assocs[i].value.reg64; + mask =3D assocs[i + MSR_MTRRcap_VCNT].value.reg64; + env->mtrr_var[i].base =3D base; + env->mtrr_var[i].mask =3D mask; + } + + /* fixed 1x 64, 2x 16, 8x 4 kB */ + fixed_offset =3D MSR_MTRRcap_VCNT * 2; + for (i =3D 0; i < 11; i++) { + hv_name =3D HV_X64_REGISTER_MSR_MTRR_FIX64K00000 + i; + assert(assocs[fixed_offset + i].name =3D=3D hv_name); + env->mtrr_fixed[i] =3D assocs[fixed_offset + i].value.reg64; + } +} + +/* + * The assocs have to be set according to this schema: + * 8 entries for 0-7 mtrr_base + * 8 entries for mtrr_mask 0-7 + * 11 entries for 1 x 64k, 2 x 16k, 8 x 4k fixed MTRR + * 27 total entries + */ +static void load_from_env_mtrr_phys(const CPUState *cpu, + struct hv_register_assoc *assocs, + size_t n_assocs) +{ + X86CPU *x86_cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86_cpu->env; + size_t i, fixed_offset; + uint64_t base, mask, fixed_value; + hv_register_name base_name, mask_name, fixed_name; + hv_register_assoc *assoc; + + assert(n_assocs =3D=3D MSHV_MTRR_MSR_COUNT); + + for (i =3D 0; i < MSR_MTRRcap_VCNT; i++) { + base =3D env->mtrr_var[i].base; + mask =3D env->mtrr_var[i].mask; + + base_name =3D HV_X64_REGISTER_MSR_MTRR_PHYS_BASE0 + i; + mask_name =3D HV_X64_REGISTER_MSR_MTRR_PHYS_MASK0 + i; + + assoc =3D &assocs[i]; + assoc->name =3D base_name; + assoc->value.reg64 =3D base; + + assoc =3D &assocs[i + MSR_MTRRcap_VCNT]; + assoc->name =3D mask_name; + assoc->value.reg64 =3D mask; + } + + /* fixed 1x 64, 2x 16, 8x 4 kB */ + fixed_offset =3D MSR_MTRRcap_VCNT * 2; + for (i =3D 0; i < 11; i++) { + fixed_name =3D HV_X64_REGISTER_MSR_MTRR_FIX64K00000 + i; + fixed_value =3D env->mtrr_fixed[i]; + + assoc =3D &assocs[fixed_offset + i]; + assoc->name =3D fixed_name; + assoc->value.reg64 =3D fixed_value; + } +} + int mshv_init_msrs(const CPUState *cpu) { int ret; @@ -126,8 +222,9 @@ static void store_in_env(CPUState *cpu, const struct hv= _register_assoc *assocs, union hv_register_value hv_value; ptrdiff_t offset; uint32_t hv_name; + size_t mtrr_index; =20 - assert(n_assocs <=3D (ARRAY_SIZE(msr_env_map))); + assert(n_assocs <=3D MSHV_MSR_TOTAL_COUNT); =20 for (i =3D 0, j =3D 0; i < ARRAY_SIZE(msr_env_map); i++) { hv_name =3D assocs[j].name; @@ -141,17 +238,38 @@ static void store_in_env(CPUState *cpu, const struct = hv_register_assoc *assocs, MSHV_ENV_FIELD(env, offset) =3D hv_value.reg64; j++; } + + mtrr_index =3D j; + store_in_env_mtrr_phys(cpu, &assocs[mtrr_index], MSHV_MTRR_MSR_COUNT); } =20 static void set_hv_name_in_assocs(struct hv_register_assoc *assocs, size_t n_assocs) { size_t i; + size_t mtrr_offset, mtrr_fixed_offset; + hv_register_name hv_name; + + assert(n_assocs =3D=3D MSHV_MSR_TOTAL_COUNT); =20 - assert(n_assocs =3D=3D ARRAY_SIZE(msr_env_map)); for (i =3D 0; i < ARRAY_SIZE(msr_env_map); i++) { assocs[i].name =3D msr_env_map[i].hv_name; } + + mtrr_offset =3D ARRAY_SIZE(msr_env_map); + for (i =3D 0; i < MSR_MTRRcap_VCNT; i++) { + hv_name =3D HV_X64_REGISTER_MSR_MTRR_PHYS_BASE0 + i; + assocs[mtrr_offset + i].name =3D hv_name; + hv_name =3D HV_X64_REGISTER_MSR_MTRR_PHYS_MASK0 + i; + assocs[mtrr_offset + MSR_MTRRcap_VCNT + i].name =3D hv_name; + } + + /* fixed 1x 64, 2x 16, 8x 4 kB */ + mtrr_fixed_offset =3D mtrr_offset + MSR_MTRRcap_VCNT * 2; + for (i =3D 0; i < 11; i++) { + hv_name =3D HV_X64_REGISTER_MSR_MTRR_FIX64K00000 + i; + assocs[mtrr_fixed_offset + i].name =3D hv_name; + } } =20 static bool msr_supported(uint32_t name) @@ -176,8 +294,8 @@ static bool msr_supported(uint32_t name) int mshv_get_msrs(CPUState *cpu) { int ret =3D 0; - size_t n_assocs =3D ARRAY_SIZE(msr_env_map); - struct hv_register_assoc assocs[ARRAY_SIZE(msr_env_map)]; + size_t n_assocs =3D MSHV_MSR_TOTAL_COUNT; + struct hv_register_assoc assocs[MSHV_MSR_TOTAL_COUNT]; size_t i, j; uint32_t name; =20 @@ -218,8 +336,9 @@ static void load_from_env(const CPUState *cpu, struct h= v_register_assoc *assocs, CPUX86State *env =3D &x86_cpu->env; ptrdiff_t offset; union hv_register_value *hv_value; + size_t mtrr_offset; =20 - assert(n_assocs =3D=3D ARRAY_SIZE(msr_env_map)); + assert(n_assocs =3D=3D MSHV_MSR_TOTAL_COUNT); =20 for (i =3D 0; i < ARRAY_SIZE(msr_env_map); i++) { mapping =3D &msr_env_map[i]; @@ -228,12 +347,15 @@ static void load_from_env(const CPUState *cpu, struct= hv_register_assoc *assocs, hv_value =3D &assocs[i].value; hv_value->reg64 =3D MSHV_ENV_FIELD(env, offset); } + + mtrr_offset =3D ARRAY_SIZE(msr_env_map); + load_from_env_mtrr_phys(cpu, &assocs[mtrr_offset], MSHV_MTRR_MSR_COUNT= ); } =20 int mshv_set_msrs(const CPUState *cpu) { - size_t n_assocs =3D ARRAY_SIZE(msr_env_map); - struct hv_register_assoc assocs[ARRAY_SIZE(msr_env_map)]; + size_t n_assocs =3D MSHV_MSR_TOTAL_COUNT; + struct hv_register_assoc assocs[MSHV_MSR_TOTAL_COUNT]; int ret; size_t i, j; =20 --=20 2.34.1