From nobody Fri Apr 3 22:38:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1774274315; cv=none; d=zohomail.com; s=zohoarc; b=Q8fETttnc3UjzLGS5GK2caH3FwhQlW2T5kPynHoKoa83ny47c3b7WvVC1d1WWK5JouPpwffHxQ8aYHfJ4akjo0KVK3xp3Oi3/CUK0jOQdJ2X8dVkz+F69bwQveFERPg+s0gDMd6IFZ5RY0nm6hMc1nAysRwXoBdN+UVzOwI7a9A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774274315; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Vlb84NjCXw4NOONm0D1TCpsCilPuQF2CzdK3RJxUGA0=; b=jDTlsDSjQR5RfOxdNsF87TAXcZGIQnCBUZ7k6KlwVewJdI7HiuDfSlUzUCppEHMstU62sLHbD6YGdIaYedWPB7nebKqQ8B0b5eUBivSJdVLys808Em6DotgLOoxIzLwLbUB39eonZS1+V2diXrja72Q6DWa8FPGFnqAFO0c2OR0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774274315651213.2008100914428; Mon, 23 Mar 2026 06:58:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w4fnZ-0007dT-Ag; Mon, 23 Mar 2026 09:58:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w4fnU-0007Up-W1 for qemu-devel@nongnu.org; Mon, 23 Mar 2026 09:58:25 -0400 Received: from linux.microsoft.com ([13.77.154.182]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w4fnT-0006lI-B7 for qemu-devel@nongnu.org; Mon, 23 Mar 2026 09:58:24 -0400 Received: from DESKTOP-TUU1E5L.localdomain (unknown [167.220.208.76]) by linux.microsoft.com (Postfix) with ESMTPSA id 48FE420B7128; Mon, 23 Mar 2026 06:58:19 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 48FE420B7128 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1774274302; bh=Vlb84NjCXw4NOONm0D1TCpsCilPuQF2CzdK3RJxUGA0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hMPwTB+rYS5v/mRxV8PZQqytZJKtgPFLB5uyyMkOElN7y1+GgbwuXj22di95cyzbK K4lxBjyhTOiK1hIm75uulI37nhlfaPPR57GBaNVHD72uJ03LSUxPdMQ42wwPysoTg6 WLQM3ODL2djcSElZW33m4Qaglx/h+FlI1JlyWIZw= From: Magnus Kulke To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Wei Liu , Richard Henderson , Marcelo Tosatti , Marcel Apfelbaum , Wei Liu , Alex Williamson , Paolo Bonzini , Zhao Liu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Magnus Kulke , Magnus Kulke , "Michael S. Tsirkin" Subject: [RFC 01/32] target/i386/mshv: use arch_load/store_reg fns Date: Mon, 23 Mar 2026 14:57:41 +0100 Message-Id: <20260323135812.383509-2-magnuskulke@linux.microsoft.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260323135812.383509-1-magnuskulke@linux.microsoft.com> References: <20260323135812.383509-1-magnuskulke@linux.microsoft.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=magnuskulke@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1774274317573158501 Content-Type: text/plain; charset="utf-8" Improved consistency around the naming of load/store register fn's. this is required since we want to roundtrip more registers in a migration than what's currently required for MMIO emulation. Signed-off-by: Magnus Kulke --- accel/mshv/mshv-all.c | 2 +- include/system/mshv_int.h | 6 ++--- target/i386/mshv/mshv-cpu.c | 52 ++++++++++++++----------------------- 3 files changed, 23 insertions(+), 37 deletions(-) diff --git a/accel/mshv/mshv-all.c b/accel/mshv/mshv-all.c index d4cc7f5371..7c0eb68a5b 100644 --- a/accel/mshv/mshv-all.c +++ b/accel/mshv/mshv-all.c @@ -650,7 +650,7 @@ static void mshv_cpu_synchronize_pre_loadvm(CPUState *c= pu) static void do_mshv_cpu_synchronize(CPUState *cpu, run_on_cpu_data arg) { if (!cpu->accel->dirty) { - int ret =3D mshv_load_regs(cpu); + int ret =3D mshv_arch_load_regs(cpu); if (ret < 0) { error_report("Failed to load registers for vcpu %d", cpu->cpu_index); diff --git a/include/system/mshv_int.h b/include/system/mshv_int.h index 35386c422f..a142dd241a 100644 --- a/include/system/mshv_int.h +++ b/include/system/mshv_int.h @@ -82,11 +82,9 @@ void mshv_init_mmio_emu(void); int mshv_create_vcpu(int vm_fd, uint8_t vp_index, int *cpu_fd); void mshv_remove_vcpu(int vm_fd, int cpu_fd); int mshv_configure_vcpu(const CPUState *cpu, const MshvFPU *fpu, uint64_t = xcr0); -int mshv_get_standard_regs(CPUState *cpu); -int mshv_get_special_regs(CPUState *cpu); int mshv_run_vcpu(int vm_fd, CPUState *cpu, hv_message *msg, MshvVmExit *e= xit); -int mshv_load_regs(CPUState *cpu); -int mshv_store_regs(CPUState *cpu); +int mshv_arch_load_regs(CPUState *cpu); +int mshv_arch_store_regs(CPUState *cpu); int mshv_set_generic_regs(const CPUState *cpu, const hv_register_assoc *as= socs, size_t n_regs); int mshv_arch_put_registers(const CPUState *cpu); diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index 2bc978deb2..9456e75277 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -107,6 +107,8 @@ static enum hv_register_name FPU_REGISTER_NAMES[26] =3D= { HV_X64_REGISTER_XMM_CONTROL_STATUS, }; =20 +static int set_special_regs(const CPUState *cpu); + static int translate_gva(const CPUState *cpu, uint64_t gva, uint64_t *gpa, uint64_t flags) { @@ -285,7 +287,7 @@ static int set_standard_regs(const CPUState *cpu) return 0; } =20 -int mshv_store_regs(CPUState *cpu) +int mshv_arch_store_regs(CPUState *cpu) { int ret; =20 @@ -295,6 +297,12 @@ int mshv_store_regs(CPUState *cpu) return -1; } =20 + ret =3D set_special_regs(cpu); + if (ret < 0) { + error_report("Failed to store speical registers"); + return ret; + } + return 0; } =20 @@ -323,7 +331,7 @@ static void populate_standard_regs(const hv_register_as= soc *assocs, rflags_to_lflags(env); } =20 -int mshv_get_standard_regs(CPUState *cpu) +static int get_standard_regs(CPUState *cpu) { struct hv_register_assoc assocs[ARRAY_SIZE(STANDARD_REGISTER_NAMES)]; int ret; @@ -401,8 +409,7 @@ static void populate_special_regs(const hv_register_ass= oc *assocs, cpu_set_apic_base(x86cpu->apic_state, assocs[16].value.reg64); } =20 - -int mshv_get_special_regs(CPUState *cpu) +static int get_special_regs(CPUState *cpu) { struct hv_register_assoc assocs[ARRAY_SIZE(SPECIAL_REGISTER_NAMES)]; int ret; @@ -422,17 +429,17 @@ int mshv_get_special_regs(CPUState *cpu) return 0; } =20 -int mshv_load_regs(CPUState *cpu) +int mshv_arch_load_regs(CPUState *cpu) { int ret; =20 - ret =3D mshv_get_standard_regs(cpu); + ret =3D get_standard_regs(cpu); if (ret < 0) { error_report("Failed to load standard registers"); return -1; } =20 - ret =3D mshv_get_special_regs(cpu); + ret =3D get_special_regs(cpu); if (ret < 0) { error_report("Failed to load special registers"); return -1; @@ -1103,16 +1110,16 @@ static int emulate_instruction(CPUState *cpu, int ret; x86_insn_stream stream =3D { .bytes =3D insn_bytes, .len =3D insn_len = }; =20 - ret =3D mshv_load_regs(cpu); + ret =3D mshv_arch_load_regs(cpu); if (ret < 0) { - error_report("failed to load registers"); + error_report("Failed to load registers"); return -1; } =20 decode_instruction_stream(env, &decode, &stream); exec_instruction(env, &decode); =20 - ret =3D mshv_store_regs(cpu); + ret =3D mshv_arch_store_regs(cpu); if (ret < 0) { error_report("failed to store registers"); return -1; @@ -1291,25 +1298,6 @@ static int handle_pio_non_str(const CPUState *cpu, return 0; } =20 -static int fetch_guest_state(CPUState *cpu) -{ - int ret; - - ret =3D mshv_get_standard_regs(cpu); - if (ret < 0) { - error_report("Failed to get standard registers"); - return -1; - } - - ret =3D mshv_get_special_regs(cpu); - if (ret < 0) { - error_report("Failed to get special registers"); - return -1; - } - - return 0; -} - static int read_memory(const CPUState *cpu, uint64_t initial_gva, uint64_t initial_gpa, uint64_t gva, uint8_t *data, size_t len) @@ -1429,9 +1417,9 @@ static int handle_pio_str(CPUState *cpu, hv_x64_io_po= rt_intercept_message *info) X86CPU *x86_cpu =3D X86_CPU(cpu); CPUX86State *env =3D &x86_cpu->env; =20 - ret =3D fetch_guest_state(cpu); + ret =3D mshv_arch_load_regs(cpu); if (ret < 0) { - error_report("Failed to fetch guest state"); + error_report("Failed to load registers"); return -1; } =20 @@ -1462,7 +1450,7 @@ static int handle_pio_str(CPUState *cpu, hv_x64_io_po= rt_intercept_message *info) =20 ret =3D set_x64_registers(cpu, reg_names, reg_values); if (ret < 0) { - error_report("Failed to set x64 registers"); + error_report("Failed to set RIP and RAX registers"); return -1; } =20 --=20 2.34.1