From nobody Fri Apr 3 22:25:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1774274707; cv=none; d=zohomail.com; s=zohoarc; b=VGI6xZhZE9ot/XQEmLmQtnYIzL9Uq2PEXbACbEKMOoFd304REkMyFFYvQNypvsknbdfCbFbQ6LeM/KFT+p7+5PkRuaQ5vvzSVtKyjlj/xnLNs2syyGGnlzbNSKFiWctQsiSgdty2SvgCVq726NGg8W9oEwB7tdHEl2r4p9YgHnk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774274707; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=5zQbl0qaIrXlqH8wQsSR333IBJGZhs7tX9K2NiD0c5Y=; b=MBIbIXYGoQ9mbDycAHh3UH6b1b2uxJIcoR76LcKLfjvJ6S+XdajQiQQJTLXnyzNT3u6tvIwuwTlCTk53qKRRqPRabT5sCr3WqE1E0Ol9cBOpWGMrY7h1YuwQ8Ls9EeJdWF8aKK8n87GFNA31r5MtJn35aAy0HSXp1jYM0Iu7M+0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774274707721916.4969142192962; Mon, 23 Mar 2026 07:05:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w4fqh-0001M5-9U; Mon, 23 Mar 2026 10:01:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w4foW-0000KK-O1 for qemu-devel@nongnu.org; Mon, 23 Mar 2026 09:59:32 -0400 Received: from linux.microsoft.com ([13.77.154.182]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w4foT-0006x8-CG for qemu-devel@nongnu.org; Mon, 23 Mar 2026 09:59:26 -0400 Received: from DESKTOP-TUU1E5L.localdomain (unknown [167.220.208.76]) by linux.microsoft.com (Postfix) with ESMTPSA id 630D820B6F08; Mon, 23 Mar 2026 06:59:11 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 630D820B6F08 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1774274354; bh=5zQbl0qaIrXlqH8wQsSR333IBJGZhs7tX9K2NiD0c5Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Q/ZRDX2XBm1qEzol0kfD+91lpBhi58V1oP9IFaZNPqfjB+VpBfxr4CFDE7GSxiFec ZuhS/USARHValeySyaF3TDKcDCniH5Wfq7Oh/Roq8fGlrNZwrsHeBV9WeBOF7k1wKN MOA0Jg1yGStijV4but70LbvZ1eZCWD8EiIqc1KeM= From: Magnus Kulke To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Wei Liu , Richard Henderson , Marcelo Tosatti , Marcel Apfelbaum , Wei Liu , Alex Williamson , Paolo Bonzini , Zhao Liu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Magnus Kulke , Magnus Kulke , "Michael S. Tsirkin" Subject: [RFC 15/32] target/i386/mshv: migrate LAPIC state Date: Mon, 23 Mar 2026 14:57:55 +0100 Message-Id: <20260323135812.383509-16-magnuskulke@linux.microsoft.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260323135812.383509-1-magnuskulke@linux.microsoft.com> References: <20260323135812.383509-1-magnuskulke@linux.microsoft.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=magnuskulke@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1774274710053154100 Content-Type: text/plain; charset="utf-8" This change implements loading and storing the hyperv lapic state as part of the load/store routines for a vcpu. The HyperV LAPIC is similar to the the split-irqchip in KVM, it will only handle MSI/X interrupts. PIC and IOAPIC have to be handled in userland. An opaque blob is added to the APICCommonState, guarded behind a flag, hence it will be covered by a migration, as we declare VMSTATE_BUFFER for the hv_lapic_state field. In the future we might want to introduce a dedicated class for MSHV, that would require us to wire up an IOAPIC delivery path to QEMU's userland emulation. Signed-off-by: Magnus Kulke --- hw/intc/apic_common.c | 3 ++ include/hw/i386/apic_internal.h | 5 +++ target/i386/mshv/mshv-cpu.c | 61 +++++++++++++++++++++++++++++++-- 3 files changed, 67 insertions(+), 2 deletions(-) diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c index bf4abc21d7..a7df870f1a 100644 --- a/hw/intc/apic_common.c +++ b/hw/intc/apic_common.c @@ -380,6 +380,9 @@ static const VMStateDescription vmstate_apic_common =3D= { VMSTATE_INT64(next_time, APICCommonState), VMSTATE_INT64(timer_expiry, APICCommonState), /* open-coded timer state */ +#ifdef CONFIG_MSHV + VMSTATE_BUFFER(hv_lapic_state, APICCommonState), +#endif VMSTATE_END_OF_LIST() }, .subsections =3D (const VMStateDescription * const []) { diff --git a/include/hw/i386/apic_internal.h b/include/hw/i386/apic_interna= l.h index 0cb06bbc76..6d4ccca4e8 100644 --- a/include/hw/i386/apic_internal.h +++ b/include/hw/i386/apic_internal.h @@ -23,6 +23,7 @@ =20 #include "cpu.h" #include "hw/i386/apic.h" +#include "hw/hyperv/hvgdk_mini.h" #include "system/memory.h" #include "qemu/timer.h" #include "target/i386/cpu-qom.h" @@ -188,6 +189,10 @@ struct APICCommonState { DeviceState *vapic; hwaddr vapic_paddr; /* note: persistence via kvmvapic */ uint32_t extended_log_dest; + +#ifdef CONFIG_MSHV + uint8_t hv_lapic_state[sizeof(struct hv_local_interrupt_controller_sta= te)]; +#endif }; =20 typedef struct VAPICState { diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index 54c262d8bc..906f5b0c3d 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -112,6 +112,25 @@ static int get_generic_regs(CPUState *cpu, struct hv_register_assoc *assocs, size_t n_regs); =20 +static int get_lapic(CPUState *cpu) +{ + X86CPU *x86cpu =3D X86_CPU(cpu); + APICCommonState *apic =3D APIC_COMMON(x86cpu->apic_state); + int cpu_fd =3D mshv_vcpufd(cpu); + int ret; + struct hv_local_interrupt_controller_state lapic_state =3D { 0 }; + + ret =3D mshv_get_lapic(cpu_fd, &lapic_state); + if (ret < 0) { + error_report("failed to get lapic state"); + return -1; + } + + memcpy(&apic->hv_lapic_state, &lapic_state, sizeof(lapic_state)); + + return 0; +} + static void populate_fpu(const hv_register_assoc *assocs, X86CPU *x86cpu) { union hv_register_value value; @@ -559,6 +578,11 @@ int mshv_arch_load_vcpu_state(CPUState *cpu) return ret; } =20 + ret =3D get_lapic(cpu); + if (ret < 0) { + return ret; + } + return 0; } =20 @@ -952,9 +976,11 @@ int mshv_set_vp_state(int cpu_fd, const struct mshv_ge= t_set_vp_state *state) =20 static int init_lint(const CPUState *cpu) { - int ret; + X86CPU *x86cpu =3D X86_CPU(cpu); + APICCommonState *apic =3D APIC_COMMON(x86cpu->apic_state); uint32_t *lvt_lint0, *lvt_lint1; int cpu_fd =3D mshv_vcpufd(cpu); + int ret; =20 struct hv_local_interrupt_controller_state lapic_state =3D { 0 }; ret =3D mshv_get_lapic(cpu_fd, &lapic_state); @@ -970,7 +996,32 @@ static int init_lint(const CPUState *cpu) =20 /* TODO: should we skip setting lapic if the values are the same? */ =20 - return mshv_set_lapic(cpu_fd, &lapic_state); + ret =3D mshv_set_lapic(cpu_fd, &lapic_state); + if (ret < 0) { + return -1; + } + + memcpy(apic->hv_lapic_state, &lapic_state, sizeof(lapic_state)); + + return 0; +} + +static int set_lapic(const CPUState *cpu) +{ + X86CPU *x86cpu =3D X86_CPU(cpu); + APICCommonState *apic =3D APIC_COMMON(x86cpu->apic_state); + int cpu_fd =3D mshv_vcpufd(cpu); + int ret; + + struct hv_local_interrupt_controller_state lapic_state =3D { 0 }; + memcpy(&lapic_state, &apic->hv_lapic_state, sizeof(lapic_state)); + ret =3D mshv_set_lapic(cpu_fd, &lapic_state); + if (ret < 0) { + error_report("failed to set lapic"); + return -1; + } + + return 0; } =20 int mshv_arch_store_vcpu_state(const CPUState *cpu) @@ -997,6 +1048,12 @@ int mshv_arch_store_vcpu_state(const CPUState *cpu) return ret; } =20 + /* INVARIANT: special regs (APIC_BASE) must be restored before LAPIC */ + ret =3D set_lapic(cpu); + if (ret < 0) { + return ret; + } + return 0; } =20 --=20 2.34.1