From nobody Thu Apr 2 01:31:55 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17742728127481022.2583671180524; Mon, 23 Mar 2026 06:33:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w4fOx-0000gV-TX; Mon, 23 Mar 2026 09:33:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w4fOQ-0000WA-NQ; Mon, 23 Mar 2026 09:32:30 -0400 Received: from zg8tmtyylji0my4xnjqumte4.icoremail.net ([162.243.164.118]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w4fOM-00028X-NE; Mon, 23 Mar 2026 09:32:30 -0400 Received: from prodtpl.icoremail.net (unknown [10.12.1.20]) by hzbj-icmmx-7 (Coremail) with SMTP id AQAAfwAXHmLhQMFpoE9sCA--.2502S2; Mon, 23 Mar 2026 21:32:17 +0800 (CST) Received: from phytium.com.cn (unknown [218.76.62.144]) by mail (Coremail) with SMTP id AQAAf8DwwZLcQMFp0nsEAA--.10052S6; Mon, 23 Mar 2026 21:32:16 +0800 (CST) From: Tao Tang To: Fabiano Rosas , Laurent Vivier , Paolo Bonzini Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Peter Maydell , Chen Baozi , Pierrick Bouvier , Chao Liu , Tao Tang Subject: [RFC v3 3/4] tests/qtest: Add qtest-attrs-test for memory access attrs Date: Mon, 23 Mar 2026 21:32:09 +0800 Message-Id: <20260323133210.1523868-4-tangtao1634@phytium.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260323133210.1523868-1-tangtao1634@phytium.com.cn> References: <20260323133210.1523868-1-tangtao1634@phytium.com.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8DwwZLcQMFp0nsEAA--.10052S6 X-CM-SenderInfo: pwdqw3tdrrljuu6sx5pwlxzhxfrphubq/1tbiAQADBWnAQfgOyQAAsQ Authentication-Results: hzbj-icmmx-7; spf=neutral smtp.mail=tangtao163 4@phytium.com.cn; X-Coremail-Antispam: 1Uk129KBjvAXoW3ZF47Kw4fZw4rKFW5GrW3KFg_yoW8Jr48Wo WfJF42q3W7t3W3Gr92krZ7CrWqq3y0kFsxJr4Iqw1UXF1xGF42yw13JFZxX3yrtw48J347 GFZ7Kr4Syrs7trn7n29KB7ZKAUJUUUU5529EdanIXcx71UUUUU7KY7ZEXasCq-sGcSsGvf J3UbIjqfuFe4nvWSU8nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UU UUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=162.243.164.118; envelope-from=tangtao1634@phytium.com.cn; helo=zg8tmtyylji0my4xnjqumte4.icoremail.net X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1774272814380158500 Content-Type: text/plain; charset="utf-8" Add qtest-attrs-test to exercise qtest memory access commands with attrs on both aarch64 and x86. The test covers: - Arm virt,secure=3Don: scalar and bulk accesses across non-secure, secure, and root spaces, plus negative coverage for realm and for non-secure accesses into secure-only RAM - x86 q35: normal accesses - libqtest-single *_attrs shortcut wrappers For negative cases, use qtest_raw_cmd() to check that accesses which miss the intended AddressSpace fail with ERR responses emitted via qtest_send_memtx_error(). On Arm, the test targets the virt machine's secure-only RAM window so that the requested attrs must select the correct address space. Also wire qtest-attrs-test into the aarch64 and i386/x86_64 qtest builds. Signed-off-by: Tao Tang --- tests/qtest/meson.build | 7 +- tests/qtest/qtest-attrs-test.c | 305 +++++++++++++++++++++++++++++++++ 2 files changed, 310 insertions(+), 2 deletions(-) create mode 100644 tests/qtest/qtest-attrs-test.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index be4fa627b5..87aa104d23 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -115,6 +115,7 @@ qtests_i386 =3D \ 'drive_del-test', 'cpu-plug-test', 'migration-test', + 'qtest-attrs-test', ] =20 if dbus_display and config_all_devices.has_key('CONFIG_VGA') @@ -249,7 +250,8 @@ qtests_arm =3D \ (config_all_devices.has_key('CONFIG_STM32L4X5_SOC') and config_all_devices.has_key('CONFIG_DM163')? ['dm163-test'] : []) + \ ['arm-cpu-features', - 'boot-serial-test'] + 'boot-serial-test', + 'qtest-attrs-test',] =20 # TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-tes= t unconditional qtests_aarch64 =3D \ @@ -270,7 +272,8 @@ qtests_aarch64 =3D \ ['arm-cpu-features', 'numa-test', 'boot-serial-test', - 'migration-test'] + 'migration-test', + 'qtest-attrs-test'] =20 qtests_s390x =3D \ qtests_filter + \ diff --git a/tests/qtest/qtest-attrs-test.c b/tests/qtest/qtest-attrs-test.c new file mode 100644 index 0000000000..85eb77344d --- /dev/null +++ b/tests/qtest/qtest-attrs-test.c @@ -0,0 +1,305 @@ +/* + * QTest for memory access with transaction attributes + * + * Verify optional attrs argument support for qtest memory commands. + * + * Copyright (c) 2026 Phytium Technology + * + * Author: + * Tao Tang + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "libqtest.h" +#include "libqtest-single.h" + +/* + * The Arm virt test uses both the default non-secure RAM at 0x4000_0000 a= nd + * the secure-only RAM window at 0x0e00_0000. The x86 q35 test only exerci= ses + * regular RAM that is visible from both the default and SMM address space= s. + */ +#define TEST_ADDR_OFFSET_NS 0x1000ULL +#define TEST_ADDR_OFFSET_S 0xe000000ULL +#define TEST_ARM_SEC_BASE 0x0ULL +#define TEST_ARM_NS_BASE 0x40000000ULL +#define TEST_X86_BASE 0x0ULL + +#define TEST_ADDR_ARM_S (TEST_ARM_SEC_BASE + TEST_ADDR_OFFSET_S) +#define TEST_ADDR_ARM_NS (TEST_ARM_NS_BASE + TEST_ADDR_OFFSET_NS) +#define TEST_ADDR_X86 (TEST_X86_BASE + TEST_ADDR_OFFSET_NS) + +#define ARM_MACHINE_ARGS "-machine virt,secure=3Don -accel tcg" +#define X86_MACHINE_ARGS "-machine q35,smm=3Don -m 1G -accel tcg" + +static void G_GNUC_PRINTF(2, 3) assert_qtest_error(QTestState *qts, + const char *fmt, ...) +{ + va_list ap; + g_autofree gchar *cmd =3D NULL; + g_auto(GStrv) response =3D NULL; + + va_start(ap, fmt); + cmd =3D g_strdup_vprintf(fmt, ap); + va_end(ap); + + response =3D qtest_raw_cmd(qts, "%s", cmd); + g_assert_cmpstr(response[0], =3D=3D, "ERR"); +} + +static void test_arm_scalar_attrs(void) +{ + QTestState *qts; + uint8_t val; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qts =3D qtest_init(ARM_MACHINE_ARGS); + + qtest_writeb_attrs(qts, TEST_ADDR_ARM_NS, 0x11, NULL); + val =3D qtest_readb_attrs(qts, TEST_ADDR_ARM_NS, NULL); + g_assert_cmpuint(val, =3D=3D, 0x11); + + qtest_writeb_attrs(qts, TEST_ADDR_ARM_NS + 0x1, 0x22, "space=3Dnon-sec= ure"); + val =3D qtest_readb_attrs(qts, TEST_ADDR_ARM_NS + 0x1, "space=3Dnon-se= cure"); + g_assert_cmpuint(val, =3D=3D, 0x22); + + qtest_writeb_attrs(qts, TEST_ADDR_ARM_S + 0x2, 0x33, "secure"); + val =3D qtest_readb_attrs(qts, TEST_ADDR_ARM_S + 0x2, "secure"); + g_assert_cmpuint(val, =3D=3D, 0x33); + + assert_qtest_error(qts, "writeb 0x%" PRIx64 " 0x44 space=3Drealm\n", + (uint64_t)(TEST_ADDR_ARM_S + 0x3)); + assert_qtest_error(qts, "readb 0x%" PRIx64 " space=3Drealm\n", + (uint64_t)(TEST_ADDR_ARM_S + 0x3)); + + qtest_writeb_attrs(qts, TEST_ADDR_ARM_S + 0x4, 0x55, "space=3Droot"); + val =3D qtest_readb_attrs(qts, TEST_ADDR_ARM_S + 0x4, "space=3Droot"); + g_assert_cmpuint(val, =3D=3D, 0x55); + + qtest_writeb_attrs(qts, TEST_ADDR_ARM_S + 0x5, 0x66, "space=3Dsecure"); + val =3D qtest_readb_attrs(qts, TEST_ADDR_ARM_S + 0x5, "space=3Dsecure"= ); + g_assert_cmpuint(val, =3D=3D, 0x66); + + qtest_writeb(qts, TEST_ADDR_ARM_NS + 0x6, 0x77); + val =3D qtest_readb(qts, TEST_ADDR_ARM_NS + 0x6); + g_assert_cmpuint(val, =3D=3D, 0x77); + val =3D qtest_readb_attrs(qts, TEST_ADDR_ARM_NS + 0x6, "space=3Dnon-se= cure"); + g_assert_cmpuint(val, =3D=3D, 0x77); + + assert_qtest_error(qts, "writeb 0x%" PRIx64 " 0x77 space=3Dnon-secure\= n", + (uint64_t)(TEST_ADDR_ARM_S + 0x7)); + assert_qtest_error(qts, "readb 0x%" PRIx64 " space=3Dnon-secure\n", + (uint64_t)(TEST_ADDR_ARM_S + 0x7)); + + qtest_quit(qts); +} + +static void test_arm_bulk_attrs(void) +{ + QTestState *qts; + uint8_t wbuf[16] =3D { + 0x00, 0x11, 0x22, 0x33, + 0x44, 0x55, 0x66, 0x77, + 0x88, 0x99, 0xaa, 0xbb, + 0xcc, 0xdd, 0xee, 0xff, + }; + uint8_t rbuf[16]; + size_t i; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qts =3D qtest_init(ARM_MACHINE_ARGS); + + qtest_memwrite_attrs(qts, TEST_ADDR_ARM_NS + 0x100, + wbuf, sizeof(wbuf), NULL); + qtest_memread_attrs(qts, TEST_ADDR_ARM_NS + 0x100, + rbuf, sizeof(rbuf), NULL); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_memwrite_attrs(qts, TEST_ADDR_ARM_NS + 0x200, + wbuf, sizeof(wbuf), "space=3Dnon-secure"); + qtest_memread_attrs(qts, TEST_ADDR_ARM_NS + 0x200, + rbuf, sizeof(rbuf), "space=3Dnon-secure"); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_memwrite_attrs(qts, TEST_ADDR_ARM_S + 0x300, + wbuf, sizeof(wbuf), "secure"); + qtest_memread_attrs(qts, TEST_ADDR_ARM_S + 0x300, + rbuf, sizeof(rbuf), "secure"); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_memset_attrs(qts, TEST_ADDR_ARM_S + 0x400, + 0xa5, sizeof(rbuf), "space=3Droot"); + qtest_memread_attrs(qts, TEST_ADDR_ARM_S + 0x400, + rbuf, sizeof(rbuf), "space=3Droot"); + for (i =3D 0; i < sizeof(rbuf); i++) { + g_assert_cmpuint(rbuf[i], =3D=3D, 0xa5); + } + + qtest_bufwrite_attrs(qts, TEST_ADDR_ARM_NS + 0x500, + wbuf, sizeof(wbuf), "space=3Dnon-secure"); + qtest_bufread_attrs(qts, TEST_ADDR_ARM_NS + 0x500, + rbuf, sizeof(rbuf), "space=3Dnon-secure"); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_bufwrite_attrs(qts, TEST_ADDR_ARM_S + 0x600, + wbuf, sizeof(wbuf), "secure"); + qtest_bufread_attrs(qts, TEST_ADDR_ARM_S + 0x600, + rbuf, sizeof(rbuf), "secure"); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_memwrite(qts, TEST_ADDR_ARM_NS + 0x700, wbuf, 4); + qtest_memread(qts, TEST_ADDR_ARM_NS + 0x700, rbuf, 4); + g_assert(memcmp(wbuf, rbuf, 4) =3D=3D 0); + + qtest_memset(qts, TEST_ADDR_ARM_NS + 0x710, 0xa5, 4); + qtest_memread(qts, TEST_ADDR_ARM_NS + 0x710, rbuf, 4); + for (i =3D 0; i < 4; i++) { + g_assert_cmpuint(rbuf[i], =3D=3D, 0xa5); + } + + qtest_bufwrite(qts, TEST_ADDR_ARM_NS + 0x720, wbuf, 4); + qtest_bufread(qts, TEST_ADDR_ARM_NS + 0x720, rbuf, 4); + g_assert(memcmp(wbuf, rbuf, 4) =3D=3D 0); + + assert_qtest_error(qts, "write 0x%" PRIx64 " 0x%zx 0x00112233 " + "space=3Dnon-secure\n", + (uint64_t)(TEST_ADDR_ARM_S + 0x730), + (size_t)4); + assert_qtest_error(qts, "read 0x%" PRIx64 " 0x%zx space=3Dnon-secure\n= ", + (uint64_t)(TEST_ADDR_ARM_S + 0x730), (size_t)4); + assert_qtest_error(qts, "memset 0x%" PRIx64 " 0x%zx 0xa5 " + "space=3Dnon-secure\n", + (uint64_t)(TEST_ADDR_ARM_S + 0x740), + (size_t)4); + assert_qtest_error(qts, "b64write 0x%" PRIx64 " 0x%zx AQIDBA=3D=3D " + "space=3Dnon-secure\n", + (uint64_t)(TEST_ADDR_ARM_S + 0x750), + (size_t)4); + assert_qtest_error(qts, "b64read 0x%" PRIx64 " 0x%zx space=3Dnon-secur= e\n", + (uint64_t)(TEST_ADDR_ARM_S + 0x750), (size_t)4); + + qtest_quit(qts); +} + +static void test_arm_single_shortcuts_attrs(void) +{ + uint8_t val; + uint8_t wbuf[4] =3D { 0x10, 0x20, 0x30, 0x40 }; + uint8_t rbuf[4]; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qtest_start(ARM_MACHINE_ARGS); + + writeb_attrs(TEST_ADDR_ARM_S + 0x700, 0x5a, "secure"); + val =3D readb_attrs(TEST_ADDR_ARM_S + 0x700, "secure"); + g_assert_cmpuint(val, =3D=3D, 0x5a); + + writel_attrs(TEST_ADDR_ARM_S + 0x704, + 0xa5a5a5a5, "space=3Droot"); + g_assert_cmphex(readl_attrs(TEST_ADDR_ARM_S + 0x704, "space=3Droot"), = =3D=3D, + 0xa5a5a5a5U); + + memwrite_attrs(TEST_ADDR_ARM_NS + 0x708, + wbuf, sizeof(wbuf), "space=3Dnon-secure"); + memread_attrs(TEST_ADDR_ARM_NS + 0x708, + rbuf, sizeof(rbuf), "space=3Dnon-secure"); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_end(); +} + +static void test_x86_scalar_attrs(void) +{ + QTestState *qts; + uint8_t val; + + if (!qtest_has_machine("q35")) { + g_test_skip("q35 machine not available"); + return; + } + + qts =3D qtest_init(X86_MACHINE_ARGS); + + qtest_writeb_attrs(qts, TEST_ADDR_X86, 0x11, NULL); + val =3D qtest_readb_attrs(qts, TEST_ADDR_X86, NULL); + g_assert_cmpuint(val, =3D=3D, 0x11); + val =3D qtest_readb_attrs(qts, TEST_ADDR_X86, "secure"); + g_assert_cmpuint(val, =3D=3D, 0x11); + + qtest_writeb_attrs(qts, TEST_ADDR_X86 + 0x1, 0x22, "secure"); + val =3D qtest_readb_attrs(qts, TEST_ADDR_X86 + 0x1, "secure"); + g_assert_cmpuint(val, =3D=3D, 0x22); + val =3D qtest_readb_attrs(qts, TEST_ADDR_X86 + 0x1, NULL); + g_assert_cmpuint(val, =3D=3D, 0x22); + + qtest_quit(qts); +} + +static void test_x86_bulk_attrs(void) +{ + QTestState *qts; + uint8_t wbuf[8] =3D { 1, 2, 3, 4, 5, 6, 7, 8 }; + uint8_t rbuf[8]; + size_t i; + + if (!qtest_has_machine("q35")) { + g_test_skip("q35 machine not available"); + return; + } + + qts =3D qtest_init(X86_MACHINE_ARGS); + + qtest_memwrite_attrs(qts, TEST_ADDR_X86 + 0x100, wbuf, sizeof(wbuf), N= ULL); + qtest_memread_attrs(qts, TEST_ADDR_X86 + 0x100, + rbuf, sizeof(rbuf), "secure"); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_memwrite_attrs(qts, TEST_ADDR_X86 + 0x180, + wbuf, sizeof(wbuf), "secure"); + qtest_memread_attrs(qts, TEST_ADDR_X86 + 0x180, + rbuf, sizeof(rbuf), NULL); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_memset_attrs(qts, TEST_ADDR_X86 + 0x200, + 0x3c, sizeof(rbuf), "secure"); + qtest_memread_attrs(qts, TEST_ADDR_X86 + 0x200, + rbuf, sizeof(rbuf), NULL); + for (i =3D 0; i < sizeof(rbuf); i++) { + g_assert_cmpuint(rbuf[i], =3D=3D, 0x3c); + } + + qtest_bufwrite_attrs(qts, TEST_ADDR_X86 + 0x280, + wbuf, sizeof(wbuf), NULL); + qtest_bufread_attrs(qts, TEST_ADDR_X86 + 0x280, + rbuf, sizeof(rbuf), "secure"); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_quit(qts); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + qtest_add_func("/qtest/arm/attrs/scalar", test_arm_scalar_attrs); + qtest_add_func("/qtest/arm/attrs/bulk", test_arm_bulk_attrs); + qtest_add_func("/qtest/arm/attrs/single_shortcuts", + test_arm_single_shortcuts_attrs); + qtest_add_func("/qtest/x86/attrs/scalar", test_x86_scalar_attrs); + qtest_add_func("/qtest/x86/attrs/bulk", test_x86_bulk_attrs); + + return g_test_run(); +} --=20 2.34.1