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The following changes since commit 8e711856d7639cbffa51405f2cc2366e3d9e3a23: Merge tag 'hppa-fixes-for-v11-pull-request' of https://github.com/hdeller/qemu-hppa into staging (2026-03-20 10:04:48 +0000) are available in the Git repository at: https://gitlab.com/pm215/qemu.git tags/pull-target-arm-20260323 for you to fetch changes up to b38859be76abf4d49f81f36317e6e37ab93121f0: hw/isa/piix: Embed i8259 irq in device state instead of allocating (2026-03-23 09:51:01 +0000) ---------------------------------------------------------------- target-arm queue: * tests/qtest/arm-cpu-features: Fix thinko in g_strdup_printf() call * configure: Remove unused variable default_cflags * whpx: arm: Various fixes, notably making '-cpu host' work * configs/targets: Restrict the legacy ldst_phys() API on ARM / Aarch64 * hw/isa/piix: Embed i8259 irq in device state instead of allocating ---------------------------------------------------------------- Mohamed Mediouni (5): whpx: arm: fix -cpu host whpx: arm: add EC_DATAABORT assert for WHvRunVpExitReasonGpaIntercept/UnmappedGpa whpx: arm: enable more enlightenments whpx: arm: remove comment bit that is no longer accurate target/arm: cpu: alter error message for host CPU type Osama Abdelkader (1): whpx: arm: fix ID_AA64MMFR3_EL1 host feature register index Peter Maydell (3): tests/qtest/arm-cpu-features: Fix thinko in g_strdup_printf() call configure: Remove unused variable default_cflags hw/isa/piix: Embed i8259 irq in device state instead of allocating Philippe Mathieu-Daudé (1): configs/targets: Restrict the legacy ldst_phys() API on ARM / Aarch64 configs/targets/aarch64-softmmu.mak | 1 + configs/targets/arm-softmmu.mak | 1 + configure | 2 -- hw/arm/virt.c | 2 +- hw/isa/piix.c | 11 ++++++----- include/hw/southbridge/piix.h | 3 +++ target/arm/cpu.c | 4 ++-- target/arm/whpx/whpx-all.c | 11 +++++++---- tests/qtest/arm-cpu-features.c | 2 +- 9 files changed, 22 insertions(+), 15 deletions(-)
In commit 62272f9f8891 we changed some uses of fixed char arrays to call g_strdup_printf() instead. In one place I made a silly error where in changing sprintf(name, "fmt string", ...) to name = g_strdup_printf("fmt string", ...) I forgot to delete "name" from the argument list. Luckily Coverity spotted this (as CID 1645771) because at this point "name" is NULL and passing g_strdup_printf() a NULL first argument is not valid. We didn't notice the mistake in testing or CI because this bit of code is only run if on an AArch64 host with KVM and SVE available. Correct the error by removing the stray function argument. Fixes: 62272f9f8891 ("tests/qtest/arm-cpu-features: Use g_strdup_printf() instead of char arrays") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@redhat.com> Message-id: 20260317111121.2062455-1-peter.maydell@linaro.org --- tests/qtest/arm-cpu-features.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index XXXXXXX..XXXXXXX 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data) * we need at least one vector length enabled. */ vq = __builtin_ffsll(vls); - name = g_strdup_printf(name, "sve%u", vq * 128); + name = g_strdup_printf("sve%u", vq * 128); error = g_strdup_printf("cannot disable %s", name); assert_error(qts, "host", error, "{ %s: false }", name); g_free(error); -- 2.43.0
configure has a variable default_cflags, which was originally added in commit bafe78ad3bc4c ("contrib/plugins: use an independent makefile") as part of it setting up the build environment for contrib/plugins, which at the time used make. However, we now build the plugins with meson, and in commit 55c84a72aba4 ("contrib/plugins: remove Makefile for contrib/plugins") we dropped the logic from configure that does that makefile setup, leaving default_cflags as an unused variable. shellcheck helpfully reports this: default_cflags='-O0 -g' ^------------^ SC2034 (warning): default_cflags appears unused. Verify use (or export if used externally). Remove the unused variable. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20260317120215.2075164-1-peter.maydell@linaro.org --- configure | 2 -- 1 file changed, 2 deletions(-) diff --git a/configure b/configure index XXXXXXX..XXXXXXX 100755 --- a/configure +++ b/configure @@ -XXX,XX +XXX,XX @@ for opt do esac done -default_cflags='-O2 -g' git_submodules_action="update" docs="auto" EXESUF="" @@ -XXX,XX +XXX,XX @@ for opt do meson_option_parse --enable-debug-graph-lock "" meson_option_parse --enable-debug-mutex "" meson_option_add -Doptimization=0 - default_cflags='-O0 -g' ;; --disable-tcg) tcg="disabled" ;; -- 2.43.0
From: Mohamed Mediouni <mohamed@unpredictable.fr> "hw/arm/virt: Register valid CPU types dynamically" went under my radar, so fix this for WHPX. Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Stefan Weil <sw@weilnetz.de> Message-id: 20260314221529.47841-2-mohamed@unpredictable.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -XXX,XX +XXX,XX @@ static GPtrArray *virt_get_valid_cpu_types(const MachineState *ms) if (target_aarch64()) { g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a53"))); g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a57"))); - if (kvm_enabled() || hvf_enabled()) { + if (kvm_enabled() || hvf_enabled() || whpx_enabled()) { g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("host"))); } } -- 2.43.0
From: Mohamed Mediouni <mohamed@unpredictable.fr> If we get anything else from Hyper-V there's a problem, so enforce this. Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Message-id: 20260314221529.47841-3-mohamed@unpredictable.fr Suggested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/whpx/whpx-all.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/whpx/whpx-all.c +++ b/target/arm/whpx/whpx-all.c @@ -XXX,XX +XXX,XX @@ int whpx_vcpu_run(CPUState *cpu) switch (vcpu->exit_ctx.ExitReason) { case WHvRunVpExitReasonGpaIntercept: case WHvRunVpExitReasonUnmappedGpa: + assert(syn_get_ec(vcpu->exit_ctx.MemoryAccess.Syndrome) == EC_DATAABORT); advance_pc = true; if (vcpu->exit_ctx.MemoryAccess.Syndrome & BIT(8)) { -- 2.43.0
From: Mohamed Mediouni <mohamed@unpredictable.fr> Unconditionally enable some more enlightenments for whpx. In particular, linux uses AccessVpRegs without checking availability and panics if it's not there, so it's important to expose it. We also had a duplicate line where we set AccessHypercallRegs = 1 twice; remove the duplicate. Microsoft’s VMM exposes SyncContext on arm64 and FastHypercallOutput regardless of architecture unconditionally, so add those two to match that configuration. Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Message-id: 20260314221529.47841-4-mohamed@unpredictable.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/whpx/whpx-all.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/whpx/whpx-all.c +++ b/target/arm/whpx/whpx-all.c @@ -XXX,XX +XXX,XX @@ int whpx_accel_init(AccelState *as, MachineState *ms) UINT32 whpx_cap_size; WHV_PARTITION_PROPERTY prop; WHV_CAPABILITY_FEATURES features; + WHV_SYNTHETIC_PROCESSOR_FEATURES_BANKS synthetic_features; MachineClass *mc = MACHINE_GET_CLASS(ms); int pa_range = 0; @@ -XXX,XX +XXX,XX @@ int whpx_accel_init(AccelState *as, MachineState *ms) } /* Enable synthetic processor features */ - WHV_SYNTHETIC_PROCESSOR_FEATURES_BANKS synthetic_features; memset(&synthetic_features, 0, sizeof(WHV_SYNTHETIC_PROCESSOR_FEATURES_BANKS)); synthetic_features.BanksCount = 1; @@ -XXX,XX +XXX,XX @@ int whpx_accel_init(AccelState *as, MachineState *ms) synthetic_features.Bank0.AccessPartitionReferenceTsc = 1; synthetic_features.Bank0.AccessHypercallRegs = 1; synthetic_features.Bank0.AccessVpIndex = 1; - synthetic_features.Bank0.AccessHypercallRegs = 1; synthetic_features.Bank0.TbFlushHypercalls = 1; synthetic_features.Bank0.AccessSynicRegs = 1; synthetic_features.Bank0.AccessSyntheticTimerRegs = 1; synthetic_features.Bank0.AccessIntrCtrlRegs = 1; synthetic_features.Bank0.SyntheticClusterIpi = 1; synthetic_features.Bank0.DirectSyntheticTimers = 1; + synthetic_features.Bank0.FastHypercallOutput = 1; + synthetic_features.Bank0.AccessVpRegs = 1; + synthetic_features.Bank0.SyncContext = 1; /* * On ARM64, have enlightenments off by default -- 2.43.0
From: Mohamed Mediouni <mohamed@unpredictable.fr> As of Windows 11 version 26H1, SME support shipped. However the MIT-licensed headers aren't updated yet. Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Message-id: 20260314221529.47841-5-mohamed@unpredictable.fr Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/whpx/whpx-all.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/whpx/whpx-all.c +++ b/target/arm/whpx/whpx-all.c @@ -XXX,XX +XXX,XX @@ static bool whpx_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) * Work needed for SVE support: * - SVE state save/restore * - any potentially needed VL management - * Also disable SME at the same time. (not currently supported by Hyper-V) + * Also disable SME at the same time. */ SET_IDREG(&ahcf->isar, ID_AA64PFR0, GET_IDREG(&ahcf->isar, ID_AA64PFR0) & ~R_ID_AA64PFR0_SVE_MASK); -- 2.43.0
From: Mohamed Mediouni <mohamed@unpredictable.fr> Make the error message for attempting to use 'host' on an unsupported accelerator match the check we're doing. Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20260314221529.47841-6-mohamed@unpredictable.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) * this is the first point where we can report it. */ if (cpu->host_cpu_probe_failed) { - if (!kvm_enabled() && !hvf_enabled()) { - error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); + if (!kvm_enabled() && !hvf_enabled() && !whpx_enabled()) { + error_setg(errp, "The 'host' CPU type can only be used with KVM, HVF or WHPX"); } else { error_setg(errp, "Failed to retrieve host CPU features"); } -- 2.43.0
From: Osama Abdelkader <osama.abdelkader@gmail.com> IdAa64Mmfr3El1 was stored in idregs[ID_AA64MMFR2_EL1_IDX], overwriting MMFR2 and leaving MMFR3 never set. Use ID_AA64MMFR3_EL1_IDX so the host MMFR3 value is stored in the correct slot. Fixes: f7fa2b88084 ("whpx: arm64: implement -cpu host") Signed-off-by: Osama Abdelkader <osama.abdelkader@gmail.com> Reviewed-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20260314221529.47841-7-mohamed@unpredictable.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/whpx/whpx-all.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/whpx/whpx-all.c +++ b/target/arm/whpx/whpx-all.c @@ -XXX,XX +XXX,XX @@ static bool whpx_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { WHvArm64RegisterIdAa64Mmfr0El1, &ahcf->isar.idregs[ID_AA64MMFR0_EL1_IDX] }, { WHvArm64RegisterIdAa64Mmfr1El1, &ahcf->isar.idregs[ID_AA64MMFR1_EL1_IDX] }, { WHvArm64RegisterIdAa64Mmfr2El1, &ahcf->isar.idregs[ID_AA64MMFR2_EL1_IDX] }, - { WHvArm64RegisterIdAa64Mmfr3El1, &ahcf->isar.idregs[ID_AA64MMFR2_EL1_IDX] } + { WHvArm64RegisterIdAa64Mmfr3El1, &ahcf->isar.idregs[ID_AA64MMFR3_EL1_IDX] } }; int i; -- 2.43.0
From: Philippe Mathieu-Daudé <philmd@linaro.org> Commit d751921cffd ("hw/arm/omap1: Remove omap_badwidth_* implementations") removed the last use of the legacy ldst_phys() API. Set the TARGET_NOT_USING_LEGACY_LDST_PHYS_API variable to hide the legacy API to the ARM / Aarch64 binaries, avoiding further API uses to creep in. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20260319104414.66367-1-philmd@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- configs/targets/aarch64-softmmu.mak | 1 + configs/targets/arm-softmmu.mak | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak index XXXXXXX..XXXXXXX 100644 --- a/configs/targets/aarch64-softmmu.mak +++ b/configs/targets/aarch64-softmmu.mak @@ -XXX,XX +XXX,XX @@ TARGET_XML_FILES= aarch64-core.xml aarch64-fpu.xml arm-core.xml arm-vfp.xml arm- # needed by boot.c TARGET_NEED_FDT=y TARGET_LONG_BITS=64 +TARGET_NOT_USING_LEGACY_LDST_PHYS_API=y diff --git a/configs/targets/arm-softmmu.mak b/configs/targets/arm-softmmu.mak index XXXXXXX..XXXXXXX 100644 --- a/configs/targets/arm-softmmu.mak +++ b/configs/targets/arm-softmmu.mak @@ -XXX,XX +XXX,XX @@ TARGET_XML_FILES= arm-core.xml arm-vfp.xml arm-vfp3.xml arm-vfp-sysregs.xml arm- # needed by boot.c TARGET_NEED_FDT=y TARGET_LONG_BITS=32 +TARGET_NOT_USING_LEGACY_LDST_PHYS_API=y -- 2.43.0
The pci_piix_realize() function's use of qemu_allocate_irqs() results in a memory leak: Direct leak of 8 byte(s) in 1 object(s) allocated from: #0 0x61045c7a1a43 in malloc (/home/pm215/qemu/build/san/qemu-system-mips+0x16f8a43) (BuildId: aa43d3865e0f1991b1fc04422b5570fe522b6fa7) #1 0x724cc3095ac9 in g_malloc (/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x62ac9) (BuildId: 116e142b9b52c8a4dfd403e759e71ab8f95d8bb3) #2 0x61045db72134 in qemu_extend_irqs /home/pm215/qemu/build/san/../../hw/core/irq.c:77:51 #3 0x61045cd7bf49 in pci_piix_realize /home/pm215/qemu/build/san/../../hw/isa/piix.c:318:35 #4 0x61045cf4533e in pci_qdev_realize /home/pm215/qemu/build/san/../../hw/pci/pci.c:2308:9 #5 0x61045db6cbca in device_set_realized /home/pm215/qemu/build/san/../../hw/core/qdev.c:523:13 #6 0x61045db86bd9 in property_set_bool /home/pm215/qemu/build/san/../../qom/object.c:2376:5 #7 0x61045db81c5e in object_property_set /home/pm215/qemu/build/san/../../qom/object.c:1450:5 #8 0x61045db8e2fc in object_property_set_qobject /home/pm215/qemu/build/san/../../qom/qom-qobject.c:28:10 #9 0x61045db8258f in object_property_set_bool /home/pm215/qemu/build/san/../../qom/object.c:1520:15 #10 0x61045db687aa in qdev_realize_and_unref /home/pm215/qemu/build/san/../../hw/core/qdev.c:283:11 #11 0x61045d892e21 in mips_malta_init /home/pm215/qemu/build/san/../../hw/mips/malta.c:1239:5 (The i386 PC sets the has-pic property to 'false', so this only affects the MIPS Malta board.) Fix this by embedding the i8259 irq in the device state instead of allocating it. This is a similar fix to the one we used for vt82c686 in commit 2225dc562a93dc, except that we use qemu_init_irq_child() instead of qemu_init_irq(). The behaviour is identical except that the _child() version avoids what would be a leak if we ever unrealized the device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20260309171258.1905205-1-peter.maydell@linaro.org --- hw/isa/piix.c | 11 ++++++----- include/hw/southbridge/piix.h | 3 +++ 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index XXXXXXX..XXXXXXX 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -XXX,XX +XXX,XX @@ static void pci_piix_realize(PCIDevice *dev, const char *uhci_type, /* PIC */ if (d->has_pic) { - qemu_irq *i8259_out_irq = qemu_allocate_irqs(piix_request_i8259_irq, d, - 1); - qemu_irq *i8259 = i8259_init(isa_bus, *i8259_out_irq); - size_t i; + qemu_irq *i8259; - for (i = 0; i < ISA_NUM_IRQS; i++) { + qemu_init_irq_child(OBJECT(dev), "i8259-irq", &d->i8259_irq, + piix_request_i8259_irq, d, 0); + i8259 = i8259_init(isa_bus, &d->i8259_irq); + + for (size_t i = 0; i < ISA_NUM_IRQS; i++) { d->isa_irqs_in[i] = i8259[i]; } diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -XXX,XX +XXX,XX @@ #include "hw/ide/pci.h" #include "hw/rtc/mc146818rtc.h" #include "hw/usb/hcd-uhci.h" +#include "hw/core/irq.h" /* PIRQRC[A:D]: PIRQx Route Control Registers */ #define PIIX_PIRQCA 0x60 @@ -XXX,XX +XXX,XX @@ struct PIIXState { qemu_irq cpu_intr; qemu_irq isa_irqs_in[ISA_NUM_IRQS]; + IRQState i8259_irq; + /* This member isn't used. Just for save/load compatibility */ int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; -- 2.43.0
v3->v4: Windows headers define an INT type which clashed with an enum value name in arm_gicv3_its.c... The following changes since commit eae587e8e3694b1aceab23239493fb4c7e1a80f5: Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-09-13' into staging (2021-09-13 11:00:30 +0100) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210913-3 for you to fetch changes up to 28e987a7e7edaa3ca7feeac65edca26145df8814: hw/arm/mps2.c: Mark internal-only I2C buses as 'full' (2021-09-13 21:01:08 +0100) ---------------------------------------------------------------- target-arm queue: * mark MPS2/MPS3 board-internal i2c buses as 'full' so that command line user-created devices are not plugged into them * Take an exception if PSTATE.IL is set * Support an emulated ITS in the virt board * Add support for kudo-bmc board * Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM * cadence_uart: Fix clock handling issues that prevented u-boot from running ---------------------------------------------------------------- Bin Meng (6): hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase hw/char: cadence_uart: Disable transmit when input clock is disabled hw/char: cadence_uart: Move clock/reset check to uart_can_receive() hw/char: cadence_uart: Convert to memop_with_attrs() ops hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read, write}() hw/char: cadence_uart: Log a guest error when device is unclocked or in reset Chris Rauer (1): hw/arm: Add support for kudo-bmc board. Marc Zyngier (1): hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM Peter Maydell (5): target/arm: Take an exception if PSTATE.IL is set qdev: Support marking individual buses as 'full' hw/arm/mps2-tz.c: Add extra data parameter to MakeDevFn hw/arm/mps2-tz.c: Mark internal-only I2C buses as 'full' hw/arm/mps2.c: Mark internal-only I2C buses as 'full' Richard Henderson (1): target/arm: Merge disas_a64_insn into aarch64_tr_translate_insn Shashi Mallela (9): hw/intc: GICv3 ITS initial framework hw/intc: GICv3 ITS register definitions added hw/intc: GICv3 ITS command queue framework hw/intc: GICv3 ITS Command processing hw/intc: GICv3 ITS Feature enablement hw/intc: GICv3 redistributor ITS processing tests/data/acpi/virt: Add IORT files for ITS hw/arm/virt: add ITS support in virt GIC tests/data/acpi/virt: Update IORT files for ITS docs/system/arm/nuvoton.rst | 1 + hw/intc/gicv3_internal.h | 188 ++++- include/hw/arm/virt.h | 2 + include/hw/intc/arm_gicv3_common.h | 13 + include/hw/intc/arm_gicv3_its_common.h | 32 +- include/hw/qdev-core.h | 24 + target/arm/cpu.h | 1 + target/arm/kvm_arm.h | 4 +- target/arm/syndrome.h | 5 + target/arm/translate.h | 2 + hw/arm/mps2-tz.c | 92 ++- hw/arm/mps2.c | 12 +- hw/arm/npcm7xx_boards.c | 34 + hw/arm/virt.c | 29 +- hw/char/cadence_uart.c | 61 +- hw/intc/arm_gicv3.c | 14 + hw/intc/arm_gicv3_common.c | 13 + hw/intc/arm_gicv3_cpuif.c | 7 +- hw/intc/arm_gicv3_dist.c | 5 +- hw/intc/arm_gicv3_its.c | 1322 ++++++++++++++++++++++++++++++++ hw/intc/arm_gicv3_its_common.c | 7 +- hw/intc/arm_gicv3_its_kvm.c | 2 +- hw/intc/arm_gicv3_redist.c | 153 +++- hw/misc/zynq_slcr.c | 31 +- softmmu/qdev-monitor.c | 7 +- target/arm/helper-a64.c | 1 + target/arm/helper.c | 8 + target/arm/kvm.c | 7 +- target/arm/translate-a64.c | 255 +++--- target/arm/translate.c | 21 + hw/intc/meson.build | 1 + tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.memhp | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.numamem | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.pxb | Bin 0 -> 124 bytes 35 files changed, 2144 insertions(+), 210 deletions(-) create mode 100644 hw/intc/arm_gicv3_its.c create mode 100644 tests/data/acpi/virt/IORT create mode 100644 tests/data/acpi/virt/IORT.memhp create mode 100644 tests/data/acpi/virt/IORT.numamem create mode 100644 tests/data/acpi/virt/IORT.pxb