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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1774216665; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=o/fT/Z4UXECEVdqdNfQV6ZbgaAiHfkFkpWrQvNThp/o=; b=U497dGxCPgoxy0WA1sLkmAvZLLmGixWFPzhfmLB+v21xkJRyMHaLFTAFUVtcQMGC0zxqv+ LdJQgBkhHfZbZgxpwelKRXouI3EGq+/+hPf+nSOsOpajjyMJ8mBnHtQDvrNM/SqLqXC4Fo 6jLGbXv87uN1+U2Zo3iYOv/k9fgHgd4= X-MC-Unique: LY5Rvsq6OpKBSE893V0vXw-1 X-Mimecast-MFC-AGG-ID: LY5Rvsq6OpKBSE893V0vXw_1774216660 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , Jamin Lin , Kane Chen , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH 1/3] hw/ssi/aspeed_smc: Convert mem ops to read/write_with_attrs for error handling Date: Sun, 22 Mar 2026 22:57:30 +0100 Message-ID: <20260322215732.387383-2-clg@redhat.com> In-Reply-To: <20260322215732.387383-1-clg@redhat.com> References: <20260322215732.387383-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1774216748656154100 Error conditions (invalid flash mode, unwritable flash, invalid data FIFO offset) now return MEMTX_ERROR instead of silently succeeding or returning undefined values. This allows the memory subsystem to properly propagate transaction errors to the guest, improving QEMU reliability. Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3335 Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Jamin Lin --- hw/ssi/aspeed_smc.c | 58 ++++++++++++++++++++++++++------------------- 1 file changed, 34 insertions(+), 24 deletions(-) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index ed6cedabcb3b..b14b1cbddfc3 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -502,17 +502,18 @@ static void aspeed_smc_flash_setup(AspeedSMCFlash *fl= , uint32_t addr) } } =20 -static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned = size) +static MemTxResult aspeed_smc_flash_read(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, MemTxAttrs= attrs) { AspeedSMCFlash *fl =3D opaque; AspeedSMCState *s =3D fl->controller; - uint64_t ret =3D 0; int i; =20 + *data =3D 0; switch (aspeed_smc_flash_mode(fl)) { case CTRL_USERMODE: for (i =3D 0; i < size; i++) { - ret |=3D (uint64_t) ssi_transfer(s->spi, 0x0) << (8 * i); + *data |=3D (uint64_t) ssi_transfer(s->spi, 0x0) << (8 * i); } break; case CTRL_READMODE: @@ -521,18 +522,19 @@ static uint64_t aspeed_smc_flash_read(void *opaque, h= waddr addr, unsigned size) aspeed_smc_flash_setup(fl, addr); =20 for (i =3D 0; i < size; i++) { - ret |=3D (uint64_t) ssi_transfer(s->spi, 0x0) << (8 * i); + *data |=3D (uint64_t) ssi_transfer(s->spi, 0x0) << (8 * i); } =20 aspeed_smc_flash_unselect(fl); break; default: aspeed_smc_error("invalid flash mode %d", aspeed_smc_flash_mode(fl= )); + return MEMTX_ERROR; } =20 - trace_aspeed_smc_flash_read(fl->cs, addr, size, ret, + trace_aspeed_smc_flash_read(fl->cs, addr, size, *data, aspeed_smc_flash_mode(fl)); - return ret; + return MEMTX_OK; } =20 /* @@ -633,8 +635,8 @@ static bool aspeed_smc_do_snoop(AspeedSMCFlash *fl, ui= nt64_t data, return false; } =20 -static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t dat= a, - unsigned size) +static MemTxResult aspeed_smc_flash_write(void *opaque, hwaddr addr, + uint64_t data, unsigned size, MemTxAttr= s attrs) { AspeedSMCFlash *fl =3D opaque; AspeedSMCState *s =3D fl->controller; @@ -645,7 +647,7 @@ static void aspeed_smc_flash_write(void *opaque, hwaddr= addr, uint64_t data, =20 if (!aspeed_smc_is_writable(fl)) { aspeed_smc_error("flash is not writable at 0x%" HWADDR_PRIx, addr); - return; + return MEMTX_ERROR; } =20 switch (aspeed_smc_flash_mode(fl)) { @@ -670,12 +672,15 @@ static void aspeed_smc_flash_write(void *opaque, hwad= dr addr, uint64_t data, break; default: aspeed_smc_error("invalid flash mode %d", aspeed_smc_flash_mode(fl= )); + return MEMTX_ERROR; } + + return MEMTX_OK; } =20 static const MemoryRegionOps aspeed_smc_flash_ops =3D { - .read =3D aspeed_smc_flash_read, - .write =3D aspeed_smc_flash_write, + .read_with_attrs =3D aspeed_smc_flash_read, + .write_with_attrs =3D aspeed_smc_flash_write, .endianness =3D DEVICE_LITTLE_ENDIAN, .valid =3D { .min_access_size =3D 1, @@ -763,7 +768,8 @@ static void aspeed_smc_reset(DeviceState *d) s->snoop_dummies =3D 0; } =20 -static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int si= ze) +static MemTxResult aspeed_smc_read(void *opaque, hwaddr addr, uint64_t *da= ta, + unsigned int size, MemTxAttrs attrs) { AspeedSMCState *s =3D ASPEED_SMC(opaque); AspeedSMCClass *asc =3D ASPEED_SMC_GET_CLASS(opaque); @@ -792,7 +798,7 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr ad= dr, unsigned int size) =20 trace_aspeed_smc_read(addr << 2, size, s->regs[addr]); =20 - return s->regs[addr]; + *data =3D s->regs[addr]; } else if (aspeed_smc_has_data_fifo(asc) && addr >=3D R_DATA_FIFO) { cs =3D asc->data_fifo_offset_to_cs(s, addr << 2); if (cs >=3D 0) { @@ -801,15 +807,17 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr = addr, unsigned int size) * The flash address is provided by the SPI command/address cy= cles, * the MMIO addr parameter is ignored. */ - return aspeed_smc_flash_read(&s->flashes[cs], 0, size); + return aspeed_smc_flash_read(&s->flashes[cs], 0, data, size, a= ttrs); } aspeed_smc_error("Invalid data fifo offset %" HWADDR_PRIx, addr <<= 2); - return -1; + *data =3D -1; + return MEMTX_ERROR; } else { qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\= n", __func__, addr); - return -1; + *data =3D -1; } + return MEMTX_OK; } =20 static uint8_t aspeed_smc_hclk_divisor(uint8_t hclk_mask) @@ -1130,8 +1138,8 @@ static void aspeed_2600_smc_dma_ctrl(AspeedSMCState *= s, uint32_t dma_ctrl) s->regs[R_DMA_CTRL] &=3D ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT); } =20 -static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data, - unsigned int size) +static MemTxResult aspeed_smc_write(void *opaque, hwaddr addr, uint64_t da= ta, + unsigned int size, MemTxAttrs attrs) { AspeedSMCState *s =3D ASPEED_SMC(opaque); AspeedSMCClass *asc =3D ASPEED_SMC_GET_CLASS(s); @@ -1186,19 +1194,21 @@ static void aspeed_smc_write(void *opaque, hwaddr a= ddr, uint64_t data, * The flash address is provided by the SPI command/address cy= cles, * the MMIO addr parameter is ignored. */ - return aspeed_smc_flash_write(&s->flashes[cs], 0, data, size); + return aspeed_smc_flash_write(&s->flashes[cs], 0, data, size, + attrs); } aspeed_smc_error("Invalid data fifo offset %" HWADDR_PRIx, addr <<= 2); + return MEMTX_ERROR; } else { qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\= n", __func__, addr); - return; } + return MEMTX_OK; } =20 static const MemoryRegionOps aspeed_smc_ops =3D { - .read =3D aspeed_smc_read, - .write =3D aspeed_smc_write, + .read_with_attrs =3D aspeed_smc_read, + .write_with_attrs =3D aspeed_smc_write, .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 @@ -2073,8 +2083,8 @@ static const uint32_t aspeed_2700_fmc_resets[ASPEED_S= MC_R_MAX] =3D { }; =20 static const MemoryRegionOps aspeed_2700_smc_flash_ops =3D { - .read =3D aspeed_smc_flash_read, - .write =3D aspeed_smc_flash_write, + .read_with_attrs =3D aspeed_smc_flash_read, + .write_with_attrs =3D aspeed_smc_flash_write, .endianness =3D DEVICE_LITTLE_ENDIAN, .valid =3D { .min_access_size =3D 1, --=20 2.53.0