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[103.95.112.190]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35bd24f1b9csm2283060a91.0.2026.03.21.07.46.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Mar 2026 07:46:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1774104390; x=1774709190; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4FxZI4z3rOz6H+RHO7jTyWTYOkyCV4lSQuIwbzBbor8=; b=eDGENyMYpAqFuouKlhWHoEt5pz1KFOsWG3JANPzFON6fXdYupP6s8EUUUTPi4lirUN M0jCDmI6+d4M3etf7CEvXdxmzZ7IVcGta+5iN6VA12SeXQ95Y9KgYstSEAfOdN1rOUKF XhPvw0JpcD1GBTLZ663MIurC8uvlMXd6Up2SeXwaQFAt3ar8riE+4S8qhTqhRCxxTUSt Vv0oWPMvLCjZIGSamjj/i5S28nFciOQ0kztDrFeEk+c2maBon9bApn9e6s6+J0EkAQt5 +gygNu9a25E9MTrdod7k8irwv68tCfSe909lg7UAj4nSaK6hzI+8AP+dcZcbdhK7mxq7 YMyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774104390; x=1774709190; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=4FxZI4z3rOz6H+RHO7jTyWTYOkyCV4lSQuIwbzBbor8=; b=a88WNYHJKxUWI9N9pveARTjvJUU0oAdVuiMZicDqIpH37eJvaqfmi8L04EYmkbpsuH C/g3/gbq6oaBZXHK3tM1RWZqyl+P3xXWbBE/QAOyIqIEw/BZ8v7Gko/PsNwDvP9/tCKU 4K5758A/GYOXEHeEfKqkWK27aTTRRUniM7WwJ1x5GaXQdvB8LjLt+lF7XFFHlFon+ZGE 4h/ObtOr9bRwzwRPDhP9GvJZsfradwbY362TX0W/B7iXbwVK3SWTtLz+MzQlhLPx/kah 6NMA7iWYd+byFf7vuw5ebS4wR5tMfPWCARbmNW5duK+KAAuJTqi5wcX2QlxDCvfcfADG UU4w== X-Forwarded-Encrypted: i=1; AJvYcCXiLBUNQBrrnWj26zSe+HpFd/dVdl0MDcz0ZigP7ZW+FpPLz/p3VJOx1I4E7C2Vm6p+1cshNIbMABRS@nongnu.org X-Gm-Message-State: AOJu0Yx1G+3QS7G2Hof4Hv5gYioFmkY9vMtXyAlE1LmLfSNLnsAcyL45 Faq9FmxKj555p2gAYbV/uq1y5reSAYIPCOostjn1pJ7JBPgDqRWf6mIF X-Gm-Gg: ATEYQzyZjPKvmFcn5EqHY+YMacDBhitKjBe8dDjA+xwmvUJghPt0glT3nqQqb/qpUMd taAgUzK/S8cFpNA6lxsc3L8zrUxHDGVtIzyWmQODqoZGb7BDF22n1zznEDLolHAK6mAmJLyCgO6 CVwnA1XDPTjSLIJ+uSVuX5z8yciGqAhPdpbJBw++RVwktZCLlcDcDe3KHU/cV8wkcb90eIcPC+P Pg+lUZ5KRy3f00Ht0YJUP7sefvoIBfS2jzhFxrH/bGJBsXs55oUp3AmLRREcWWN++gBJVeCUoK5 qY8VYHHmwzQHFmVYhleB0SfZu+XonqEhpILbK0YgOwLN2PSNqzFp43TBwZkAC9hIGZcbB70kZ9j VX8KMYYek/toX0BFUc2kErtngFmA/EB5CWhQISKBbIcMh9AiSC3BYWq625xQpWljU5hJ9Js/Wox ZKiZlPDik1BiRAyVU/3/W5drfN0wxMnw3Q7zf7efBtABtZj3iUcccARZJzjWgoAdcbBEWB X-Received: by 2002:a17:90b:3d48:b0:359:fecd:1cd3 with SMTP id 98e67ed59e1d1-35bd2d1cf08mr5074721a91.23.1774104390319; Sat, 21 Mar 2026 07:46:30 -0700 (PDT) From: Nicholas Piggin To: qemu-riscv@nongnu.org Cc: Nicholas Piggin , Laurent Vivier , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-devel@nongnu.org, Joel Stanley Subject: [PATCH v3 3/3] tests/tcg: Add riscv test for interrupted vector ops Date: Sun, 22 Mar 2026 00:45:54 +1000 Message-ID: <20260321144554.606417-4-npiggin@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260321144554.606417-1-npiggin@gmail.com> References: <20260321144554.606417-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=npiggin@gmail.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1774104443199158500 Content-Type: text/plain; charset="utf-8" riscv vector instructions can be interrupted with a trap, and partial completion is recorded in the vstart register. Some causes are implementation dependent, for example an asynchronous interrupt (which I don't think TCG allows). Others are architectural, typically memory access faults on vector load/store instructions. Add some TCG tests for interrupting vector load instructions and resuming partially completed ones. This would have caught a recent (now reverted) regression in vector stride load implementation, commit 28c12c1f2f50d ("Generate strided vector loads/stores with tcg nodes.") Signed-off-by: Nicholas Piggin --- tests/tcg/riscv64/Makefile.target | 11 + tests/tcg/riscv64/test-interrupted-v.c | 329 +++++++++++++++++++++++++ 2 files changed, 340 insertions(+) create mode 100644 tests/tcg/riscv64/test-interrupted-v.c diff --git a/tests/tcg/riscv64/Makefile.target b/tests/tcg/riscv64/Makefile= .target index 19a49b6467..b2b2325843 100644 --- a/tests/tcg/riscv64/Makefile.target +++ b/tests/tcg/riscv64/Makefile.target @@ -1,6 +1,10 @@ # -*- Mode: makefile -*- # RISC-V specific tweaks =20 +# Not all environments have compilers with vector intrinsics yet. +HAVE_RISCV_VECTOR_INTRINSICS :=3D $(shell echo '#ifndef __riscv_v_intrinsi= c\n#error\n#endif' | \ + $(CC) -march=3Drv64gcv -E -x c - >/dev/n= ull 2>&1 && echo y) + VPATH +=3D $(SRC_PATH)/tests/tcg/riscv64 TESTS +=3D test-div TESTS +=3D noexec @@ -23,3 +27,10 @@ run-test-fcvtmod: QEMU_OPTS +=3D -cpu rv64,d=3Dtrue,zfa= =3Dtrue TESTS +=3D test-vstart-overflow test-vstart-overflow: CFLAGS +=3D -march=3Drv64gcv run-test-vstart-overflow: QEMU_OPTS +=3D -cpu rv64,v=3Don + +ifeq ($(HAVE_RISCV_VECTOR_INTRINSICS),y) +# Test for interrupted vector instructions +TESTS +=3D test-interrupted-v +test-interrupted-v: CFLAGS +=3D -march=3Drv64gcv +run-test-interrupted-v: QEMU_OPTS +=3D -cpu rv64,v=3Don +endif diff --git a/tests/tcg/riscv64/test-interrupted-v.c b/tests/tcg/riscv64/tes= t-interrupted-v.c new file mode 100644 index 0000000000..3d0d21b49b --- /dev/null +++ b/tests/tcg/riscv64/test-interrupted-v.c @@ -0,0 +1,329 @@ +/* + * Test for interrupted vector operations. + * + * Some vector instructions can be interrupted partially complete, vstart = will + * be set to where the operation has progressed to, and the instruction ca= n be + * re-executed with vstart !=3D 0. It is implementation dependent as to wh= at + * instructions can be interrupted and what vstart values are permitted wh= en + * executing them. Vector memory operations can typically be interrupted + * (as they can take page faults), so these are easy to test. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static unsigned long page_size; + +static volatile int nr_segv; +static volatile unsigned long fault_start, fault_end; +static volatile bool fault_write; + +/* + * Careful: qemu-user does not save/restore vector state in + * signals yet, so any library or compiler autovec code will + * corrupt our test. + * + * Do only minimal work in the signal handler. + */ +static void SEGV_handler(int signo, siginfo_t *info, void *context) +{ + unsigned long page =3D (unsigned long)info->si_addr & + ~(unsigned long)(page_size - 1); + + assert((unsigned long)info->si_addr >=3D fault_start); + assert((unsigned long)info->si_addr < fault_end); + if (fault_write) { + mprotect((void *)page, page_size, PROT_READ | PROT_WRITE); + } else { + mprotect((void *)page, page_size, PROT_READ); + } + nr_segv++; +} + +/* Use noinline to make generated code easier to inspect */ +static __attribute__((noinline)) +uint8_t unit_load(uint8_t *mem, size_t nr, bool ff) +{ + size_t vl; + vuint8m1_t vec, redvec, sum; + + vl =3D __riscv_vsetvl_e8m1(nr); + if (ff) { + vec =3D __riscv_vle8ff_v_u8m1(mem, &vl, vl); + } else { + vec =3D __riscv_vle8_v_u8m1(mem, vl); + } + redvec =3D __riscv_vmv_v_x_u8m1(0, vl); + sum =3D __riscv_vredsum_vs_u8m1_u8m1(vec, redvec, vl); + return __riscv_vmv_x_s_u8m1_u8(sum); +} + +static __attribute__((noinline)) +uint8_t seg2_load(uint8_t *mem, size_t nr, bool ff) +{ + size_t vl; + vuint8m1x2_t segvec; + vuint8m1_t vec, redvec, sum; + + vl =3D __riscv_vsetvl_e8m1(nr); + if (ff) { + segvec =3D __riscv_vlseg2e8ff_v_u8m1x2(mem, &vl, vl); + } else { + segvec =3D __riscv_vlseg2e8_v_u8m1x2(mem, vl); + } + vec =3D __riscv_vadd_vv_u8m1(__riscv_vget_v_u8m1x2_u8m1(segvec, 0), + __riscv_vget_v_u8m1x2_u8m1(segvec, 1), vl); + redvec =3D __riscv_vmv_v_x_u8m1(0, vl); + sum =3D __riscv_vredsum_vs_u8m1_u8m1(vec, redvec, vl); + return __riscv_vmv_x_s_u8m1_u8(sum); +} + +static __attribute__((noinline)) +uint8_t strided_load(uint8_t *mem, size_t nr, size_t stride) +{ + size_t vl; + vuint8m1_t vec, redvec, sum; + + vl =3D __riscv_vsetvl_e8m1(nr); + vec =3D __riscv_vlse8_v_u8m1(mem, stride, vl); + redvec =3D __riscv_vmv_v_x_u8m1(0, vl); + sum =3D __riscv_vredsum_vs_u8m1_u8m1(vec, redvec, vl); + return __riscv_vmv_x_s_u8m1_u8(sum); +} + +static __attribute__((noinline)) +uint8_t indexed_load(uint8_t *mem, size_t nr, uint32_t *indices) +{ + size_t vl; + vuint32m4_t idx; + vuint8m1_t vec, redvec, sum; + + vl =3D __riscv_vsetvl_e8m1(nr); + idx =3D __riscv_vle32_v_u32m4(indices, vl); + vec =3D __riscv_vloxei32_v_u8m1(mem, idx, vl); + redvec =3D __riscv_vmv_v_x_u8m1(0, vl); + sum =3D __riscv_vredsum_vs_u8m1_u8m1(vec, redvec, vl); + return __riscv_vmv_x_s_u8m1_u8(sum); +} + +/* New store functions */ +static __attribute__((noinline)) +void unit_store(uint8_t *mem, size_t nr, vuint8m1_t vec) +{ + size_t vl; + + vl =3D __riscv_vsetvl_e8m1(nr); + __riscv_vse8_v_u8m1(mem, vec, vl); +} + +static __attribute__((noinline)) +void seg2_store(uint8_t *mem, size_t nr, vuint8m1x2_t segvec) +{ + size_t vl; + + vl =3D __riscv_vsetvl_e8m1(nr); + __riscv_vsseg2e8_v_u8m1x2(mem, segvec, vl); +} + +static __attribute__((noinline)) +void strided_store(uint8_t *mem, size_t nr, size_t stride, vuint8m1_t vec) +{ + size_t vl; + + vl =3D __riscv_vsetvl_e8m1(nr); + __riscv_vsse8_v_u8m1(mem, stride, vec, vl); +} + +static __attribute__((noinline)) +void indexed_store(uint8_t *mem, size_t nr, uint32_t *indices, vuint8m1_t = vec) +{ + size_t vl; + vuint32m4_t idx; + + vl =3D __riscv_vsetvl_e8m1(nr); + idx =3D __riscv_vle32_v_u32m4(indices, vl); + __riscv_vsoxei32_v_u8m1(mem, idx, vec, vl); +} + +/* Use e8 elements, 128-bit vectors */ +#define NR_ELEMS 16 + +static int run_interrupted_v_tests(void) +{ + struct sigaction act =3D { 0 }; + uint8_t *mem; + uint32_t indices[NR_ELEMS]; + int i; + + page_size =3D sysconf(_SC_PAGESIZE); + + act.sa_flags =3D SA_SIGINFO; + act.sa_sigaction =3D &SEGV_handler; + if (sigaction(SIGSEGV, &act, NULL) =3D=3D -1) { + perror("sigaction"); + exit(EXIT_FAILURE); + } + + mem =3D mmap(NULL, NR_ELEMS * page_size, PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + assert(mem !=3D MAP_FAILED); + madvise(mem, NR_ELEMS * page_size, MADV_NOHUGEPAGE); + + /*** Load tests ***/ + fault_write =3D false; + + /* Unit-stride tests load memory crossing a page boundary */ + memset(mem, 0, NR_ELEMS * page_size); + for (i =3D 0; i < NR_ELEMS; i++) { + mem[page_size - NR_ELEMS + i] =3D 3; + } + for (i =3D 0; i < NR_ELEMS; i++) { + mem[page_size + i] =3D 5; + } + + nr_segv =3D 0; + fault_start =3D (unsigned long)&mem[page_size - (NR_ELEMS / 2)]; + fault_end =3D fault_start + NR_ELEMS; + mprotect(mem, page_size * 2, PROT_NONE); + assert(unit_load(&mem[page_size - (NR_ELEMS / 2)], NR_ELEMS, false) + =3D=3D 8 * NR_ELEMS / 2); + assert(nr_segv =3D=3D 2); + + nr_segv =3D 0; + fault_start =3D (unsigned long)&mem[page_size - NR_ELEMS]; + fault_end =3D fault_start + NR_ELEMS * 2; + mprotect(mem, page_size * 2, PROT_NONE); + assert(seg2_load(&mem[page_size - NR_ELEMS], NR_ELEMS, false) + =3D=3D 8 * NR_ELEMS); + assert(nr_segv =3D=3D 2); + + nr_segv =3D 0; + fault_start =3D (unsigned long)&mem[page_size - (NR_ELEMS / 2)]; + fault_end =3D fault_start + (NR_ELEMS / 2); + mprotect(mem, page_size * 2, PROT_NONE); + assert(unit_load(&mem[page_size - (NR_ELEMS / 2)], NR_ELEMS, true) + =3D=3D 3 * NR_ELEMS / 2); + assert(nr_segv =3D=3D 1); /* fault-first does not fault the second pag= e */ + + nr_segv =3D 0; + fault_start =3D (unsigned long)&mem[page_size - NR_ELEMS]; + fault_end =3D fault_start + NR_ELEMS; + mprotect(mem, page_size * 2, PROT_NONE); + assert(seg2_load(&mem[page_size - NR_ELEMS], NR_ELEMS * 2, true) + =3D=3D 3 * NR_ELEMS); + assert(nr_segv =3D=3D 1); /* fault-first does not fault the second pag= e */ + + /* Following tests load one element from first byte of each page */ + mprotect(mem, page_size * 2, PROT_READ | PROT_WRITE); + memset(mem, 0, NR_ELEMS * page_size); + for (i =3D 0; i < NR_ELEMS; i++) { + mem[i * page_size] =3D 3; + indices[i] =3D i * page_size; + } + + nr_segv =3D 0; + fault_start =3D (unsigned long)mem; + fault_end =3D fault_start + NR_ELEMS * page_size; + mprotect(mem, NR_ELEMS * page_size, PROT_NONE); + assert(strided_load(mem, NR_ELEMS, page_size) =3D=3D 3 * NR_ELEMS); + assert(nr_segv =3D=3D NR_ELEMS); + + nr_segv =3D 0; + fault_start =3D (unsigned long)mem; + fault_end =3D fault_start + NR_ELEMS * page_size; + mprotect(mem, NR_ELEMS * page_size, PROT_NONE); + assert(indexed_load(mem, NR_ELEMS, indices) =3D=3D 3 * NR_ELEMS); + assert(nr_segv =3D=3D NR_ELEMS); + + /*** Store tests ***/ + fault_write =3D true; + + uint8_t store_data[NR_ELEMS]; + uint8_t store_data_seg0[NR_ELEMS]; + uint8_t store_data_seg1[NR_ELEMS]; + vuint8m1_t vec; + vuint8m1x2_t segvec; + size_t vl =3D __riscv_vsetvl_e8m1(NR_ELEMS); + + /* Create some data to store */ + for (i =3D 0; i < NR_ELEMS; i++) { + store_data[i] =3D i * 3; + store_data_seg0[i] =3D i * 5; + store_data_seg1[i] =3D i * 7; + } + vec =3D __riscv_vle8_v_u8m1(store_data, vl); + segvec =3D __riscv_vcreate_v_u8m1x2( + __riscv_vle8_v_u8m1(store_data_seg0, vl), + __riscv_vle8_v_u8m1(store_data_seg1, vl)); + + /* Unit-stride store test crossing a page boundary */ + mprotect(mem, page_size * 2, PROT_READ | PROT_WRITE); + memset(mem, 0, page_size * 2); + nr_segv =3D 0; + fault_start =3D (unsigned long)&mem[page_size - (NR_ELEMS / 2)]; + fault_end =3D fault_start + NR_ELEMS; + mprotect(mem, page_size * 2, PROT_NONE); + unit_store(&mem[page_size - (NR_ELEMS / 2)], NR_ELEMS, vec); + assert(nr_segv =3D=3D 2); + for (i =3D 0; i < NR_ELEMS; i++) { + assert(mem[page_size - (NR_ELEMS / 2) + i] =3D=3D store_data[i]); + } + + /* Segmented store test crossing a page boundary */ + mprotect(mem, page_size * 2, PROT_READ | PROT_WRITE); + memset(mem, 0, page_size * 2); + nr_segv =3D 0; + fault_start =3D (unsigned long)&mem[page_size - NR_ELEMS]; + fault_end =3D fault_start + NR_ELEMS * 2; + mprotect(mem, page_size * 2, PROT_NONE); + seg2_store(&mem[page_size - NR_ELEMS], NR_ELEMS, segvec); + assert(nr_segv =3D=3D 2); + for (i =3D 0; i < NR_ELEMS; i++) { + assert(mem[page_size - NR_ELEMS + i * 2] =3D=3D store_data_seg0[i]= ); + assert(mem[page_size - NR_ELEMS + i * 2 + 1] =3D=3D store_data_seg= 1[i]); + } + + /* Strided store test to one element on each page */ + mprotect(mem, NR_ELEMS * page_size, PROT_READ | PROT_WRITE); + memset(mem, 0, NR_ELEMS * page_size); + nr_segv =3D 0; + fault_start =3D (unsigned long)mem; + fault_end =3D fault_start + NR_ELEMS * page_size; + mprotect(mem, NR_ELEMS * page_size, PROT_NONE); + strided_store(mem, NR_ELEMS, page_size, vec); + assert(nr_segv =3D=3D NR_ELEMS); + for (i =3D 0; i < NR_ELEMS; i++) { + assert(mem[i * page_size] =3D=3D store_data[i]); + } + + /* Indexed store test to one element on each page */ + mprotect(mem, NR_ELEMS * page_size, PROT_READ | PROT_WRITE); + memset(mem, 0, NR_ELEMS * page_size); + nr_segv =3D 0; + fault_start =3D (unsigned long)mem; + fault_end =3D fault_start + NR_ELEMS * page_size; + mprotect(mem, NR_ELEMS * page_size, PROT_NONE); + indexed_store(mem, NR_ELEMS, indices, vec); + assert(nr_segv =3D=3D NR_ELEMS); + for (i =3D 0; i < NR_ELEMS; i++) { + assert(mem[indices[i]] =3D=3D store_data[i]); + } + + munmap(mem, NR_ELEMS * page_size); + + return 0; +} + +int main(void) +{ + return run_interrupted_v_tests(); +} --=20 2.51.0