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[103.95.112.190]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82b040debf9sm4764875b3a.47.2026.03.21.07.14.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Mar 2026 07:14:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1774102450; x=1774707250; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jiwdrJNDFg1OgiJNKsCj9IdOduRF8mocY80E3W+1o2E=; b=ZlA+5zRG1EsyloF+5YCtSw90d0QUlDkRwvugG53s7kj6Uzpbmm/Y+WiD9S/9EpcEan OIkaoKNOCE6gLAiccyb94MTTo8PlIWQr4QiJXe0AoTgi+kNA5h3dl4IDOJua7FSIYDFz mExaH/ints8wQhIJ447ev6APAG2g8uU52QoFsFMzobQRg87MXOzekrso2Qw45Z2t+Q/Y SNondEm8jLiDqYUPbFZuZhRAIdaPdTlPF+t4Ab5Ke/auU6OYIhVj0drgeYdaZ8kH0ma1 IlShn+66Osmk/yfX/1G2ldW/SE5xCkOc24nG7bxU20Odtce6bVGWrzUsdmbjft4oHfVL AQyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774102450; x=1774707250; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=jiwdrJNDFg1OgiJNKsCj9IdOduRF8mocY80E3W+1o2E=; b=A3U/qZnUXLkEaGawVdGwxXEfDze9EezcORDBg/FlskKguLUocTPvYJwXqDdXSDk+3Z WLkmjRfmRiJoNZQtKZxVlMSPXJOBp+5aMLst/55xIIDPYx2HDwXJsJt2I6jTHzlGmg7f f1CdOXT2Vvgv/RjwXlfWJpe5teZi/EcKA5sOPNhwX/qKSMiM3f0lkQbY2LYVi03GjRUj 8v+9J1i0SmAneFb6ZjqTNJp00ym7rZf9Pz70+1mL8PAECLDy8GaMmS2UN86Y6o4WLRc5 fDYhi7VJAbqoVXr/m6RcdiswUZs3lvWSpQDdLnTVTfRbVLyoUr0pTsZwVCvTXCjc42Ip O2Bw== X-Forwarded-Encrypted: i=1; AJvYcCU5yJ7aCw9beOspt37aNMmcqY5zWm/2IWmQn3vxd03qpeev/+GkOLG+HpQ1UioNieTpq4nMnjUxEOQI@nongnu.org X-Gm-Message-State: AOJu0YwTsjU27s4BmmDDhgpQM2+wWGx3+D1J4+brZMesjgNP+eYzRiTO 22JonBJB/ZVlsioDnJ5JkC1lRh3DD7WMFT6MV13u7dZZPF6by6m7kv9O X-Gm-Gg: ATEYQzzu5UzZYQDQcoknyXJDNoPP58Bdk165gg1VwBJbLcvrBqTqfoFIqaSLoub5LE7 pnxynRr3o6hTxiCsVglKIH0rWPNd6XGtgLivoFz3uFmQpurzvMAHuZbd8L74tBD+LzSSDrwBoYC QUC2s79+9PQ/LN02KDe05QZ8nDP8FOf+1cGaVMkOZSXhRWsjnDpz5YOTCiNUbBCrecw2IiVLR8H Z/kr+apS7RD3PhMegB37JvGYh5jk38bGQzXTLA2F+kELg3gitsA7c9+IFuOTwCzuNYG13weai3L xraquA+CuRvnAy4bVbeFVGF9/tjZwgOPk5/Ngacckz7+XQgVrQZpDZ2U5grGLEhIX+LiOF25DaG kPeZ09Mpsvdh+Unzn5TtJl6hAjLW07brb5kVjimOUao9hk0ZR+ZcvZ4SQtcHvF357gv3Nm4jSfe aeNcNV+K0SxjOybRs1YZFRovmOCXRhF/cKLO04164pA/SGcVlJVYIbxfF7QU/mH5A5d8kD X-Received: by 2002:aa7:9e41:0:b0:82b:4a85:3e2f with SMTP id d2e1a72fcca58-82b4a854131mr3350503b3a.41.1774102449552; Sat, 21 Mar 2026 07:14:09 -0700 (PDT) From: Nicholas Piggin To: qemu-riscv@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Laurent Vivier , Pierrick Bouvier , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Richard Henderson , Joel Stanley Subject: [PATCH v3 1/5] tests/tcg/riscv64: Add a user signal handling test Date: Sun, 22 Mar 2026 00:13:39 +1000 Message-ID: <20260321141345.599105-2-npiggin@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260321141345.599105-1-npiggin@gmail.com> References: <20260321141345.599105-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_GMAIL_RCVD=1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1774102543891158500 Content-Type: text/plain; charset="utf-8" Add a few basic signal handling tests for user emulation. Signed-off-by: Nicholas Piggin --- tests/tcg/riscv64/Makefile.target | 5 + tests/tcg/riscv64/test-signal-handling.c | 303 +++++++++++++++++++++++ 2 files changed, 308 insertions(+) create mode 100644 tests/tcg/riscv64/test-signal-handling.c diff --git a/tests/tcg/riscv64/Makefile.target b/tests/tcg/riscv64/Makefile= .target index 4da5b9a3b3..f318891396 100644 --- a/tests/tcg/riscv64/Makefile.target +++ b/tests/tcg/riscv64/Makefile.target @@ -18,3 +18,8 @@ TESTS +=3D test-fcvtmod test-fcvtmod: CFLAGS +=3D -march=3Drv64imafdc test-fcvtmod: LDFLAGS +=3D -static run-test-fcvtmod: QEMU_OPTS +=3D -cpu rv64,d=3Dtrue,zfa=3Dtrue + +# Test signal handling. +TESTS +=3D test-signal-handling +test-signal-handling: CFLAGS +=3D -march=3Drv64gc +run-test-signal-handling: QEMU_OPTS +=3D -cpu rv64 diff --git a/tests/tcg/riscv64/test-signal-handling.c b/tests/tcg/riscv64/t= est-signal-handling.c new file mode 100644 index 0000000000..c202503382 --- /dev/null +++ b/tests/tcg/riscv64/test-signal-handling.c @@ -0,0 +1,303 @@ +/* + * Test for linux-user signal handling. + * + * This ensures that integer and fp register values are + * saved as expected in the sigcontext, created by a SIGILL. + * + * TODO: Register restore is not explicitly verified, except + * for advancing pc, and the restoring of registers that were + * clobbered by the compiler in the signal handler. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * This horrible hack seems to be required when including + * signal.h and asm/sigcontext.h, to prevent sigcontext + * redefinition by bits/sigcontext.h :( + * + * bits/sigcontext.h does not have the extended state or + * RISCV_V_MAGIC, etc. It could have just been introduced + * as a new type. + */ +#define _BITS_SIGCONTEXT_H 1 +#include + +static uint64_t *initial_gvalues; +static uint64_t *final_gvalues; +static uint64_t *signal_gvalues; +static double *initial_fvalues; +static double *final_fvalues; +static double *signal_fvalues; + +extern unsigned long unimp_addr[]; + +static bool got_signal =3D false; + +#define BT_BUF_SIZE 100 + +static void *find_callchain_root(void) +{ + int nptrs; + void *buffer[BT_BUF_SIZE]; + + nptrs =3D backtrace(buffer, BT_BUF_SIZE); + + return buffer[nptrs - 1]; +} + +static void *callchain_root; + +static void ILL_handler(int signo, siginfo_t *info, void *context) +{ + ucontext_t *uc =3D context; + struct sigcontext *sc =3D (struct sigcontext *)&uc->uc_mcontext; + + got_signal =3D true; + + assert(unimp_addr =3D=3D info->si_addr); + assert(sc->sc_regs.pc =3D=3D (unsigned long)info->si_addr); + + /* Ensure stack unwind through the signal frame is not broken */ + assert(callchain_root =3D=3D find_callchain_root()); + + for (int i =3D 0; i < 31; i++) { + ((uint64_t *)signal_gvalues)[i] =3D ((unsigned long *)&sc->sc_regs= .ra)[i]; + } + + for (int i =3D 0; i < 32; i++) { + ((uint64_t *)signal_fvalues)[i] =3D sc->sc_fpregs.d.f[i]; + } + /* Test sc->sc_fpregs.d.fcsr ? */ + + sc->sc_regs.pc +=3D 4; +} + +static void init_test(void) +{ + int i; + + callchain_root =3D find_callchain_root(); + + initial_gvalues =3D malloc(8 * 31); + memset(initial_gvalues, 0, 8 * 31); + final_gvalues =3D malloc(8 * 31); + memset(final_gvalues, 0, 8 * 31); + signal_gvalues =3D malloc(8 * 31); + memset(signal_gvalues, 0, 8 * 31); + + initial_fvalues =3D malloc(8 * 32); + memset(initial_fvalues, 0, 8 * 32); + for (i =3D 0; i < 32 ; i++) { + initial_fvalues[i] =3D 3.142 * (i + 1); + } + final_fvalues =3D malloc(8 * 32); + memset(final_fvalues, 0, 8 * 32); + signal_fvalues =3D malloc(8 * 32); + memset(signal_fvalues, 0, 8 * 32); +} + +static void run_test(void) +{ + asm volatile( + /* Save initial values from gp registers */ + "mv t0, %[initial_gvalues]\n\t" + "sd x1, 0x0(t0)\n\t" + "sd x2, 0x8(t0)\n\t" + "sd x3, 0x10(t0)\n\t" + "sd x4, 0x18(t0)\n\t" + "sd x5, 0x20(t0)\n\t" + "sd x6, 0x28(t0)\n\t" + "sd x7, 0x30(t0)\n\t" + "sd x8, 0x38(t0)\n\t" + "sd x9, 0x40(t0)\n\t" + "sd x10, 0x48(t0)\n\t" + "sd x11, 0x50(t0)\n\t" + "sd x12, 0x58(t0)\n\t" + "sd x13, 0x60(t0)\n\t" + "sd x14, 0x68(t0)\n\t" + "sd x15, 0x70(t0)\n\t" + "sd x16, 0x78(t0)\n\t" + "sd x17, 0x80(t0)\n\t" + "sd x18, 0x88(t0)\n\t" + "sd x19, 0x90(t0)\n\t" + "sd x20, 0x98(t0)\n\t" + "sd x21, 0xa0(t0)\n\t" + "sd x22, 0xa8(t0)\n\t" + "sd x23, 0xb0(t0)\n\t" + "sd x24, 0xb8(t0)\n\t" + "sd x25, 0xc0(t0)\n\t" + "sd x26, 0xc8(t0)\n\t" + "sd x27, 0xd0(t0)\n\t" + "sd x28, 0xd8(t0)\n\t" + "sd x29, 0xe0(t0)\n\t" + "sd x30, 0xe8(t0)\n\t" + "sd x31, 0xf0(t0)\n\t" + /* Load initial values into float registers */ + "mv t0, %[initial_fvalues]\n\t" + "fld f0, 0x0(t0)\n\t" + "fld f1, 0x8(t0)\n\t" + "fld f2, 0x10(t0)\n\t" + "fld f3, 0x18(t0)\n\t" + "fld f4, 0x20(t0)\n\t" + "fld f5, 0x28(t0)\n\t" + "fld f6, 0x30(t0)\n\t" + "fld f7, 0x38(t0)\n\t" + "fld f8, 0x40(t0)\n\t" + "fld f9, 0x48(t0)\n\t" + "fld f10, 0x50(t0)\n\t" + "fld f11, 0x58(t0)\n\t" + "fld f12, 0x60(t0)\n\t" + "fld f13, 0x68(t0)\n\t" + "fld f14, 0x70(t0)\n\t" + "fld f15, 0x78(t0)\n\t" + "fld f16, 0x80(t0)\n\t" + "fld f17, 0x88(t0)\n\t" + "fld f18, 0x90(t0)\n\t" + "fld f19, 0x98(t0)\n\t" + "fld f20, 0xa0(t0)\n\t" + "fld f21, 0xa8(t0)\n\t" + "fld f22, 0xb0(t0)\n\t" + "fld f23, 0xb8(t0)\n\t" + "fld f24, 0xc0(t0)\n\t" + "fld f25, 0xc8(t0)\n\t" + "fld f26, 0xd0(t0)\n\t" + "fld f27, 0xd8(t0)\n\t" + "fld f28, 0xe0(t0)\n\t" + "fld f29, 0xe8(t0)\n\t" + "fld f30, 0xf0(t0)\n\t" + "fld f31, 0xf8(t0)\n\t" + /* Trigger the SIGILL */ +".global unimp_addr\n\t" +"unimp_addr:\n\t" + "unimp\n\t" + "nop\n\t" + /* Save final values from gp registers */ + "mv t0, %[final_gvalues]\n\t" + "sd x1, 0x0(t0)\n\t" + "sd x2, 0x8(t0)\n\t" + "sd x3, 0x10(t0)\n\t" + "sd x4, 0x18(t0)\n\t" + "sd x5, 0x20(t0)\n\t" + "sd x6, 0x28(t0)\n\t" + "sd x7, 0x30(t0)\n\t" + "sd x8, 0x38(t0)\n\t" + "sd x9, 0x40(t0)\n\t" + "sd x10, 0x48(t0)\n\t" + "sd x11, 0x50(t0)\n\t" + "sd x12, 0x58(t0)\n\t" + "sd x13, 0x60(t0)\n\t" + "sd x14, 0x68(t0)\n\t" + "sd x15, 0x70(t0)\n\t" + "sd x16, 0x78(t0)\n\t" + "sd x17, 0x80(t0)\n\t" + "sd x18, 0x88(t0)\n\t" + "sd x19, 0x90(t0)\n\t" + "sd x20, 0x98(t0)\n\t" + "sd x21, 0xa0(t0)\n\t" + "sd x22, 0xa8(t0)\n\t" + "sd x23, 0xb0(t0)\n\t" + "sd x24, 0xb8(t0)\n\t" + "sd x25, 0xc0(t0)\n\t" + "sd x26, 0xc8(t0)\n\t" + "sd x27, 0xd0(t0)\n\t" + "sd x28, 0xd8(t0)\n\t" + "sd x29, 0xe0(t0)\n\t" + "sd x30, 0xe8(t0)\n\t" + "sd x31, 0xf0(t0)\n\t" + /* Save final values from float registers */ + "mv t0, %[final_fvalues]\n\t" + "fsd f0, 0x0(t0)\n\t" + "fsd f1, 0x8(t0)\n\t" + "fsd f2, 0x10(t0)\n\t" + "fsd f3, 0x18(t0)\n\t" + "fsd f4, 0x20(t0)\n\t" + "fsd f5, 0x28(t0)\n\t" + "fsd f6, 0x30(t0)\n\t" + "fsd f7, 0x38(t0)\n\t" + "fsd f8, 0x40(t0)\n\t" + "fsd f9, 0x48(t0)\n\t" + "fsd f10, 0x50(t0)\n\t" + "fsd f11, 0x58(t0)\n\t" + "fsd f12, 0x60(t0)\n\t" + "fsd f13, 0x68(t0)\n\t" + "fsd f14, 0x70(t0)\n\t" + "fsd f15, 0x78(t0)\n\t" + "fsd f16, 0x80(t0)\n\t" + "fsd f17, 0x88(t0)\n\t" + "fsd f18, 0x90(t0)\n\t" + "fsd f19, 0x98(t0)\n\t" + "fsd f20, 0xa0(t0)\n\t" + "fsd f21, 0xa8(t0)\n\t" + "fsd f22, 0xb0(t0)\n\t" + "fsd f23, 0xb8(t0)\n\t" + "fsd f24, 0xc0(t0)\n\t" + "fsd f25, 0xc8(t0)\n\t" + "fsd f26, 0xd0(t0)\n\t" + "fsd f27, 0xd8(t0)\n\t" + "fsd f28, 0xe0(t0)\n\t" + "fsd f29, 0xe8(t0)\n\t" + "fsd f30, 0xf0(t0)\n\t" + "fsd f31, 0xf8(t0)\n\t" + : "=3Dm" (initial_gvalues), + "=3Dm" (final_gvalues), + "=3Dm" (final_fvalues) + : "m" (initial_fvalues), + [initial_gvalues] "r" (initial_gvalues), + [initial_fvalues] "r" (initial_fvalues), + [final_gvalues] "r" (final_gvalues), + [final_fvalues] "r" (final_fvalues) + : "t0", + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"); + + assert(got_signal); + + /* + * x4 / t0 is used in the asm so it has to be handled specially + * and is not a simple equality. + */ + assert(initial_gvalues[4] =3D=3D (unsigned long)initial_gvalues); + assert(signal_gvalues[4] =3D=3D (unsigned long)initial_fvalues); + assert(final_gvalues[4] =3D=3D (unsigned long)final_gvalues); + initial_gvalues[4] =3D final_gvalues[4] =3D signal_gvalues[4] =3D 0; + + /* + * Ensure registers match before, inside, and after signal + * handler. + */ + assert(!memcmp(initial_gvalues, final_gvalues, 8 * 31)); + assert(!memcmp(initial_gvalues, signal_gvalues, 8 * 31)); + assert(!memcmp(initial_fvalues, final_fvalues, 8 * 32)); + assert(!memcmp(initial_fvalues, signal_fvalues, 8 * 32)); +} + +int main(void) +{ + struct sigaction act =3D { 0 }; + + act.sa_flags =3D SA_SIGINFO; + act.sa_sigaction =3D &ILL_handler; + if (sigaction(SIGILL, &act, NULL) =3D=3D -1) { + perror("sigaction"); + exit(EXIT_FAILURE); + } + + init_test(); + + run_test(); +} --=20 2.51.0 From nobody Sun Mar 22 14:25:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Plumb through this error handling which will be used by the next change. Suggested-by: Richard Henderson Signed-off-by: Nicholas Piggin --- linux-user/riscv/signal.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c index 22b1b8149f..ece276f85f 100644 --- a/linux-user/riscv/signal.c +++ b/linux-user/riscv/signal.c @@ -145,7 +145,7 @@ badframe: force_sig(TARGET_SIGSEGV); } =20 -static void restore_sigcontext(CPURISCVState *env, struct target_sigcontex= t *sc) +static bool restore_sigcontext(CPURISCVState *env, struct target_sigcontex= t *sc) { int i; =20 @@ -161,9 +161,11 @@ static void restore_sigcontext(CPURISCVState *env, str= uct target_sigcontext *sc) uint32_t fcsr; __get_user(fcsr, &sc->fcsr); riscv_csr_write(env, CSR_FCSR, fcsr); + + return true; } =20 -static void restore_ucontext(CPURISCVState *env, struct target_ucontext *u= c) +static bool restore_ucontext(CPURISCVState *env, struct target_ucontext *u= c) { sigset_t blocked; target_sigset_t target_set; @@ -177,7 +179,7 @@ static void restore_ucontext(CPURISCVState *env, struct= target_ucontext *uc) target_to_host_sigset_internal(&blocked, &target_set); set_sigmask(&blocked); =20 - restore_sigcontext(env, &uc->uc_mcontext); + return restore_sigcontext(env, &uc->uc_mcontext); } =20 long do_rt_sigreturn(CPURISCVState *env) @@ -191,7 +193,10 @@ long do_rt_sigreturn(CPURISCVState *env) goto badframe; } =20 - restore_ucontext(env, &frame->uc); + if (!restore_ucontext(env, &frame->uc)) { + goto badframe; + } + target_restore_altstack(&frame->uc.uc_stack, env); =20 unlock_user_struct(frame, frame_addr, 0); --=20 2.51.0 From nobody Sun Mar 22 14:25:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1774102517; cv=none; d=zohomail.com; s=zohoarc; b=WqRA3tYKpTZ33NqJ6rtROu/s4MRpPAz4LDKHPB80vN0eJg21TdQBKPnnYAkSjolXE4GRSwng6b2kuLuLPKndz5ghOCC3JNy2ytEeAYYllQSwq/147e4do95zZ2K/yYWqH1zZi7jua7MfMEwrftpD3PTMZe1EK1fmtheuD8bxAzw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774102517; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=zqaGAnnpccfVW8ZFyBB14Gt89PnbcdQ0eaqs3g8GXfw=; b=fkncPp2YylbM0iLyKCsf5XgPNzbhaaZOg/yqnbJfeyLQ8j1lZj2lN9kgARwOHREET0a/eJWllR+eFuhJYgK44B8fXuGeFiEy2IxCHZGc7u/BXdNEvcS7hzmeA/ZRb+IkBxWOgtgNubUoQielWN/feQbCduELK03UxD+iWNmTkFM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1774102517641604.5030722044207; Sat, 21 Mar 2026 07:15:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w3x5w-0006Ri-2Z; Sat, 21 Mar 2026 10:14:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w3x5r-0006PK-Vd for qemu-devel@nongnu.org; Sat, 21 Mar 2026 10:14:24 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w3x5q-0003n7-AE for qemu-devel@nongnu.org; Sat, 21 Mar 2026 10:14:23 -0400 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-82735a41920so1184361b3a.2 for ; Sat, 21 Mar 2026 07:14:21 -0700 (PDT) Received: from lima-default (103.95.112.190.qld.leaptel.network. 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Update the linux-user signal handling to this new structure. Signed-off-by: Nicholas Piggin --- linux-user/riscv/signal.c | 93 +++++++++++++++++++++++++++---- linux-user/riscv/vdso-asmoffset.h | 4 +- 2 files changed, 85 insertions(+), 12 deletions(-) diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c index ece276f85f..e20b9ac177 100644 --- a/linux-user/riscv/signal.c +++ b/linux-user/riscv/signal.c @@ -31,14 +31,43 @@ =20 The code below is qemu re-implementation of arch/riscv/kernel/signal.c = */ =20 -struct target_sigcontext { +struct target_gp_state { abi_long pc; abi_long gpr[31]; /* x0 is not present, so all offsets must be -1 */ +}; + +struct target_fp_state { uint64_t fpr[32]; uint32_t fcsr; +}; + +/* The Magic number for signal context frame header. */ +#define END_MAGIC 0x0 + +/* The size of END signal context header. */ +#define END_HDR_SIZE 0x0 + +struct target_ctx_hdr { + uint32_t magic; + uint32_t size; +}; + +struct target_extra_ext_header { + uint32_t __padding[129] __attribute__((aligned(16))); + uint32_t reserved; + struct target_ctx_hdr hdr; +}; + +struct target_sigcontext { + struct target_gp_state sc_regs; + union { + struct target_fp_state sc_fpregs; + struct target_extra_ext_header sc_extdesc; + }; }; /* cf. riscv-linux:arch/riscv/include/uapi/asm/ptrace.h */ =20 -QEMU_BUILD_BUG_ON(offsetof(struct target_sigcontext, fpr) !=3D offsetof_fr= eg0); +QEMU_BUILD_BUG_ON(offsetof(struct target_sigcontext, sc_fpregs.fpr) !=3D + offsetof_freg0); =20 struct target_ucontext { abi_ulong uc_flags; @@ -79,19 +108,26 @@ static abi_ulong get_sigframe(struct target_sigaction = *ka, =20 static void setup_sigcontext(struct target_sigcontext *sc, CPURISCVState *= env) { + struct target_ctx_hdr *hdr; int i; =20 - __put_user(env->pc, &sc->pc); + __put_user(env->pc, &sc->sc_regs.pc); =20 for (i =3D 1; i < 32; i++) { - __put_user(env->gpr[i], &sc->gpr[i - 1]); + __put_user(env->gpr[i], &sc->sc_regs.gpr[i - 1]); } for (i =3D 0; i < 32; i++) { - __put_user(env->fpr[i], &sc->fpr[i]); + __put_user(env->fpr[i], &sc->sc_fpregs.fpr[i]); } =20 uint32_t fcsr =3D riscv_csr_read(env, CSR_FCSR); - __put_user(fcsr, &sc->fcsr); + __put_user(fcsr, &sc->sc_fpregs.fcsr); + + __put_user(0, &sc->sc_extdesc.reserved); + + hdr =3D &sc->sc_extdesc.hdr; + __put_user(END_MAGIC, &hdr->magic); + __put_user(END_HDR_SIZE, &hdr->size); } =20 static void setup_ucontext(struct target_ucontext *uc, @@ -147,21 +183,58 @@ badframe: =20 static bool restore_sigcontext(CPURISCVState *env, struct target_sigcontex= t *sc) { + struct target_ctx_hdr *hdr; + uint32_t rsv, magic, size; int i; =20 - __get_user(env->pc, &sc->pc); + __get_user(env->pc, &sc->sc_regs.pc); =20 for (i =3D 1; i < 32; ++i) { - __get_user(env->gpr[i], &sc->gpr[i - 1]); + __get_user(env->gpr[i], &sc->sc_regs.gpr[i - 1]); } for (i =3D 0; i < 32; ++i) { - __get_user(env->fpr[i], &sc->fpr[i]); + __get_user(env->fpr[i], &sc->sc_fpregs.fpr[i]); } =20 uint32_t fcsr; - __get_user(fcsr, &sc->fcsr); + __get_user(fcsr, &sc->sc_fpregs.fcsr); riscv_csr_write(env, CSR_FCSR, fcsr); =20 + hdr =3D &sc->sc_extdesc.hdr; + __get_user(rsv, &sc->sc_extdesc.reserved); + if (rsv !=3D 0) { + qemu_log_mask(LOG_GUEST_ERROR, "signal: sigcontext reserved field = is " + "non-zero\n"); + return false; + } + + __get_user(magic, &hdr->magic); + while (magic !=3D END_MAGIC) { + switch (magic) { + default: + qemu_log_mask(LOG_GUEST_ERROR, "signal: unknown extended state= in " + "sigcontext, magic=3D0x%08x\n",= magic); + return false; + } + + __get_user(size, &hdr->size); + if (size =3D=3D 0) { + qemu_log_mask(LOG_GUEST_ERROR, "signal: extended state in " + "sigcontext has size 0\n"); + return false; + } + + hdr =3D (void *)hdr + size; + __get_user(magic, &hdr->magic); + } + + __get_user(size, &hdr->size); + if (size !=3D END_HDR_SIZE) { + qemu_log_mask(LOG_GUEST_ERROR, "signal: extended state end header = has " + "size=3D%u (should be 0)\n", size); + return false; + } + return true; } =20 diff --git a/linux-user/riscv/vdso-asmoffset.h b/linux-user/riscv/vdso-asmo= ffset.h index 123902ef61..92e8ac10ab 100644 --- a/linux-user/riscv/vdso-asmoffset.h +++ b/linux-user/riscv/vdso-asmoffset.h @@ -1,9 +1,9 @@ #ifdef TARGET_ABI32 -# define sizeof_rt_sigframe 0x2b0 +# define sizeof_rt_sigframe 0x3b0 # define offsetof_uc_mcontext 0x120 # define offsetof_freg0 0x80 #else -# define sizeof_rt_sigframe 0x340 +# define sizeof_rt_sigframe 0x440 # define offsetof_uc_mcontext 0x130 # define offsetof_freg0 0x100 #endif --=20 2.51.0 From nobody Sun Mar 22 14:25:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Nicholas Piggin --- linux-user/riscv/signal.c | 175 +++++++++++++++++++++++++++++++++-- target/riscv/cpu.h | 4 + target/riscv/csr.c | 7 +- target/riscv/vector_helper.c | 19 +++- 4 files changed, 191 insertions(+), 14 deletions(-) diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c index e20b9ac177..2e1a1a5027 100644 --- a/linux-user/riscv/signal.c +++ b/linux-user/riscv/signal.c @@ -41,7 +41,17 @@ struct target_fp_state { uint32_t fcsr; }; =20 +struct target_v_ext_state { + abi_ulong vstart; + abi_ulong vl; + abi_ulong vtype; + abi_ulong vcsr; + abi_ulong vlenb; + abi_ptr datap; +}; + /* The Magic number for signal context frame header. */ +#define RISCV_V_MAGIC 0x53465457 #define END_MAGIC 0x0 =20 /* The size of END signal context header. */ @@ -106,6 +116,130 @@ static abi_ulong get_sigframe(struct target_sigaction= *ka, return sp; } =20 +static unsigned int get_v_state_hdr_size(CPURISCVState *env) +{ + return sizeof(struct target_ctx_hdr) + + sizeof(struct target_v_ext_state); +} + +static unsigned int get_v_state_data_size(CPURISCVState *env) +{ + RISCVCPU *cpu =3D env_archcpu(env); + return cpu->cfg.vlenb * 32; +} + +static struct target_ctx_hdr *save_v_state(CPURISCVState *env, + struct target_ctx_hdr *hdr) +{ + RISCVCPU *cpu =3D env_archcpu(env); + target_ulong vlenb =3D cpu->cfg.vlenb; + uint32_t riscv_v_sc_size =3D get_v_state_hdr_size(env) + + get_v_state_data_size(env); + struct target_v_ext_state *vs; + abi_ulong vcsr; + abi_ptr datap; + void *host_datap; + +#ifdef CONFIG_DEBUG_REMAP + /* + * The host pointers are derived from lock_user, not g2h, so + * h2g can not be used when CONFIG_DEBUG_REMAP=3Dy. + */ + qemu_log_mask(LOG_UNIMP, "signal: sigcontext can not save V state " + "when CONFIG_DEBUG_REMAP=3Dy\n"); + return hdr; +#endif + + vs =3D (struct target_v_ext_state *)(hdr + 1); + vcsr =3D riscv_csr_read(env, CSR_VCSR); + host_datap =3D (vs + 1); + datap =3D h2g(host_datap); + + __put_user(RISCV_V_MAGIC, &hdr->magic); + __put_user(riscv_v_sc_size, &hdr->size); + + __put_user(env->vstart, &vs->vstart); + __put_user(env->vl, &vs->vl); + __put_user(env->vtype, &vs->vtype); + __put_user(vcsr, &vs->vcsr); + __put_user(vlenb, &vs->vlenb); + __put_user(datap, &vs->datap); + + for (int i =3D 0; i < 32; i++) { + for (int j =3D 0; j < vlenb; j +=3D 8) { + size_t idx =3D (i * vlenb + j); + __put_user(env->vreg[idx / 8], + (uint64_t *)(host_datap + idx)); + } + } + + return (void *)hdr + riscv_v_sc_size; +} + +static bool restore_v_state(CPURISCVState *env, + struct target_ctx_hdr *hdr) +{ + RISCVCPU *cpu =3D env_archcpu(env); + target_ulong vlenb; + target_ulong vcsr, vl, vtype, vstart; + struct target_v_ext_state *vs; + uint32_t size; + abi_ptr datap; + void *host_datap; + + if (!riscv_has_ext(env, RVV)) { + qemu_log_mask(LOG_GUEST_ERROR, "signal: sigcontext has V state but= " + "CPU does not support V extension\n= "); + return false; + } + + __get_user(size, &hdr->size); + if (size < get_v_state_hdr_size(env)) { + qemu_log_mask(LOG_GUEST_ERROR, "signal: sigcontext V state header " + "size is too small (%u)\n", size); + return false; + } + + vs =3D (struct target_v_ext_state *)(hdr + 1); + + __get_user(vstart, &vs->vstart); + __get_user(vl, &vs->vl); + __get_user(vtype, &vs->vtype); + __get_user(vcsr, &vs->vcsr); + + riscv_cpu_set_vstart(env, vstart); + riscv_cpu_vsetvl(env, vl, vtype, 0); + riscv_csr_write(env, CSR_VCSR, vcsr); + + __get_user(vlenb, &vs->vlenb); + + if (vlenb !=3D cpu->cfg.vlenb) { + qemu_log_mask(LOG_GUEST_ERROR, "signal: sigcontext has invalid " + "vlenb\n"); + return false; + } + + __get_user(datap, &vs->datap); + + host_datap =3D lock_user(VERIFY_READ, datap, vlenb * 32, true); + if (!host_datap) { + qemu_log_mask(LOG_GUEST_ERROR, "signal: sigcontext has V state but= " + "datap pointer is invalid\n"); + return false; + } + + for (int i =3D 0; i < 32; i++) { + for (int j =3D 0; j < vlenb; j +=3D 8) { + size_t idx =3D (i * vlenb + j); + __get_user(env->vreg[idx / 8], + (uint64_t *)(host_datap + idx)); + } + } + unlock_user(host_datap, datap, 0); + + return true; +} + static void setup_sigcontext(struct target_sigcontext *sc, CPURISCVState *= env) { struct target_ctx_hdr *hdr; @@ -126,6 +260,9 @@ static void setup_sigcontext(struct target_sigcontext *= sc, CPURISCVState *env) __put_user(0, &sc->sc_extdesc.reserved); =20 hdr =3D &sc->sc_extdesc.hdr; + if (riscv_has_ext(env, RVV)) { + hdr =3D save_v_state(env, hdr); + } __put_user(END_MAGIC, &hdr->magic); __put_user(END_HDR_SIZE, &hdr->size); } @@ -152,17 +289,24 @@ void setup_rt_frame(int sig, struct target_sigaction = *ka, { abi_ulong frame_addr; struct target_rt_sigframe *frame; + size_t frame_size =3D sizeof(*frame); =20 - frame_addr =3D get_sigframe(ka, env, sizeof(*frame)); + if (riscv_has_ext(env, RVV)) { + frame_size +=3D get_v_state_hdr_size(env) + + get_v_state_data_size(env); + } + + frame_addr =3D get_sigframe(ka, env, frame_size); trace_user_setup_rt_frame(env, frame_addr); =20 - if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) { + frame =3D lock_user(VERIFY_WRITE, frame_addr, frame_size, 0); + if (!frame) { goto badframe; } =20 setup_ucontext(&frame->uc, env, set); frame->info =3D *info; - unlock_user_struct(frame, frame_addr, 1); + unlock_user(frame, frame_addr, frame_size); =20 env->pc =3D ka->_sa_handler; env->gpr[xSP] =3D frame_addr; @@ -174,7 +318,7 @@ void setup_rt_frame(int sig, struct target_sigaction *k= a, return; =20 badframe: - unlock_user_struct(frame, frame_addr, 1); + unlock_user(frame, frame_addr, frame_size); if (sig =3D=3D TARGET_SIGSEGV) { ka->_sa_handler =3D TARGET_SIG_DFL; } @@ -211,6 +355,11 @@ static bool restore_sigcontext(CPURISCVState *env, str= uct target_sigcontext *sc) __get_user(magic, &hdr->magic); while (magic !=3D END_MAGIC) { switch (magic) { + case RISCV_V_MAGIC: + if (!restore_v_state(env, hdr)) { + return false; + } + break; default: qemu_log_mask(LOG_GUEST_ERROR, "signal: unknown extended state= in " "sigcontext, magic=3D0x%08x\n",= magic); @@ -258,11 +407,23 @@ static bool restore_ucontext(CPURISCVState *env, stru= ct target_ucontext *uc) long do_rt_sigreturn(CPURISCVState *env) { struct target_rt_sigframe *frame; + size_t frame_size =3D sizeof(*frame); abi_ulong frame_addr; =20 + if (riscv_has_ext(env, RVV)) { + /* + * userspace may have set up a discontiguous V state data area, + * so need to map that region separately once the address is + * known, from datap. + */ + frame_size +=3D get_v_state_hdr_size(env); + } + frame_addr =3D env->gpr[xSP]; trace_user_do_sigreturn(env, frame_addr); - if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1)) { + + frame =3D lock_user(VERIFY_READ, frame_addr, frame_size, 1); + if (!frame) { goto badframe; } =20 @@ -272,11 +433,11 @@ long do_rt_sigreturn(CPURISCVState *env) =20 target_restore_altstack(&frame->uc.uc_stack, env); =20 - unlock_user_struct(frame, frame_addr, 0); + unlock_user(frame, frame_addr, 0); return -QEMU_ESIGRETURN; =20 badframe: - unlock_user_struct(frame, frame_addr, 0); + unlock_user(frame, frame_addr, 0); force_sig(TARGET_SIGSEGV); return 0; } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 35d1f6362c..e1eca79197 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -668,6 +668,10 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *e= nv, target_ulong riscv_cpu_get_fflags(CPURISCVState *env); void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); =20 +void riscv_cpu_set_vstart(CPURISCVState *env, target_ulong val); +target_ulong riscv_cpu_vsetvl(CPURISCVState *env, target_ulong s1, + target_ulong s2, target_ulong x0); + #ifndef CONFIG_USER_ONLY void cpu_set_exception_base(int vp_index, target_ulong address); #endif diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5064483917..8a6fd11fb5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -991,11 +991,8 @@ static RISCVException write_vstart(CPURISCVState *env,= int csrno, #if !defined(CONFIG_USER_ONLY) env->mstatus |=3D MSTATUS_VS; #endif - /* - * The vstart CSR is defined to have only enough writable bits - * to hold the largest element index, i.e. lg2(VLEN) bits. - */ - env->vstart =3D val & ~(~0ULL << ctzl(riscv_cpu_cfg(env)->vlenb << 3)); + riscv_cpu_set_vstart(env, val); + return RISCV_EXCP_NONE; } =20 diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index caa8dd9c12..bceefe019b 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -33,8 +33,17 @@ #include "vector_internals.h" #include =20 -target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, - target_ulong s2, target_ulong x0) +void riscv_cpu_set_vstart(CPURISCVState *env, target_ulong val) +{ + /* + * The vstart CSR is defined to have only enough writable bits + * to hold the largest element index, i.e. lg2(VLEN) bits. + */ + env->vstart =3D val & ~(~0ULL << ctzl(riscv_cpu_cfg(env)->vlenb << 3)); +} + +target_ulong riscv_cpu_vsetvl(CPURISCVState *env, target_ulong s1, + target_ulong s2, target_ulong x0) { int vlmax, vl; RISCVCPU *cpu =3D env_archcpu(env); @@ -99,6 +108,12 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_= ulong s1, return vl; } =20 +target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, + target_ulong s2, target_ulong x0) +{ + return riscv_cpu_vsetvl(env, s1, s2, x0); +} + /* * Get the maximum number of elements can be operated. * --=20 2.51.0 From nobody Sun Mar 22 14:25:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1774102504; cv=none; d=zohomail.com; s=zohoarc; b=dy7vbvmALmDsw3kLRHPuoJTYvpRiY3jD5zarFHXNQI/1KMkBXiksh5Hlei9G71vlWD9DX3Q2xp/jjVJAoJMrWI2iwdC9nIuSq5oCj9cvIuYT6rcCtJ0in+KKe1zb3YSZeEAbpZYA3+/bwNR/z8CXStZvrCxNITwajnrtmgKcfL4= ARC-Message-Signature: i=1; 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TESTS +=3D test-signal-handling -test-signal-handling: CFLAGS +=3D -march=3Drv64gc -run-test-signal-handling: QEMU_OPTS +=3D -cpu rv64 +test-signal-handling: CFLAGS +=3D -march=3Drv64gcv +run-test-signal-handling: QEMU_OPTS +=3D -cpu rv64,v=3Don diff --git a/tests/tcg/riscv64/test-signal-handling.c b/tests/tcg/riscv64/t= est-signal-handling.c index c202503382..b71fa6ee87 100644 --- a/tests/tcg/riscv64/test-signal-handling.c +++ b/tests/tcg/riscv64/test-signal-handling.c @@ -19,10 +19,27 @@ #include #include #include +#include +#include #include #include #include =20 +#ifdef __riscv_v_intrinsic +#include +#else +static inline unsigned long __riscv_vlenb(void) +{ + unsigned long vlenb; + __asm__ __volatile__ ("csrr %0, vlenb" : "=3Dr" (vlenb)); + return vlenb; +} +#endif + +#ifndef COMPAT_HWCAP_ISA_V +#define COMPAT_HWCAP_ISA_V (1 << ('V' - 'A')) +#endif + /* * This horrible hack seems to be required when including * signal.h and asm/sigcontext.h, to prevent sigcontext @@ -41,6 +58,10 @@ static uint64_t *signal_gvalues; static double *initial_fvalues; static double *final_fvalues; static double *signal_fvalues; +static size_t vlenb; +static uint8_t *initial_vvalues; +static uint8_t *final_vvalues; +static uint8_t *signal_vvalues; =20 extern unsigned long unimp_addr[]; =20 @@ -64,6 +85,8 @@ static void ILL_handler(int signo, siginfo_t *info, void = *context) { ucontext_t *uc =3D context; struct sigcontext *sc =3D (struct sigcontext *)&uc->uc_mcontext; + struct __riscv_ctx_hdr *sc_ext =3D &sc->sc_extdesc.hdr; + bool found_v =3D false; =20 got_signal =3D true; =20 @@ -82,12 +105,48 @@ static void ILL_handler(int signo, siginfo_t *info, vo= id *context) } /* Test sc->sc_fpregs.d.fcsr ? */ =20 + assert(sc->sc_extdesc.reserved =3D=3D 0); + while (sc_ext->magic !=3D END_MAGIC) { + assert(sc_ext->size !=3D 0); + + if (sc_ext->magic =3D=3D RISCV_V_MAGIC) { + struct __sc_riscv_v_state *sc_v_state =3D + (struct __sc_riscv_v_state *)(sc_ext + 1); + struct __riscv_v_ext_state *v_state =3D &sc_v_state->v_state; + + found_v =3D true; + + assert(getauxval(AT_HWCAP) & COMPAT_HWCAP_ISA_V); + + assert(v_state->vlenb =3D=3D vlenb); + assert(v_state->vtype =3D=3D 0xc0); /* vma, vta */ + assert(v_state->vl =3D=3D vlenb); + assert(v_state->vstart =3D=3D 0); + assert(v_state->vcsr =3D=3D 0); + + uint64_t *vregs =3D v_state->datap; + for (int i =3D 0; i < 32; i++) { + for (int j =3D 0; j < vlenb; j +=3D 8) { + size_t idx =3D (i * vlenb + j) / 8; + ((uint64_t *)signal_vvalues)[idx] =3D vregs[idx]; + } + } + } + + sc_ext =3D (void *)sc_ext + sc_ext->size; + } + + assert(sc_ext->size =3D=3D 0); + if (getauxval(AT_HWCAP) & COMPAT_HWCAP_ISA_V) { + assert(found_v); + } + sc->sc_regs.pc +=3D 4; } =20 static void init_test(void) { - int i; + int i, j; =20 callchain_root =3D find_callchain_root(); =20 @@ -107,6 +166,19 @@ static void init_test(void) memset(final_fvalues, 0, 8 * 32); signal_fvalues =3D malloc(8 * 32); memset(signal_fvalues, 0, 8 * 32); + + vlenb =3D __riscv_vlenb(); + initial_vvalues =3D malloc(vlenb * 32); + memset(initial_vvalues, 0, vlenb * 32); + for (i =3D 0; i < 32 ; i++) { + for (j =3D 0; j < vlenb; j++) { + initial_vvalues[i * vlenb + j] =3D i * vlenb + j; + } + } + final_vvalues =3D malloc(vlenb * 32); + memset(final_vvalues, 0, vlenb * 32); + signal_vvalues =3D malloc(vlenb * 32); + memset(signal_vvalues, 0, vlenb * 32); } =20 static void run_test(void) @@ -179,6 +251,72 @@ static void run_test(void) "fld f29, 0xe8(t0)\n\t" "fld f30, 0xf0(t0)\n\t" "fld f31, 0xf8(t0)\n\t" + /* Load initial values into vector registers */ + "mv t0, %[initial_vvalues]\n\t" + "vsetvli x0,%[vlenb],e8,m1,ta,ma\n\t" + "vle8.v v0, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v1, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v2, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v3, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v4, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v5, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v6, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v7, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v8, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v9, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v10, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v11, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v12, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v13, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v14, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v15, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v16, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v17, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v18, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v19, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v20, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v21, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v22, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v23, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v24, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v25, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v26, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v27, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v28, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v29, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v30, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vle8.v v31, (t0)\n\t" /* Trigger the SIGILL */ ".global unimp_addr\n\t" "unimp_addr:\n\t" @@ -251,19 +389,93 @@ static void run_test(void) "fsd f29, 0xe8(t0)\n\t" "fsd f30, 0xf0(t0)\n\t" "fsd f31, 0xf8(t0)\n\t" + /* Save final values from vector registers */ + "mv t0, %[final_vvalues]\n\t" + "vse8.v v0, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v1, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v2, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v3, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v4, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v5, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v6, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v7, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v8, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v9, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v10, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v11, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v12, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v13, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v14, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v15, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v16, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v17, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v18, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v19, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v20, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v21, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v22, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v23, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v24, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v25, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v26, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v27, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v28, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v29, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v30, (t0)\n\t" + "add t0, t0, %[vlenb]\n\t" + "vse8.v v31, (t0)\n\t" : "=3Dm" (initial_gvalues), "=3Dm" (final_gvalues), - "=3Dm" (final_fvalues) - : "m" (initial_fvalues), + "=3Dm" (final_fvalues), + "=3Dm" (final_vvalues) + : [vlenb] "r" (vlenb), + "m" (initial_fvalues), + "m" (initial_vvalues), [initial_gvalues] "r" (initial_gvalues), [initial_fvalues] "r" (initial_fvalues), + [initial_vvalues] "r" (initial_vvalues), [final_gvalues] "r" (final_gvalues), - [final_fvalues] "r" (final_fvalues) + [final_fvalues] "r" (final_fvalues), + [final_vvalues] "r" (final_vvalues) : "t0", "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", - "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"); + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", + "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", + "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", + "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", + "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"); =20 assert(got_signal); =20 @@ -272,7 +484,7 @@ static void run_test(void) * and is not a simple equality. */ assert(initial_gvalues[4] =3D=3D (unsigned long)initial_gvalues); - assert(signal_gvalues[4] =3D=3D (unsigned long)initial_fvalues); + assert(signal_gvalues[4] =3D=3D (unsigned long)initial_vvalues + 31 * = vlenb); assert(final_gvalues[4] =3D=3D (unsigned long)final_gvalues); initial_gvalues[4] =3D final_gvalues[4] =3D signal_gvalues[4] =3D 0; =20 @@ -284,6 +496,8 @@ static void run_test(void) assert(!memcmp(initial_gvalues, signal_gvalues, 8 * 31)); assert(!memcmp(initial_fvalues, final_fvalues, 8 * 32)); assert(!memcmp(initial_fvalues, signal_fvalues, 8 * 32)); + assert(!memcmp(initial_vvalues, signal_vvalues, vlenb * 32)); + assert(!memcmp(initial_vvalues, final_vvalues, vlenb * 32)); } =20 int main(void) --=20 2.51.0