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David Alan Gilbert" , qemu-ppc@nongnu.org, Max Filippov , Pierrick Bouvier , Chinmay Rath , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH-for-11.1 v2 2/7] target/ppc: Have 'info tlb' dump MMU information on monitor Date: Fri, 20 Mar 2026 17:50:15 +0100 Message-ID: <20260320165021.39521-3-philmd@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260320165021.39521-1-philmd@linaro.org> References: <20260320165021.39521-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774025468474158500 Currently 'info tlb' dumps the MMU information on stdout. Propagate the @Monitor argument and replace qemu_printf() by monitor_printf() -- or monitor_puts when no formatting -- to dump information over the monitor (which is not always stdout). Fixes: bebabbc7aa7 ("ppc: booke206: add "info tlb" support") Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/ppc/cpu.h | 2 +- target/ppc/mmu-hash64.h | 2 +- target/ppc/mmu-hash64.c | 10 +++---- target/ppc/mmu_common.c | 66 ++++++++++++++++++++--------------------- target/ppc/monitor.c | 2 +- 5 files changed, 41 insertions(+), 41 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 296e7604077..ba17ea83fa2 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -3082,7 +3082,7 @@ static inline bool ppc_interrupts_little_endian(Power= PCCPU *cpu, bool hv) } #endif =20 -void dump_mmu(CPUPPCState *env); +void dump_mmu(Monitor *mon, CPUPPCState *env); =20 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len); void ppc_store_vscr(CPUPPCState *env, uint32_t vscr); diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h index ae8d4b37aed..9ce6939191a 100644 --- a/target/ppc/mmu-hash64.h +++ b/target/ppc/mmu-hash64.h @@ -4,7 +4,7 @@ #ifndef CONFIG_USER_ONLY =20 #ifdef TARGET_PPC64 -void dump_slb(PowerPCCPU *cpu); +void dump_slb(Monitor *mon, PowerPCCPU *cpu); int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot, target_ulong esid, target_ulong vsid); bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_t= ype, diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 2c33d98001d..356aee0c92c 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -23,7 +23,6 @@ #include "exec/page-protection.h" #include "exec/target_page.h" #include "qemu/error-report.h" -#include "qemu/qemu-print.h" #include "system/hw_accel.h" #include "system/memory.h" #include "kvm_ppc.h" @@ -34,6 +33,7 @@ #include "mmu-book3s-v3.h" #include "mmu-books.h" #include "helper_regs.h" +#include "monitor/monitor.h" =20 #ifdef CONFIG_TCG #include "exec/helper-proto.h" @@ -83,7 +83,7 @@ static ppc_slb_t *slb_lookup(PowerPCCPU *cpu, target_ulon= g eaddr) return NULL; } =20 -void dump_slb(PowerPCCPU *cpu) +void dump_slb(Monitor *mon, PowerPCCPU *cpu) { CPUPPCState *env =3D &cpu->env; int i; @@ -91,15 +91,15 @@ void dump_slb(PowerPCCPU *cpu) =20 cpu_synchronize_state(CPU(cpu)); =20 - qemu_printf("SLB\tESID\t\t\tVSID\n"); + monitor_puts(mon, "SLB\tESID\t\t\tVSID\n"); for (i =3D 0; i < cpu->hash64_opts->slb_size; i++) { slbe =3D env->slb[i].esid; slbv =3D env->slb[i].vsid; if (slbe =3D=3D 0 && slbv =3D=3D 0) { continue; } - qemu_printf("%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n", - i, slbe, slbv); + monitor_printf(mon, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n", + i, slbe, slbv); } } =20 diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 52d48615ac2..5ea9b6d6773 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -29,11 +29,11 @@ #include "exec/log.h" #include "helper_regs.h" #include "qemu/error-report.h" -#include "qemu/qemu-print.h" #include "internal.h" #include "mmu-book3s-v3.h" #include "mmu-radix64.h" #include "mmu-booke.h" +#include "monitor/monitor.h" =20 /* #define DUMP_PAGE_TABLES */ =20 @@ -349,20 +349,20 @@ static const char *book3e_tsize_to_str[32] =3D { "1T", "2T" }; =20 -static void mmubooke_dump_mmu(CPUPPCState *env) +static void mmubooke_dump_mmu(Monitor *mon, CPUPPCState *env) { ppcemb_tlb_t *entry; int i; =20 #ifdef CONFIG_KVM if (kvm_enabled() && !env->kvm_sw_tlb) { - qemu_printf("Cannot access KVM TLB\n"); + monitor_puts(mon, "Cannot access KVM TLB\n"); return; } #endif =20 - qemu_printf("\nTLB:\n"); - qemu_printf("Effective Physical Size PID Prot = " + monitor_puts(mon, "\nTLB:\n"); + monitor_puts(mon, "Effective Physical Size PID Pr= ot " "Attr\n"); =20 entry =3D &env->tlb.tlbe[0]; @@ -387,21 +387,21 @@ static void mmubooke_dump_mmu(CPUPPCState *env) } else { snprintf(size_buf, sizeof(size_buf), "%3" PRId64 "k", size / K= iB); } - qemu_printf("0x%016" PRIx64 " 0x%016" PRIx64 " %s %-5u %08x %08x\n= ", + monitor_printf(mon, "0x%016" PRIx64 " 0x%016" PRIx64 " %s %-5u %08= x %08x\n", (uint64_t)ea, (uint64_t)pa, size_buf, (uint32_t)entry-= >PID, entry->prot, entry->attr); } =20 } =20 -static void mmubooke206_dump_one_tlb(CPUPPCState *env, int tlbn, int offse= t, - int tlbsize) +static void mmubooke206_dump_one_tlb(Monitor *mon, CPUPPCState *env, + int tlbn, int offset, int tlbsize) { ppcmas_tlb_t *entry; int i; =20 - qemu_printf("\nTLB%d:\n", tlbn); - qemu_printf("Effective Physical Size TID TS SRWX" + monitor_printf(mon, "\nTLB%d:\n", tlbn); + monitor_puts(mon, "Effective Physical Size TID TS= SRWX" " URWX WIMGE U0123\n"); =20 entry =3D &env->tlb.tlbm[offset]; @@ -418,7 +418,7 @@ static void mmubooke206_dump_one_tlb(CPUPPCState *env, = int tlbn, int offset, ea =3D entry->mas2 & ~(size - 1); pa =3D entry->mas7_3 & ~(size - 1); =20 - qemu_printf("0x%016" PRIx64 " 0x%016" PRIx64 " %4s %-5u %1u S%c%c= %c" + monitor_printf(mon, "0x%016" PRIx64 " 0x%016" PRIx64 " %4s %-5u %1= u S%c%c%c" " U%c%c%c %c%c%c%c%c U%c%c%c%c\n", (uint64_t)ea, (uint64_t)pa, book3e_tsize_to_str[tsize], @@ -442,14 +442,14 @@ static void mmubooke206_dump_one_tlb(CPUPPCState *env= , int tlbn, int offset, } } =20 -static void mmubooke206_dump_mmu(CPUPPCState *env) +static void mmubooke206_dump_mmu(Monitor *mon, CPUPPCState *env) { int offset =3D 0; int i; =20 #ifdef CONFIG_KVM if (kvm_enabled() && !env->kvm_sw_tlb) { - qemu_printf("Cannot access KVM TLB\n"); + monitor_puts(mon, "Cannot access KVM TLB\n"); return; } #endif @@ -461,12 +461,12 @@ static void mmubooke206_dump_mmu(CPUPPCState *env) continue; } =20 - mmubooke206_dump_one_tlb(env, i, offset, size); + mmubooke206_dump_one_tlb(mon, env, i, offset, size); offset +=3D size; } } =20 -static void mmu6xx_dump_BATs(CPUPPCState *env, int type) +static void mmu6xx_dump_BATs(Monitor *mon, CPUPPCState *env, int type) { target_ulong *BATlt, *BATut, *BATu, *BATl; target_ulong BEPIl, BEPIu, bl; @@ -489,7 +489,7 @@ static void mmu6xx_dump_BATs(CPUPPCState *env, int type) BEPIu =3D *BATu & BATU32_BEPIU; BEPIl =3D *BATu & BATU32_BEPIL; bl =3D (*BATu & BATU32_BL) << 15; - qemu_printf("%s BAT%d BATu " TARGET_FMT_lx + monitor_printf(mon, "%s BAT%d BATu " TARGET_FMT_lx " BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " " TARGET_FMT_lx " " TARGET_FMT_lx "\n", type =3D=3D ACCESS_CODE ? "code" : "data", i, @@ -497,38 +497,38 @@ static void mmu6xx_dump_BATs(CPUPPCState *env, int ty= pe) } } =20 -static void mmu6xx_dump_mmu(CPUPPCState *env) +static void mmu6xx_dump_mmu(Monitor *mon, CPUPPCState *env) { PowerPCCPU *cpu =3D env_archcpu(env); ppc6xx_tlb_t *tlb; target_ulong sr; int type, way, entry, i; =20 - qemu_printf("HTAB base =3D 0x%"HWADDR_PRIx"\n", ppc_hash32_hpt_base(cp= u)); - qemu_printf("HTAB mask =3D 0x%"HWADDR_PRIx"\n", ppc_hash32_hpt_mask(cp= u)); + monitor_printf(mon, "HTAB base =3D 0x%"HWADDR_PRIx"\n", ppc_hash32_hpt= _base(cpu)); + monitor_printf(mon, "HTAB mask =3D 0x%"HWADDR_PRIx"\n", ppc_hash32_hpt= _mask(cpu)); =20 - qemu_printf("\nSegment registers:\n"); + monitor_puts(mon, "\nSegment registers:\n"); for (i =3D 0; i < 32; i++) { sr =3D env->sr[i]; if (sr & 0x80000000) { - qemu_printf("%02d T=3D%d Ks=3D%d Kp=3D%d BUID=3D0x%03x " + monitor_printf(mon, "%02d T=3D%d Ks=3D%d Kp=3D%d BUID=3D0x%03x= " "CNTLR_SPEC=3D0x%05x\n", i, sr & 0x80000000 ? 1 : 0, sr & 0x40000000 ? 1 : 0, sr & 0x20000000 ? 1 : 0, (uint32_t)((sr >> 20) & 0= x1FF), (uint32_t)(sr & 0xFFFFF)); } else { - qemu_printf("%02d T=3D%d Ks=3D%d Kp=3D%d N=3D%d VSID=3D0x%06x\= n", i, + monitor_printf(mon, "%02d T=3D%d Ks=3D%d Kp=3D%d N=3D%d VSID= =3D0x%06x\n", i, sr & 0x80000000 ? 1 : 0, sr & 0x40000000 ? 1 : 0, sr & 0x20000000 ? 1 : 0, sr & 0x10000000 ? 1 : 0, (uint32_t)(sr & 0x00FFFFFF)); } } =20 - qemu_printf("\nBATs:\n"); - mmu6xx_dump_BATs(env, ACCESS_INT); - mmu6xx_dump_BATs(env, ACCESS_CODE); + monitor_puts(mon, "\nBATs:\n"); + mmu6xx_dump_BATs(mon, env, ACCESS_INT); + mmu6xx_dump_BATs(mon, env, ACCESS_CODE); =20 - qemu_printf("\nTLBs [EPN EPN + SIZE]\n"); + monitor_puts(mon, "\nTLBs [EPN EPN + SIZE]\n"= ); for (type =3D 0; type < 2; type++) { for (way =3D 0; way < env->nb_ways; way++) { for (entry =3D env->nb_tlb * type + env->tlb_per_way * way; @@ -536,7 +536,7 @@ static void mmu6xx_dump_mmu(CPUPPCState *env) entry++) { =20 tlb =3D &env->tlb.tlb6[entry]; - qemu_printf("%s TLB %02d/%02d way:%d %s [" + monitor_printf(mon, "%s TLB %02d/%02d way:%d %s [" TARGET_FMT_lx " " TARGET_FMT_lx "]\n", type ? "code" : "data", entry % env->nb_tlb, env->nb_tlb, way, @@ -547,31 +547,31 @@ static void mmu6xx_dump_mmu(CPUPPCState *env) } } =20 -void dump_mmu(CPUPPCState *env) +void dump_mmu(Monitor *mon, CPUPPCState *env) { switch (env->mmu_model) { case POWERPC_MMU_BOOKE: - mmubooke_dump_mmu(env); + mmubooke_dump_mmu(mon, env); break; case POWERPC_MMU_BOOKE206: - mmubooke206_dump_mmu(env); + mmubooke206_dump_mmu(mon, env); break; case POWERPC_MMU_SOFT_6xx: - mmu6xx_dump_mmu(env); + mmu6xx_dump_mmu(mon, env); break; #if defined(TARGET_PPC64) case POWERPC_MMU_64B: case POWERPC_MMU_2_03: case POWERPC_MMU_2_06: case POWERPC_MMU_2_07: - dump_slb(env_archcpu(env)); + dump_slb(mon, env_archcpu(env)); break; case POWERPC_MMU_3_00: if (ppc64_v3_radix(env_archcpu(env))) { qemu_log_mask(LOG_UNIMP, "%s: the PPC64 MMU is unsupported\n", __func__); } else { - dump_slb(env_archcpu(env)); + dump_slb(mon, env_archcpu(env)); } break; #endif diff --git a/target/ppc/monitor.c b/target/ppc/monitor.c index 7c88e0e2bda..41337d77a89 100644 --- a/target/ppc/monitor.c +++ b/target/ppc/monitor.c @@ -19,5 +19,5 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict) monitor_printf(mon, "No CPU available\n"); return; } - dump_mmu(env1); + dump_mmu(mon, env1); } --=20 2.53.0