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Fri, 20 Mar 2026 06:06:21 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Alexander Graf , Peter Maydell , qemu-arm@nongnu.org, Pedro Barbuda , Mohamed Mediouni , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [RFC PATCH 34/35] tests/tcg: create a mini-gic3 library Date: Fri, 20 Mar 2026 13:06:05 +0000 Message-ID: <20260320130607.2071996-35-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260320130607.2071996-1-alex.bennee@linaro.org> References: <20260320130607.2071996-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774012012435158500 Just enough GIC to trigger timer interrupts. Signed-off-by: Alex Benn=C3=A9e --- tests/tcg/aarch64/system/lib/gicv3.h | 56 +++++++++++++++++ tests/tcg/aarch64/system/lib/gicv3.c | 77 +++++++++++++++++++++++ tests/tcg/aarch64/Makefile.softmmu-target | 7 ++- 3 files changed, 138 insertions(+), 2 deletions(-) create mode 100644 tests/tcg/aarch64/system/lib/gicv3.h create mode 100644 tests/tcg/aarch64/system/lib/gicv3.c diff --git a/tests/tcg/aarch64/system/lib/gicv3.h b/tests/tcg/aarch64/syste= m/lib/gicv3.h new file mode 100644 index 00000000000..9a1268937c6 --- /dev/null +++ b/tests/tcg/aarch64/system/lib/gicv3.h @@ -0,0 +1,56 @@ +/* + * GICv3 Helper Library + * + * Copyright (c) 2024 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef GICV3_H +#define GICV3_H + +#include + +/* Virt machine GICv3 base addresses */ +#define GICD_BASE 0x08000000 /* c.f. VIRT_GIC_DIST */ +#define GICR_BASE 0x080a0000 /* c.f. VIRT_GIC_REDIST */ + +/* Distributor registers */ +#define GICD_CTLR (GICD_BASE + 0x0000) +#define GICD_TYPER (GICD_BASE + 0x0004) +#define GICD_IIDR (GICD_BASE + 0x0008) + +/* Redistributor registers (per-CPU) */ +#define GICR_SGI_OFFSET 0x00010000 + +#define GICR_CTLR 0x0000 +#define GICR_WAKER 0x0014 +#define GICR_IGROUPR0 (GICR_SGI_OFFSET + 0x0080) +#define GICR_ISENABLER0 (GICR_SGI_OFFSET + 0x0100) +#define GICR_IPRIORITYR0 (GICR_SGI_OFFSET + 0x0400) + +/* GICD_CTLR bits */ +#define GICD_CTLR_ARE_NS (1U << 4) +#define GICD_CTLR_ENA_G1NS (1U << 1) +#define GICD_CTLR_ENA_G0 (1U << 0) + +/* GICR_WAKER bits */ +#define GICR_WAKER_ChildrenAsleep (1U << 2) +#define GICR_WAKER_ProcessorSleep (1U << 1) + +/** + * gicv3_init: + * + * Initialize GICv3 distributor and the redistributor for the current CPU. + */ +void gicv3_init(void); + +/** + * gicv3_enable_irq: + * @irq: The IRQ number to enable + * + * Enable the specified IRQ (SPI or PPI). + */ +void gicv3_enable_irq(unsigned int irq); + +#endif /* GICV3_H */ diff --git a/tests/tcg/aarch64/system/lib/gicv3.c b/tests/tcg/aarch64/syste= m/lib/gicv3.c new file mode 100644 index 00000000000..a09a0e430e6 --- /dev/null +++ b/tests/tcg/aarch64/system/lib/gicv3.c @@ -0,0 +1,77 @@ +/* + * GICv3 Helper Library Implementation + * + * Copyright (c) 2024 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "gicv3.h" + +#define write_sysreg(r, v) do { \ + uint64_t __val =3D (uint64_t)(v); \ + asm volatile("msr " #r ", %x0" \ + : : "rZ" (__val)); \ +} while (0) + +#define isb() asm volatile("isb" : : : "memory") + +static inline void write_reg(uintptr_t addr, uint32_t val) +{ + *(volatile uint32_t *)addr =3D val; +} + +static inline uint32_t read_reg(uintptr_t addr) +{ + return *(volatile uint32_t *)addr; +} + +void gicv3_init(void) +{ + uint32_t val; + + /* 1. Enable Distributor ARE and Group 1 NS */ + val =3D read_reg(GICD_CTLR); + val |=3D GICD_CTLR_ARE_NS | GICD_CTLR_ENA_G1NS; + write_reg(GICD_CTLR, val); + + /* 2. Wake up Redistributor 0 */ + /* Clear ProcessorSleep */ + val =3D read_reg(GICR_BASE + GICR_WAKER); + val &=3D ~GICR_WAKER_ProcessorSleep; + write_reg(GICR_BASE + GICR_WAKER, val); + + /* Wait for ChildrenAsleep to be cleared */ + while (read_reg(GICR_BASE + GICR_WAKER) & GICR_WAKER_ChildrenAsleep) { + /* spin */ + } + + /* 3. Enable CPU interface */ + /* Set Priority Mask to allow all interrupts */ + write_sysreg(ICC_PMR_EL1, 0xff); + /* Enable Group 1 Non-Secure interrupts */ + write_sysreg(ICC_IGRPEN1_EL1, 1); + isb(); +} + +void gicv3_enable_irq(unsigned int irq) +{ + if (irq < 32) { + /* PPI: use GICR_ISENABLER0 */ + uintptr_t addr; + + /* Set Group 1 */ + addr =3D GICR_BASE + GICR_IGROUPR0; + write_reg(addr, read_reg(addr) | (1U << irq)); + + /* Set priority (0xa0) */ + addr =3D GICR_BASE + GICR_IPRIORITYR0 + irq; + *(volatile uint8_t *)addr =3D 0xa0; + + /* Enable it */ + addr =3D GICR_BASE + GICR_ISENABLER0; + write_reg(addr, 1U << irq); + } else { + /* SPI: not implemented yet */ + } +} diff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/= Makefile.softmmu-target index f7a7d2b800f..c0939a0eeca 100644 --- a/tests/tcg/aarch64/Makefile.softmmu-target +++ b/tests/tcg/aarch64/Makefile.softmmu-target @@ -4,8 +4,9 @@ =20 AARCH64_SRC=3D$(SRC_PATH)/tests/tcg/aarch64 AARCH64_SYSTEM_SRC=3D$(AARCH64_SRC)/system +AARCH64_SYSTEM_LIB_SRC=3D$(AARCH64_SYSTEM_SRC)/lib =20 -VPATH+=3D$(AARCH64_SYSTEM_SRC) +VPATH+=3D$(AARCH64_SYSTEM_SRC) $(AARCH64_SYSTEM_LIB_SRC) =20 # These objects provide the basic boot code and helper functions for all t= ests CRT_OBJS=3Dboot.o @@ -24,7 +25,7 @@ LINK_SCRIPT=3D$(AARCH64_SYSTEM_SRC)/kernel.ld LDFLAGS=3D-Wl,-T$(LINK_SCRIPT) TESTS+=3D$(AARCH64_TESTS) $(MULTIARCH_TESTS) EXTRA_RUNS+=3D$(MULTIARCH_RUNS) -CFLAGS+=3D-nostdlib -ggdb -O0 $(MINILIB_INC) +CFLAGS+=3D-nostdlib -ggdb -O0 $(MINILIB_INC) -I$(AARCH64_SYSTEM_LIB_SRC) LDFLAGS+=3D-static -nostdlib $(CRT_OBJS) $(MINILIB_OBJS) -lgcc =20 config-cc.mak: Makefile @@ -102,6 +103,8 @@ run-pauth-3: $(call skip-test, "RUN of pauth-3", "not built") endif =20 +gicv3.o: gicv3.c gicv3.h + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ ifneq ($(CROSS_CC_HAS_ARMV8_MTE),) QEMU_MTE_ENABLED_MACHINE=3D-M virt,mte=3Don -cpu max -display none QEMU_OPTS_WITH_MTE_ON =3D $(QEMU_MTE_ENABLED_MACHINE) $(QEMU_BASE_ARGS) -k= ernel --=20 2.47.3