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Fri, 20 Mar 2026 06:15:55 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Alexander Graf , Peter Maydell , qemu-arm@nongnu.org, Pedro Barbuda , Mohamed Mediouni , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [RFC PATCH 33/35] tests/tcg: split stage 1 between devices and RAM Date: Fri, 20 Mar 2026 13:06:04 +0000 Message-ID: <20260320130607.2071996-34-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260320130607.2071996-1-alex.bennee@linaro.org> References: <20260320130607.2071996-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774012604988158500 All the -M virt devices live in the first GB of address space. Add a 1Gb block mapping for devices and continue pointing the second block at stage 2 and adjust appropriately. Signed-off-by: Alex Benn=C3=A9e --- tests/tcg/aarch64/system/boot.S | 43 ++++++++++++++++++++------------- 1 file changed, 26 insertions(+), 17 deletions(-) diff --git a/tests/tcg/aarch64/system/boot.S b/tests/tcg/aarch64/system/boo= t.S index 8bfa4e4efc7..03a5bad2ab0 100644 --- a/tests/tcg/aarch64/system/boot.S +++ b/tests/tcg/aarch64/system/boot.S @@ -248,29 +248,34 @@ at_testel: msr ttbr0_el1, x0 =20 /* - * Setup a flat address mapping page-tables. Stage one simply - * maps RAM to the first Gb. The stage2 tables have two 2mb - * translation block entries covering a series of adjacent - * 4k pages. + * Setup a flat address mapping page-tables. + * + * ttb (Level 1): + * - Entry 0 [0 - 1GB]: 1GB Device block (for GIC and other H/W) + * - Entry 1 [1GB - 2GB]: Table entry pointing to ttb_stage2 (for RAM) */ =20 - /* Stage 1 entry: indexed by IA[38:30] */ - adr x1, . /* phys address */ - bic x1, x1, #(1 << 30) - 1 /* 1GB alignment*/ - add x2, x0, x1, lsr #(30 - 3) /* offset in l1 page table */ + /* Entry 0: 1GB Device block mapping at 0x0 */ + ldr x1, =3D0x401 | (1 << 2) /* AF=3D1, block, AttrIndx=3DAttr1 (Device) = */ + str x1, [x0] =20 - /* point to stage 2 table [47:12] */ - adrp x0, ttb_stage2 - orr x1, x0, #3 /* ptr to stage 2 */ - str x1, [x2] + /* Entry 1: Table entry pointing to ttb_stage2 */ + adrp x1, ttb_stage2 + orr x1, x1, #3 /* ptr to table (type=3D3) */ + str x1, [x0, #8] =20 - /* Stage 2 entries: indexed by IA[29:21] */ + /* Stage 2 entries: indexed by IA[29:21] (within 1GB-2GB range) */ + adrp x0, ttb_stage2 + add x0, x0, :lo12:ttb_stage2 ldr x5, =3D(((1 << 9) - 1) << 21) =20 /* First block: .text/RO/execute enabled */ adr x1, . /* phys address */ bic x1, x1, #(1 << 21) - 1 /* 2mb block alignment */ - and x4, x1, x5 /* IA[29:21] */ + /* Note: we assume RAM is in the 1GB-2GB range, so IA[30] is 1 */ + mov x4, x1 + bic x4, x4, #(1 << 30) /* remove 1GB offset for L2 index */ + and x4, x4, x5 /* IA[29:21] */ add x2, x0, x4, lsr #(21 - 3) /* offset in l2 page table */ ldr x3, =3D0x401 /* attr(AF, block) */ orr x1, x1, x3 @@ -280,7 +285,9 @@ at_testel: adrp x1, .data add x1, x1, :lo12:.data bic x1, x1, #(1 << 21) - 1 /* 2mb block alignment */ - and x4, x1, x5 /* IA[29:21] */ + mov x4, x1 + bic x4, x4, #(1 << 30) /* remove 1GB offset for L2 index */ + and x4, x4, x5 /* IA[29:21] */ add x2, x0, x4, lsr #(21 - 3) /* offset in l2 page table */ ldr x3, =3D(3 << 53) | 0x401 /* attr(AF, NX, block) */ orr x1, x1, x3 @@ -290,7 +297,9 @@ at_testel: adrp x1, mte_page add x1, x1, :lo12:mte_page bic x1, x1, #(1 << 21) - 1 - and x4, x1, x5 + mov x4, x1 + bic x4, x4, #(1 << 30) /* remove 1GB offset for L2 index */ + and x4, x4, x5 add x2, x0, x4, lsr #(21 - 3) /* attr(AF, NX, block, AttrIndx=3DAttr1) */ ldr x3, =3D(3 << 53) | 0x401 | (1 << 2) @@ -317,7 +326,7 @@ at_testel: ldr x0, =3D (2 << 32) | 25 | (3 << 10) | (3 << 8) msr tcr_el1, x0 =20 - mov x0, #0xee /* Inner/outer cacheable WB */ + ldr x0, =3D0x04ee /* Attr1: Device-nGnRE, Attr0: Normal WB */ msr mair_el1, x0 isb =20 --=20 2.47.3