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Fri, 20 Mar 2026 06:06:09 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Alexander Graf , Peter Maydell , qemu-arm@nongnu.org, Pedro Barbuda , Mohamed Mediouni , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [RFC PATCH 02/35] target/arm: migrate system/cp trap syndromes to registerfields Date: Fri, 20 Mar 2026 13:05:33 +0000 Message-ID: <20260320130607.2071996-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260320130607.2071996-1-alex.bennee@linaro.org> References: <20260320130607.2071996-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774012113414154100 Migrate syn_aa64_sysregtrap and co-processor register trap syndromes to the registerfields API. The co-processor syndromes are split between single and duel register moves. Signed-off-by: Alex Benn=C3=A9e --- target/arm/syndrome.h | 118 +++++++++++++++++++++++++++++++++++------- 1 file changed, 99 insertions(+), 19 deletions(-) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 517fb2368bc..3d2660614c6 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -208,53 +208,133 @@ static inline uint32_t syn_aa32_bkpt(uint32_t imm16,= bool is_16bit) return res; } =20 +/* + * ISS encoding for an exception from MSR, MRS, or System instruction + * in AArch64 state. + */ +FIELD(SYSREG_ISS, ISREAD, 0, 1) /* Direction, 1 is read */ +FIELD(SYSREG_ISS, CRM, 1, 4) +FIELD(SYSREG_ISS, RT, 5, 5) +FIELD(SYSREG_ISS, CRN, 10, 4) +FIELD(SYSREG_ISS, OP1, 14, 3) +FIELD(SYSREG_ISS, OP2, 17, 3) +FIELD(SYSREG_ISS, OP0, 20, 2) + static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, int crn, int crm, int rt, int isread) { - return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL - | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5) - | (crm << 1) | isread; + uint32_t res =3D syn_set_ec(0, EC_SYSTEMREGISTERTRAP); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + + res =3D FIELD_DP32(res, SYSREG_ISS, OP0, op0); + res =3D FIELD_DP32(res, SYSREG_ISS, OP2, op2); + res =3D FIELD_DP32(res, SYSREG_ISS, OP1, op1); + res =3D FIELD_DP32(res, SYSREG_ISS, CRN, crn); + res =3D FIELD_DP32(res, SYSREG_ISS, RT, rt); + res =3D FIELD_DP32(res, SYSREG_ISS, CRM, crm); + res =3D FIELD_DP32(res, SYSREG_ISS, ISREAD, isread); + + return res; } =20 +/* + * ISS encoding for an exception from an MCR or MRC access + * (move to/from co-processor) + */ +FIELD(COPROC_ISS, ISREAD, 0, 1) +FIELD(COPROC_ISS, CRM, 1, 4) +FIELD(COPROC_ISS, RT, 5, 5) +FIELD(COPROC_ISS, CRN, 10, 4) +FIELD(COPROC_ISS, OP1, 14, 3) +FIELD(COPROC_ISS, OP2, 17, 3) +FIELD(COPROC_ISS, COND, 20, 4) +FIELD(COPROC_ISS, CV, 24, 1) + static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int op= c2, int crn, int crm, int rt, int isre= ad, bool is_16bit) { - return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) - | (crn << 10) | (rt << 5) | (crm << 1) | isread; + uint32_t res =3D syn_set_ec(0, EC_CP14RTTRAP); + res =3D FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1); + + res =3D FIELD_DP32(res, COPROC_ISS, CV, cv); + res =3D FIELD_DP32(res, COPROC_ISS, COND, cond); + res =3D FIELD_DP32(res, COPROC_ISS, OP2, opc2); + res =3D FIELD_DP32(res, COPROC_ISS, OP1, opc1); + res =3D FIELD_DP32(res, COPROC_ISS, CRN, crn); + res =3D FIELD_DP32(res, COPROC_ISS, RT, rt); + res =3D FIELD_DP32(res, COPROC_ISS, CRM, crm); + res =3D FIELD_DP32(res, COPROC_ISS, ISREAD, isread); + + return res; } =20 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int op= c2, int crn, int crm, int rt, int isre= ad, bool is_16bit) { - return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) - | (crn << 10) | (rt << 5) | (crm << 1) | isread; + uint32_t res =3D syn_set_ec(0, EC_CP15RTTRAP); + res =3D FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1); + + res =3D FIELD_DP32(res, COPROC_ISS, CV, cv); + res =3D FIELD_DP32(res, COPROC_ISS, COND, cond); + res =3D FIELD_DP32(res, COPROC_ISS, OP2, opc2); + res =3D FIELD_DP32(res, COPROC_ISS, OP1, opc1); + res =3D FIELD_DP32(res, COPROC_ISS, CRN, crn); + res =3D FIELD_DP32(res, COPROC_ISS, RT, rt); + res =3D FIELD_DP32(res, COPROC_ISS, CRM, crm); + res =3D FIELD_DP32(res, COPROC_ISS, ISREAD, isread); + + return res; } =20 +/* + * ISS encoding for an exception from an MCRR or MRRC access + * (move to/from co-processor with 2 regs) + */ +FIELD(COPROC_R2_ISS, ISREAD, 0, 1) +FIELD(COPROC_R2_ISS, CRM, 1, 4) +FIELD(COPROC_R2_ISS, RT, 5, 5) +FIELD(COPROC_R2_ISS, RT2, 10, 5) +FIELD(COPROC_R2_ISS, OP1, 16, 4) +FIELD(COPROC_R2_ISS, COND, 20, 4) +FIELD(COPROC_R2_ISS, CV, 24, 1) + static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int c= rm, int rt, int rt2, int isread, bool is_16bit) { - return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc1 << 16) - | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; + uint32_t res =3D syn_set_ec(0, EC_CP14RRTTRAP); + res =3D FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1); + + res =3D FIELD_DP32(res, COPROC_R2_ISS, CV, cv); + res =3D FIELD_DP32(res, COPROC_R2_ISS, COND, cond); + res =3D FIELD_DP32(res, COPROC_R2_ISS, OP1, opc1); + res =3D FIELD_DP32(res, COPROC_R2_ISS, RT2, rt2); + res =3D FIELD_DP32(res, COPROC_R2_ISS, RT, rt); + res =3D FIELD_DP32(res, COPROC_R2_ISS, CRM, crm); + res =3D FIELD_DP32(res, COPROC_R2_ISS, ISREAD, isread); + + return res; } =20 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int c= rm, int rt, int rt2, int isread, bool is_16bit) { - return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc1 << 16) - | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; + uint32_t res =3D syn_set_ec(0, EC_CP15RRTTRAP); + res =3D FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1); + + res =3D FIELD_DP32(res, COPROC_R2_ISS, CV, cv); + res =3D FIELD_DP32(res, COPROC_R2_ISS, COND, cond); + res =3D FIELD_DP32(res, COPROC_R2_ISS, OP1, opc1); + res =3D FIELD_DP32(res, COPROC_R2_ISS, RT2, rt2); + res =3D FIELD_DP32(res, COPROC_R2_ISS, RT, rt); + res =3D FIELD_DP32(res, COPROC_R2_ISS, CRM, crm); + res =3D FIELD_DP32(res, COPROC_R2_ISS, ISREAD, isread); + + return res; } =20 static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit, --=20 2.47.3