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Fri, 20 Mar 2026 06:06:23 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Alexander Graf , Peter Maydell , qemu-arm@nongnu.org, Pedro Barbuda , Mohamed Mediouni , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [RFC PATCH 27/35] target/arm: wrap event_register in a union Date: Fri, 20 Mar 2026 13:05:58 +0000 Message-ID: <20260320130607.2071996-28-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260320130607.2071996-1-alex.bennee@linaro.org> References: <20260320130607.2071996-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774012174450154100 While the event register is either set or not due to the implementation defined nature of bool types we can't set it directly from TCG code. By wrapping in a union we can alias a 32 bit value to the bool in a future patch. Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 9 +++++++-- hw/intc/armv7m_nvic.c | 2 +- target/arm/machine.c | 4 ++-- target/arm/tcg/m_helper.c | 4 ++-- target/arm/tcg/op_helper.c | 6 +++--- 5 files changed, 15 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index bf6cf74c2e1..9c25b60ae83 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -763,9 +763,14 @@ typedef struct CPUArchState { /* * The event register is shared by all ARM profiles (A/R/M), * so it is stored in the top-level CPU state. - * WFE/SEV handling is currently implemented only for M-profile. + * + * It is treated as a boolean but we need the union so we can set + * it from TCG. */ - bool event_register; + union { + bool as_bool; + uint32_t as_uint32; + } event_register; =20 /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index a7651f831eb..d630f80e51a 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -238,7 +238,7 @@ static void nvic_update_pending_state(NVICState *s, Vec= Info *vec, int scr_bank =3D exc_targets_secure(s, irq) ? M_REG_S : M_REG_NS; /* SEVONPEND: interrupt going to pending is a WFE wakeup event */ if (s->cpu->env.v7m.scr[scr_bank] & R_V7M_SCR_SEVONPEND_MASK) { - s->cpu->env.event_register =3D true; + s->cpu->env.event_register.as_bool =3D true; qemu_cpu_kick(CPU(s->cpu)); } } diff --git a/target/arm/machine.c b/target/arm/machine.c index b0e499515cf..844e6a37c77 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -514,7 +514,7 @@ static bool event_needed(void *opaque) { ARMCPU *cpu =3D opaque; =20 - return cpu->env.event_register; + return cpu->env.event_register.as_bool; } =20 static const VMStateDescription vmstate_event =3D { @@ -523,7 +523,7 @@ static const VMStateDescription vmstate_event =3D { .minimum_version_id =3D 1, .needed =3D event_needed, .fields =3D (const VMStateField[]) { - VMSTATE_BOOL(env.event_register, ARMCPU), + VMSTATE_BOOL(env.event_register.as_bool, ARMCPU), VMSTATE_END_OF_LIST() } }; diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index a0cb8cb021e..3259e624e02 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -964,7 +964,7 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t l= r, bool dotailchain, * take (which might now be the derived exception). * Exception entry sets the event register (ARM ARM R_BPBR) */ - env->event_register =3D true; + env->event_register.as_bool =3D true; armv7m_nvic_acknowledge_irq(env->nvic); =20 /* Switch to target security state -- must do this before writing SPSE= L */ @@ -1910,7 +1910,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) arm_rebuild_hflags(env); =20 /* Exception return sets the event register (ARM ARM R_BPBR) */ - env->event_register =3D true; + env->event_register.as_bool =3D true; qemu_log_mask(CPU_LOG_INT, "...successful exception return\n"); } =20 diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 635c538ed4b..b5c8024ace7 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -476,7 +476,7 @@ void HELPER(sev)(CPUARMState *env) CPU_FOREACH(cs) { ARMCPU *target_cpu =3D ARM_CPU(cs); if (arm_feature(&target_cpu->env, ARM_FEATURE_M)) { - target_cpu->env.event_register =3D true; + target_cpu->env.event_register.as_bool =3D true; } if (!qemu_cpu_is_self(cs)) { qemu_cpu_kick(cs); @@ -503,8 +503,8 @@ void HELPER(wfe)(CPUARMState *env) if (arm_feature(env, ARM_FEATURE_M)) { CPUState *cs =3D env_cpu(env); =20 - if (env->event_register) { - env->event_register =3D false; + if (env->event_register.as_bool) { + env->event_register.as_bool =3D false; return; } =20 --=20 2.47.3