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Fri, 20 Mar 2026 06:06:09 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Alexander Graf , Peter Maydell , qemu-arm@nongnu.org, Pedro Barbuda , Mohamed Mediouni , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [RFC PATCH 01/35] target/arm: migrate basic syndrome helpers to registerfields Date: Fri, 20 Mar 2026 13:05:32 +0000 Message-ID: <20260320130607.2071996-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260320130607.2071996-1-alex.bennee@linaro.org> References: <20260320130607.2071996-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774012079190154100 We have a registerfields interface which we can use for defining fields alongside helpers to access them. Define the basic syndrome layout and convert the helpers that take the imm16 data directly. Signed-off-by: Alex Benn=C3=A9e --- target/arm/syndrome.h | 75 ++++++++++++++++++++++++++++++++----------- 1 file changed, 57 insertions(+), 18 deletions(-) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index bff61f052cc..517fb2368bc 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -25,7 +25,7 @@ #ifndef TARGET_ARM_SYNDROME_H #define TARGET_ARM_SYNDROME_H =20 -#include "qemu/bitops.h" +#include "hw/core/registerfields.h" =20 /* Valid Syndrome Register EC field values */ enum arm_exception_class { @@ -76,6 +76,11 @@ enum arm_exception_class { EC_AA64_BKPT =3D 0x3c, }; =20 +/* Generic syndrome encoding layout for HSR and lower 32 bits of ESR_EL2 */ +FIELD(SYNDROME, EC, 26, 6) +FIELD(SYNDROME, IL, 25, 1) +FIELD(SYNDROME, ISS, 0, 25) + typedef enum { SME_ET_AccessTrap, SME_ET_Streaming, @@ -113,12 +118,12 @@ typedef enum { =20 static inline uint32_t syn_get_ec(uint32_t syn) { - return syn >> ARM_EL_EC_SHIFT; + return FIELD_EX32(syn, SYNDROME, EC); } =20 static inline uint32_t syn_set_ec(uint32_t syn, uint32_t ec) { - return deposit32(syn, ARM_EL_EC_SHIFT, ARM_EL_EC_LENGTH, ec); + return FIELD_DP32(syn, SYNDROME, EC, ec); } =20 /* @@ -133,49 +138,74 @@ static inline uint32_t syn_set_ec(uint32_t syn, uint3= 2_t ec) */ static inline uint32_t syn_uncategorized(void) { - return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL; + uint32_t res =3D syn_set_ec(0, EC_UNCATEGORIZED); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + return res; } =20 +FIELD(ISS_IMM16, IMM16, 0, 16) + static inline uint32_t syn_aa64_svc(uint32_t imm16) { - return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); + uint32_t res =3D syn_set_ec(0, EC_AA64_SVC); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + res =3D FIELD_DP32(res, ISS_IMM16, IMM16, imm16); + return res; } =20 static inline uint32_t syn_aa64_hvc(uint32_t imm16) { - return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); + uint32_t res =3D syn_set_ec(0, EC_AA64_HVC); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + res =3D FIELD_DP32(res, ISS_IMM16, IMM16, imm16); + return res; } =20 static inline uint32_t syn_aa64_smc(uint32_t imm16) { - return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); + uint32_t res =3D syn_set_ec(0, EC_AA64_SMC); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + res =3D FIELD_DP32(res, ISS_IMM16, IMM16, imm16); + return res; } =20 static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) { - return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) - | (is_16bit ? 0 : ARM_EL_IL); + uint32_t res =3D syn_set_ec(0, EC_AA32_SVC); + res =3D FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1); + res =3D FIELD_DP32(res, ISS_IMM16, IMM16, imm16); + return res; } =20 static inline uint32_t syn_aa32_hvc(uint32_t imm16) { - return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); + uint32_t res =3D syn_set_ec(0, EC_AA32_HVC); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + res =3D FIELD_DP32(res, ISS_IMM16, IMM16, imm16); + return res; } =20 static inline uint32_t syn_aa32_smc(void) { - return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL; + uint32_t res =3D syn_set_ec(0, EC_AA32_SMC); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + return res; } =20 static inline uint32_t syn_aa64_bkpt(uint32_t imm16) { - return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff= ); + uint32_t res =3D syn_set_ec(0, EC_AA64_BKPT); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + res =3D FIELD_DP32(res, ISS_IMM16, IMM16, imm16); + return res; } =20 static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) { - return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) - | (is_16bit ? 0 : ARM_EL_IL); + uint32_t res =3D syn_set_ec(0, EC_AA32_BKPT); + res =3D FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1); + res =3D FIELD_DP32(res, ISS_IMM16, IMM16, imm16); + return res; } =20 static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, @@ -246,7 +276,9 @@ static inline uint32_t syn_simd_access_trap(int cv, int= cond, bool is_16bit) =20 static inline uint32_t syn_sve_access_trap(void) { - return (EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL; + uint32_t res =3D syn_set_ec(0, EC_SVEACCESSTRAP); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + return res; } =20 /* @@ -361,12 +393,16 @@ static inline uint32_t syn_wfx(int cv, int cond, int = ti, bool is_16bit) =20 static inline uint32_t syn_illegalstate(void) { - return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL; + uint32_t res =3D syn_set_ec(0, EC_ILLEGALSTATE); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + return res; } =20 static inline uint32_t syn_pcalignment(void) { - return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; + uint32_t res =3D syn_set_ec(0, EC_PCALIGNMENT); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + return res; } =20 static inline uint32_t syn_gcs_data_check(GCSInstructionType it, int rn) @@ -388,7 +424,10 @@ static inline uint32_t syn_gcs_gcsstr(int ra, int rn) =20 static inline uint32_t syn_serror(uint32_t extra) { - return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra; + uint32_t res =3D syn_set_ec(0, EC_SERROR); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + res =3D FIELD_DP32(res, SYNDROME, ISS, extra); + return res; } =20 static inline uint32_t syn_mop(bool is_set, bool is_setg, int options, --=20 2.47.3