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Fri, 20 Mar 2026 06:06:15 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Alexander Graf , Peter Maydell , qemu-arm@nongnu.org, Pedro Barbuda , Mohamed Mediouni , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [RFC PATCH 10/35] target/arm: migrate fault syndromes to registerfields Date: Fri, 20 Mar 2026 13:05:41 +0000 Message-ID: <20260320130607.2071996-11-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260320130607.2071996-1-alex.bennee@linaro.org> References: <20260320130607.2071996-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1774012135750154100 Migrate syn_insn_abort and syn_data_abort_* to the registerfields API. Signed-off-by: Alex Benn=C3=A9e --- target/arm/syndrome.h | 87 ++++++++++++++++++++++++++++++++++++------- 1 file changed, 74 insertions(+), 13 deletions(-) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 3fd82f5b565..db92a8020e3 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -494,20 +494,64 @@ static inline uint32_t syn_gpc(int s2ptw, int ind, in= t gpcsc, int vncr, return res; } =20 +/* + * ISS encoding for an exception from an Instruction Abort + * + * (aka instruction abort) + */ +FIELD(IABORT_ISS, IFSC, 0, 6) +FIELD(IABORT_ISS, S1PTW, 7, 1) +FIELD(IABORT_ISS, EA, 9, 1) +FIELD(IABORT_ISS, FnV, 10, 1) /* FAR not Valid */ +FIELD(IABORT_ISS, SET, 11, 2) +FIELD(IABORT_ISS, PFV, 14, 1) +FIELD(IABORT_ISS, TopLevel, 21, 1) /* FEAT_THE */ + static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int = fsc) { - return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) - | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc; + uint32_t res =3D syn_set_ec(0, EC_INSNABORT + same_el); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + + res =3D FIELD_DP32(res, IABORT_ISS, EA, ea); + res =3D FIELD_DP32(res, IABORT_ISS, S1PTW, s1ptw); + res =3D FIELD_DP32(res, IABORT_ISS, IFSC, fsc); + + return res; } =20 +/* + * ISS encoding for an exception from a Data Abort + */ +FIELD(DABORT_ISS, DFSC, 0, 6) +FIELD(DABORT_ISS, WNR, 6, 1) +FIELD(DABORT_ISS, S1PTW, 7, 1) +FIELD(DABORT_ISS, CM, 8, 1) +FIELD(DABORT_ISS, EA, 9, 1) +FIELD(DABORT_ISS, FnV, 10, 1) +FIELD(DABORT_ISS, LST, 11, 2) +FIELD(DABORT_ISS, VNCR, 13, 1) +FIELD(DABORT_ISS, AR, 14, 1) +FIELD(DABORT_ISS, SF, 15, 1) +FIELD(DABORT_ISS, SRT, 16, 5) +FIELD(DABORT_ISS, SSE, 21, 1) +FIELD(DABORT_ISS, SAS, 22, 2) +FIELD(DABORT_ISS, ISV, 24, 1) + static inline uint32_t syn_data_abort_no_iss(int same_el, int fnv, int ea, int cm, int s1ptw, int wnr, int fsc) { - return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) - | ARM_EL_IL - | (fnv << 10) | (ea << 9) | (cm << 8) | (s1ptw << 7) - | (wnr << 6) | fsc; + uint32_t res =3D syn_set_ec(0, EC_DATAABORT + same_el); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + + res =3D FIELD_DP32(res, DABORT_ISS, FnV, fnv); + res =3D FIELD_DP32(res, DABORT_ISS, EA, ea); + res =3D FIELD_DP32(res, DABORT_ISS, CM, cm); + res =3D FIELD_DP32(res, DABORT_ISS, S1PTW, s1ptw); + res =3D FIELD_DP32(res, DABORT_ISS, WNR, wnr); + res =3D FIELD_DP32(res, DABORT_ISS, DFSC, fsc); + + return res; } =20 static inline uint32_t syn_data_abort_with_iss(int same_el, @@ -517,11 +561,22 @@ static inline uint32_t syn_data_abort_with_iss(int sa= me_el, int wnr, int fsc, bool is_16bit) { - return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16) - | (sf << 15) | (ar << 14) - | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; + uint32_t res =3D syn_set_ec(0, EC_DATAABORT + same_el); + res =3D FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1); + + res =3D FIELD_DP32(res, DABORT_ISS, ISV, 1); + res =3D FIELD_DP32(res, DABORT_ISS, SAS, sas); + res =3D FIELD_DP32(res, DABORT_ISS, SSE, sse); + res =3D FIELD_DP32(res, DABORT_ISS, SRT, srt); + res =3D FIELD_DP32(res, DABORT_ISS, SF, sf); + res =3D FIELD_DP32(res, DABORT_ISS, AR, ar); + res =3D FIELD_DP32(res, DABORT_ISS, EA, ea); + res =3D FIELD_DP32(res, DABORT_ISS, CM, cm); + res =3D FIELD_DP32(res, DABORT_ISS, S1PTW, s1ptw); + res =3D FIELD_DP32(res, DABORT_ISS, WNR, wnr); + res =3D FIELD_DP32(res, DABORT_ISS, DFSC, fsc); + + return res; } =20 /* @@ -530,8 +585,14 @@ static inline uint32_t syn_data_abort_with_iss(int sam= e_el, */ static inline uint32_t syn_data_abort_vncr(int ea, int wnr, int fsc) { - return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (1 << ARM_EL_EC_SHIFT) - | ARM_EL_IL | ARM_EL_VNCR | (wnr << 6) | fsc; + uint32_t res =3D syn_set_ec(0, EC_DATAABORT_SAME_EL); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + + res =3D FIELD_DP32(res, DABORT_ISS, VNCR, 1); + res =3D FIELD_DP32(res, DABORT_ISS, WNR, wnr); + res =3D FIELD_DP32(res, DABORT_ISS, DFSC, fsc); + + return res; } =20 static inline uint32_t syn_swstep(int same_el, int isv, int ex) --=20 2.47.3