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Fri, 20 Mar 2026 00:46:08 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , Richard Henderson , Anton Johansson , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH 1/2] target/mips: Inline cpu_ld{uw, l}_code() calls in set_badinstr_registers Date: Fri, 20 Mar 2026 08:45:54 +0100 Message-ID: <20260320074555.33974-2-philmd@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260320074555.33974-1-philmd@linaro.org> References: <20260320074555.33974-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1773992800978154100 In preparation of removing the cpu_lduw_code() and cpu_ldl_code() wrappers, inline them. Directly replace MO_TE by mo_endian_env(env). Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/system/tlb_helper.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/target/mips/tcg/system/tlb_helper.c b/target/mips/tcg/system/t= lb_helper.c index 566924b079e..b989c7e5bd5 100644 --- a/target/mips/tcg/system/tlb_helper.c +++ b/target/mips/tcg/system/tlb_helper.c @@ -999,16 +999,22 @@ static void set_hflags_for_handler(CPUMIPSState *env) =20 static inline void set_badinstr_registers(CPUMIPSState *env) { + CPUState *cs =3D env_cpu(env); + MemOpIdx oi; + if (env->insn_flags & ISA_NANOMIPS32) { if (env->CP0_Config3 & (1 << CP0C3_BI)) { - uint32_t instr =3D (cpu_lduw_code(env, env->active_tc.PC)) << = 16; + uint32_t instr; + + oi =3D make_memop_idx(mo_endian_env(env) | MO_UW, cpu_mmu_inde= x(cs, true)); + instr =3D cpu_ldw_code_mmu(env, env->active_tc.PC, oi, 0) << = 16; if ((instr & 0x10000000) =3D=3D 0) { - instr |=3D cpu_lduw_code(env, env->active_tc.PC + 2); + instr |=3D cpu_ldw_code_mmu(env, env->active_tc.PC + 2, oi= , 0); } env->CP0_BadInstr =3D instr; =20 if ((instr & 0xFC000000) =3D=3D 0x60000000) { - instr =3D cpu_lduw_code(env, env->active_tc.PC + 4) << 16; + instr =3D cpu_ldw_code_mmu(env, env->active_tc.PC + 4, oi= , 0) << 16; env->CP0_BadInstrX =3D instr; } } @@ -1019,12 +1025,14 @@ static inline void set_badinstr_registers(CPUMIPSSt= ate *env) /* TODO: add BadInstr support for microMIPS */ return; } + + oi =3D make_memop_idx(mo_endian_env(env) | MO_UL, cpu_mmu_index(cs, tr= ue)); if (env->CP0_Config3 & (1 << CP0C3_BI)) { - env->CP0_BadInstr =3D cpu_ldl_code(env, env->active_tc.PC); + env->CP0_BadInstr =3D cpu_ldl_code_mmu(env, env->active_tc.PC, oi,= 0); } if ((env->CP0_Config3 & (1 << CP0C3_BP)) && (env->hflags & MIPS_HFLAG_BMASK)) { - env->CP0_BadInstrP =3D cpu_ldl_code(env, env->active_tc.PC - 4); + env->CP0_BadInstrP =3D cpu_ldl_code_mmu(env, env->active_tc.PC - 4= , oi, 0); } } =20 --=20 2.53.0