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Thu, 19 Mar 2026 05:13:23 -0700 (PDT) From: Jim MacArthur Date: Thu, 19 Mar 2026 12:12:42 +0000 Subject: [PATCH RFC 2/2] tcg/aarch64/tcg-target.c.inc: Manual replace of I3310, I3313 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260319-aarch64-tcg-instruction-format-rename-v1-2-8a13bf98f8ff@linaro.org> References: <20260319-aarch64-tcg-instruction-format-rename-v1-0-8a13bf98f8ff@linaro.org> In-Reply-To: <20260319-aarch64-tcg-instruction-format-rename-v1-0-8a13bf98f8ff@linaro.org> To: qemu-devel@nongnu.org Cc: Richard Henderson , qemu-arm@nongnu.org, Jim MacArthur X-Mailer: b4 0.13.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=jim.macarthur@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1773922494961158500 These are not formats in themselves, but extra constants to OR in with the existing ldst_imm format. Signed-off-by: Jim MacArthur --- tcg/aarch64/tcg-target.c.inc | 64 +++++++++++++++++++++++++---------------= ---- 1 file changed, 36 insertions(+), 28 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index e9f86176d2..1f59d40a77 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -458,8 +458,9 @@ typedef enum { Ildst_imm_LDRVQ =3D 0x3c000000 | 3 << 22 | 0 << 30, Ildst_imm_STRVQ =3D 0x3c000000 | 2 << 22 | 0 << 30, =20 - Ildst_imm_TO_I3310 =3D 0x00200800, - Ildst_imm_TO_I3313 =3D 0x01000000, + /* Additions to the ldst_imm format */ + ldst_imm_to_sign_extend =3D 0x00200800, + ldst_imm_to_uimm =3D 0x01000000, =20 /* Load/store register pair instructions. */ Ildstpair_LDP =3D 0x28400000, @@ -880,12 +881,12 @@ static void tcg_out_insn_qrr_e(TCGContext *s, AArch64= Insn insn, bool q, | (rn & 0x1f) << 5 | (rd & 0x1f)); } =20 -static void tcg_out_insn_3310(TCGContext *s, AArch64Insn insn, - TCGReg rd, TCGReg base, TCGType ext, - TCGReg regoff) +static void tcg_out_insn_ldst_sign_extend(TCGContext *s, AArch64Insn insn, + TCGReg rd, TCGReg base, TCGType = ext, + TCGReg regoff) { /* Note the AArch64Insn constants above are for C3.3.12. Adjust. */ - tcg_out32(s, insn | Ildst_imm_TO_I3310 | regoff << 16 | + tcg_out32(s, insn | ldst_imm_to_sign_extend | regoff << 16 | 0x4000 | ext << 13 | base << 5 | (rd & 0x1f)); } =20 @@ -895,11 +896,11 @@ static void tcg_out_insn_ldst_imm(TCGContext *s, AArc= h64Insn insn, tcg_out32(s, insn | (offset & 0x1ff) << 12 | rn << 5 | (rd & 0x1f)); } =20 -static void tcg_out_insn_3313(TCGContext *s, AArch64Insn insn, - TCGReg rd, TCGReg rn, uintptr_t scaled_uimm) +static void tcg_out_insn_ldst_uimm(TCGContext *s, AArch64Insn insn, + TCGReg rd, TCGReg rn, uintptr_t scaled_= uimm) { /* Note the AArch64Insn constants above are for C3.3.12. Adjust. */ - tcg_out32(s, insn | Ildst_imm_TO_I3313 | scaled_uimm << 10 + tcg_out32(s, insn | ldst_imm_to_uimm | scaled_uimm << 10 | rn << 5 | (rd & 0x1f)); } =20 @@ -1203,9 +1204,6 @@ static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd= , TCGReg rs, g_assert_not_reached(); } =20 -/* Define something more legible for general use. */ -#define tcg_out_ldst_r tcg_out_insn_3310 - static void tcg_out_ldst(TCGContext *s, AArch64Insn insn, TCGReg rd, TCGReg rn, intptr_t offset, int lgsize) { @@ -1214,7 +1212,7 @@ static void tcg_out_ldst(TCGContext *s, AArch64Insn i= nsn, TCGReg rd, if (offset >=3D 0 && !(offset & ((1 << lgsize) - 1))) { uintptr_t scaled_uimm =3D offset >> lgsize; if (scaled_uimm <=3D 0xfff) { - tcg_out_insn_3313(s, insn, rd, rn, scaled_uimm); + tcg_out_insn_ldst_uimm(s, insn, rd, rn, scaled_uimm); return; } } @@ -1227,7 +1225,7 @@ static void tcg_out_ldst(TCGContext *s, AArch64Insn i= nsn, TCGReg rd, =20 /* Worst-case scenario, move offset to temp register, use reg offset. = */ tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, offset); - tcg_out_ldst_r(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP0); + tcg_out_insn_ldst_sign_extend(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_T= MP0); } =20 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) @@ -1764,28 +1762,34 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, M= emOp memop, TCGType ext, { switch (memop & MO_SSIZE) { case MO_UB: - tcg_out_ldst_r(s, Ildst_imm_LDRB, data_r, h.base, h.index_ext, h.i= ndex); + tcg_out_insn_ldst_sign_extend(s, Ildst_imm_LDRB, data_r, h.base, + h.index_ext, h.index); break; case MO_SB: - tcg_out_ldst_r(s, ext ? Ildst_imm_LDRSBX : Ildst_imm_LDRSBW, - data_r, h.base, h.index_ext, h.index); + tcg_out_insn_ldst_sign_extend(s, + ext ? Ildst_imm_LDRSBX : Ildst_imm_L= DRSBW, + data_r, h.base, h.index_ext, h.index= ); break; case MO_UW: - tcg_out_ldst_r(s, Ildst_imm_LDRH, data_r, h.base, h.index_ext, h.i= ndex); + tcg_out_insn_ldst_sign_extend(s, Ildst_imm_LDRH, data_r, h.base, + h.index_ext, h.index); break; case MO_SW: - tcg_out_ldst_r(s, (ext ? Ildst_imm_LDRSHX : Ildst_imm_LDRSHW), - data_r, h.base, h.index_ext, h.index); + tcg_out_insn_ldst_sign_extend(s, + ext ? Ildst_imm_LDRSHX : Ildst_imm_L= DRSHW, + data_r, h.base, h.index_ext, h.index= ); break; case MO_UL: - tcg_out_ldst_r(s, Ildst_imm_LDRW, data_r, h.base, h.index_ext, h.i= ndex); + tcg_out_insn_ldst_sign_extend(s, Ildst_imm_LDRW, data_r, h.base, + h.index_ext, h.index); break; case MO_SL: - tcg_out_ldst_r(s, Ildst_imm_LDRSWX, data_r, h.base, h.index_ext, - h.index); + tcg_out_insn_ldst_sign_extend(s, Ildst_imm_LDRSWX, data_r, h.base, + h.index_ext, h.index); break; case MO_UQ: - tcg_out_ldst_r(s, Ildst_imm_LDRX, data_r, h.base, h.index_ext, h.i= ndex); + tcg_out_insn_ldst_sign_extend(s, Ildst_imm_LDRX, data_r, h.base, + h.index_ext, h.index); break; default: g_assert_not_reached(); @@ -1797,16 +1801,20 @@ static void tcg_out_qemu_st_direct(TCGContext *s, M= emOp memop, { switch (memop & MO_SIZE) { case MO_8: - tcg_out_ldst_r(s, Ildst_imm_STRB, data_r, h.base, h.index_ext, h.i= ndex); + tcg_out_insn_ldst_sign_extend(s, Ildst_imm_STRB, data_r, h.base, + h.index_ext, h.index); break; case MO_16: - tcg_out_ldst_r(s, Ildst_imm_STRH, data_r, h.base, h.index_ext, h.i= ndex); + tcg_out_insn_ldst_sign_extend(s, Ildst_imm_STRH, data_r, h.base, + h.index_ext, h.index); break; case MO_32: - tcg_out_ldst_r(s, Ildst_imm_STRW, data_r, h.base, h.index_ext, h.i= ndex); + tcg_out_insn_ldst_sign_extend(s, Ildst_imm_STRW, data_r, h.base, + h.index_ext, h.index); break; case MO_64: - tcg_out_ldst_r(s, Ildst_imm_STRX, data_r, h.base, h.index_ext, h.i= ndex); + tcg_out_insn_ldst_sign_extend(s, Ildst_imm_STRX, data_r, h.base, + h.index_ext, h.index); break; default: g_assert_not_reached(); --=20 2.43.0