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Wed, 18 Mar 2026 11:53:26 -0700 (PDT) From: luisccc To: qemu-devel@nongnu.org Cc: luisccc , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) Subject: [RFC PATCH 4/6] target/riscv: Implement extension for Optimizing Context Switching (Sspmpen) Date: Wed, 18 Mar 2026 18:52:34 +0000 Message-ID: <20260318185238.99143-5-luisccunha8@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260318185238.99143-1-luisccunha8@gmail.com> References: <20260318185238.99143-1-luisccunha8@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=luisccunha8@gmail.com; helo=mail-wm1-x333.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Wed, 18 Mar 2026 15:44:18 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773863133904154100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Luis Cunha --- target/riscv/cpu_bits.h | 4 ++ target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/csr.c | 67 +++++++++++++++++++++++++++++++ target/riscv/spmp.c | 6 ++- 4 files changed, 77 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 36f7c1e873..0a8cfedc5d 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -255,6 +255,10 @@ #define CSR_SCTRSTATUS 0x14f #define CSR_SCTRDEPTH 0x15f =20 +/* S-mode Physical Memory Protection (SPMP) */ +#define CSR_SPMPEN 0x183 +#define CSR_SPMPENH 0x193 + /* VS-Level Control transfer records CSRs */ #define CSR_VSCTRCTL 0x24e =20 diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index 772cc176d0..88edac21ca 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -120,6 +120,7 @@ BOOL_FIELD(rvv_ma_all_1s) BOOL_FIELD(rvv_vl_half_avl) BOOL_FIELD(rvv_vsetvl_x0_vill) BOOL_FIELD(ext_smpmpdeleg) +BOOL_FIELD(ext_sspmpen) /* Named features */ BOOL_FIELD(ext_svade) BOOL_FIELD(ext_zic64b) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4b9fa11540..a11d7e6704 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -769,6 +769,16 @@ static RISCVException spmp(CPURISCVState *env, int csr= no) return smode(env, csrno); } =20 +static RISCVException sspmpen(CPURISCVState *env, int csrno) +{ + if (!riscv_cpu_cfg(env)->ext_sspmpen) { + return RISCV_EXCP_ILLEGAL_INST; + } + + /* SSPMPEN can only exist, if spmp exists */ + return spmp(env, csrno); +} + static RISCVException have_mseccfg(CPURISCVState *env, int csrno) { if (riscv_cpu_cfg(env)->ext_smepmp) { @@ -5389,6 +5399,61 @@ static RISCVException rmw_mpmpdeleg(CPURISCVState *e= nv, int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException rmw_spmpen64(CPURISCVState *env, int csrno, + uint64_t *ret_val, + uint64_t new_val, uint64_t wr_mask) +{ + uint64_t new_spmpen =3D (env->spmp_state.spmpen & ~wr_mask) | + (new_val & wr_mask); + + if (env->spmp_state.num_deleg_rules =3D=3D 0) { + if (ret_val) { + *ret_val =3D 0; + } + + return RISCV_EXCP_NONE; + } + + if (ret_val) { + *ret_val =3D env->spmp_state.spmpen; + } + + sspmpen_csr_write(env, new_spmpen); + + return RISCV_EXCP_NONE; +} + +static RISCVException rmw_spmpen(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_ma= sk) +{ + uint64_t rval =3D 0; + RISCVException ret; + ret =3D rmw_spmpen64(env, csrno, &rval, new_val, wr_mask); + if (ret_val) { + *ret_val =3D rval; + } + + return ret; +} + +static RISCVException rmw_spmpenh(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, + target_ulong wr_mask) +{ + uint64_t rval =3D 0; + RISCVException ret; + + ret =3D rmw_spmpen64(env, csrno, &rval, + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); + if (ret_val) { + *ret_val =3D rval >> 32; + } + + return ret; +} + static RISCVException read_tselect(CPURISCVState *env, int csrno, target_ulong *val) { @@ -6388,6 +6453,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { =20 /* S-mode Physical Memory Protection */ [CSR_MPMPDELEG] =3D { "mpmpdeleg", spmp, NULL, NULL, rmw_mpmpdeleg }, + [CSR_SPMPEN] =3D { "spmpen", sspmpen, NULL, NULL, rmw_spmpen }, + [CSR_SPMPENH] =3D { "spmpenh", sspmpen, NULL, NULL, rmw_spmpenh }, =20 /* Debug CSRs */ [CSR_TSELECT] =3D { "tselect", debug, read_tselect, write_tselect= }, diff --git a/target/riscv/spmp.c b/target/riscv/spmp.c index 85c5259b33..1615c207df 100644 --- a/target/riscv/spmp.c +++ b/target/riscv/spmp.c @@ -147,7 +147,11 @@ static uint8_t spmp_is_in_range(CPURISCVState *env, in= t spmp_index, =20 static bool spmp_get_spmpen_bit(CPURISCVState *env, int index) { - return true; + if (!riscv_cpu_cfg(env)->ext_sspmpen) { + return true; + } + + return (env->spmp_state.spmpen >> index) & 0x1; } =20 /* --=20 2.43.0